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The surge in demand for 3D MOSFETs, such as FinFETs, driven by recent technological advances, is explored in this review. FinFETs, positioned as promising alternatives to bulk CMOS, exhibit favorable electrostatic characteristics and offer power/performance benefits, scalability, and control over short-channel effects. Simulations provide insights into functionality and leakage, addressing off-current issues common in narrow band-gap materials within a CMOS-compatible process. Multiple structures have been introduced for FinFETs. Moreover, some studies on the fabrication of FinFETs using different materials have been discussed. Despite their potential, challenges like corner effects, quantum effects, width quantization, layout dependencies, and parasitics have been acknowledged. In the post-planar CMOS landscape, FinFETs show potential for scalability in nanoscale CMOS, which leads to novel structures for them. Finally, recent developments in FinFET-based sensors are discussed. In a general view, this comprehensive review delves into the intricacies of FinFET fabrication, exploring historical development, classifications, and cutting-edge ideas for the used materials and FinFET application, i.e., sensing. [ABSTRACT FROM AUTHOR]

Featured Application: Metal gate of CMOS devices. The continuous down-scaling of complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) had been suffering two fateful technical issues, one relative to the thinning of gate dielectric and the other to the aggressive shortening of channel in last 20 years. To solve the first issue, the high-κ dielectric and metal gate technology had been induced to replace the conventional gate stack of silicon dioxide layer and poly-silicon. To suppress the short channel effects, device architecture had changed from planar bulk Si device to fully depleted silicon on insulator (FDSOI) and FinFETs, and will transit to gate all-around FETs (GAA-FETs). Different from the planar devices, the FinFETs and GAA-FETs have a 3D channel. The conventional high-κ/metal gate process using sputtering faces conformality difficulty, and all atomic layer deposition (ALD) of gate stack become necessary. This review covers both scientific and technological parts related to the ALD of metal gates including the concept of effect work function, the material selection, the precursors for the deposition, the threshold voltage (Vt) tuning of the metal gate in contact with HfO2/SiO2/Si. The ALD of n-type metal gate will be detailed systematically, based mainly on the authors' works in last five years, and the all ALD gate stacks will be proposed for the future generations based on the learning. [ABSTRACT FROM AUTHOR]

An analytical model for the silicon-on-insulator (SOI) tunnel field-effect transistor (FET) with linearly graded workfunction-modulated gate is proposed to improve device performance through subthreshold slope (SS) optimization. The surface potential of the suggested model is analyzed using the two-dimensional (2-D) Poisson equation with imposed channel boundary conditions. Other electrical parameters such as the electric field, drain current, transconductance, and SS are evaluated to examine the performance of the model. Moreover, the performance in terms of the SS and $$I_{60}$$ values for the proposed model with downscaling of gate oxide thickness and silicon body thickness are also investigated and the results compared with results for a conventional tunnel FET (TFET) model. The present model exhibits significant reduction in subthreshold slope ( $$\sim 14\,\hbox {mV/decade}$$ ) and improvement in $$I_{60} $$ performance. The accuracy of the model is verified against 2-D technology computer-aided design (TCAD) model simulations. [ABSTRACT FROM AUTHOR]

This paper presents a novel TaN-Al2O3-HfSiOx-SiO2-silicon (TAHOS) nonvolatile memory (NVM) design with dipole engineering at the HfSiOx/SiO2 interface. The threshold voltage shift achieved by using dipole engineering could enable work function adjustment for NVM devices. The dipole layer at the tunnel oxide-charge storage layer interface increases the programming speed and provides satisfactory retention. This NVM device has a high program/erase (P/E) speed; a 2-V memory window can be achieved by applying 16 V for 10 μs. Regarding high-temperature retention characteristics, 62% of the initial memory window was maintained after 103 P/E-cycle stress in a 10-year simulation. This paper discusses the performance improvement enabled by using dipole layer engineering in the TAHOS NVM. [ABSTRACT FROM AUTHOR]

NOR/AND flash memory was studied in neuromorphic systems to perform vector-by-matrix multiplication (VMM) by summing the current. Because the size of NOR/AND cells exceeds those of other memristor synaptic devices, we proposed a 3D AND-type stacked array to reduce the cell size. Through a tilted implantation method, the conformal sources and drains of each cell could be formed, with confirmation by a technology computer aided design (TCAD) simulation. In addition, the cell-to-cell variation due to the etch slope could be eliminated by controlling the deposition thickness of the cells. The suggested array can be beneficial in simple program/inhibit schemes given its use of Fowler–Nordheim (FN) tunneling because the drain lines and source lines are parallel. Therefore, the conductance of each synaptic device can be updated at low power level. [ABSTRACT FROM AUTHOR]