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In this paper, we extend our previous methodology for designing a family of low-error area-efficient fixed-width two's-complement multipliers that receive two n-bit numbers and produce an n-bit product. The generalized methodology involving four steps results in several better error-compensation biases. These better error-compensation biases can be easily mapped to low-error area-efficient fixed-width multipliers suitable for very large-scale integration implementation and digital signal processing application. Via the proposed Type 18 x 8 fixed-width multiplier, the reduction of the average error can be improved by 88% compared with the direct-truncated (D-Truncated) multiplier. It is also shown that the same proposed multiplier leads to 32.75% reduction in area compared with the standard multiplier. Index Terms--Area efficient, Baugh-Wooley algorithm, fixed-width multiplier, truncation error.

In this paper, we propose an efficient systolic architecture for the delay least-mean-square (DLMS) adaptive finite impulse response (FIR) digital filter based on a new tree-systolic processing element (PE) and an optimized tree-level rule. Applying our tree-systolic PE, a higher convergence rate than that of the conventional DLMS structures can be obtained without sacrificing the properties of the systolic-array architecture. The efficient systolic adaptive FIR digital filter not only operates at the highest throughput in the word-level but also considers finite driving/update of the feedback error signal. Furthermore, based on our proposed optimized tree-level rule that takes account of minimum delay and high regularity, an efficient N-tap systolic adaptive FIR digital filter can be easily determined under the constraint of maximum driving of the feedback error signal. Index Terms--Adaptive filter, DLMS algorithm, equalization, system identification, systolic architecture.

This brief develops a general methodology for designing a lower-error two's-complement fixed-width multiplier that receives two n-bit numbers and produces an n-bit product. By properly choosing the generalized index, we derive the better error-compensation bias to reduce the truncation error and then construct a lower error fixed-width multiplier, which is area efficient for VLSI implementation. Finally, we successfully apply the proposed fixed-width multiplier to realizing a digital FIR filter, which has shown that the performance is better than that using other fixed-width multipliers. Index Terms--Area-efficient, fixed-width multiplier, speech processing, truncation error.

This paper presents an energy-efficient fast independent component analysis (FastICA) implementation with an early determination scheme for eight-channel electroencephalogram (EEG) signal separation. The main contributions are as follows: 1) energy-efficient FastICA using the proposed early determination scheme and the corresponding architecture; 2) cost-effective FastICA using the proposed preprocessing unit architecture with one coordinate rotation digital computer-based eigenvalue decomposition processor and the proposed one-unit architecture with the hardware reuse scheme; and 3) low-computation-time FastICA using the four parallel one-units architecture. The resulting power dissipation of the FastICA implementation for eight-channel EEG signal separation is 16.35 mW at 100 MHz at 1.0 V. Compared with the design without early determination, the proposed FastICA architecture implemented in united microelectronics corporation 90 nm 1P9M complementary metal–oxide–semiconductor process with a core area of 1.221\,\times\,1.218 mm^2 can achieve average energy reduction by 47.63%. From the post-layout simulation results, the maximum computation time is 0.29 s. [ABSTRACT FROM AUTHOR]

The daily experience of mental stress profoundly influences our health and work performance while concurrently triggering alterations in brain electrical activity. Electroencephalogram (EEG) is a widely adopted method for assessing cognitive and affective states. This study delves into the EEG correlates of stress and the potential use of resting EEG in evaluating stress levels. Over 13 weeks, our longitudinal study focuses on the real-life experiences of college students, collecting data from each of the 18 participants across multiple days in classroom settings. To tackle the complexity arising from the multitude of EEG features and the imbalance in data samples across stress levels, we use the sequential backward selection (SBS) method for feature selection and the adaptive synthetic (ADASYN) sampling algorithm for imbalanced data. Our findings unveil that delta and theta features account for approximately 50% of the selected features through the SBS process. In leave-one-out (LOO) cross-validation, the combination of band power and pair-wise coherence (COH) achieves a maximum balanced accuracy of 94.8% in stress-level detection for the above daily stress dataset. Notably, using ADASYN and borderline synthesized minority over-sampling technique (borderline-SMOTE) methods enhances model accuracy compared to the traditional SMOTE approach. These results provide valuable insights into using EEG signals for assessing stress levels in real-life scenarios, shedding light on potential strategies for managing stress more effectively.