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Cryptography plays consistently an essential role in securing any sort of communications or data broadcast over the network. Since the security of any designed block cipher algorithm is related to its Substitution box (S-box), several efforts have been made by researchers to design a vigorous S-box that maintains flawlessly the cost, performance, and security trade-off. From the literature, we can find a variety of input–output sizes of S-boxes, each of which has its benefits and drawbacks. Therefore, this work introduces a new S-box pattern generation based on the chaotic enhanced logistic map where its chaotic behavior offers good randomness ability, a fact that enhances its unpredictability. In our realization, the intention was the generation of a 5-bit Sbox due to its suitability and cost-effectiveness to be integrated into lightweight cryptosystems. Moreover, the S-box security strength is proved by testing it through numerous cryptanalysis measurements. We can mention non-linearity, bijectivity, linearity, differential cryptanalysis, boomerang attacks resilience, Avalanche effect, and algebraic attacks resilience. The results show that our proposition provides good resistance to the aforementioned attacks and even shows superiority over its 5-bit competitors in terms of non-linearity, differential, Boomerang, and algebraic attack resistance. [ABSTRACT FROM AUTHOR]

With the outstanding growth of Internet of Things (IoT) devices, security and power efficiency of integrated circuits can no longer be overlooked. Current approved standards for cryptographic algorithms are not suitable for constrained environments. In this context, the National Institute of Standards and Technology (NIST) started a lightweight cryptography (LWC) competition to develop new algorithm standards that can be fit into small devices. In 2023, NIST has decided to standardize the Ascon family for LWC. This algorithm has been designed to be more resilient to side-channel and fault-based analysis. Nonetheless, hardware implementations of Ascon have been broken by multiple statistical fault analysis and power analysis. These attacks have underlined the necessity to develop adapted countermeasures to side-channel and perturbation-based attacks. However, existing countermeasures are power and area consuming. In this article, we propose a new countermeasure for the Ascon cipher that does not significantly increase the area and power consumption. Our architecture relies on the nonvolatile feature of the Magnetic Tunnel Junction (MTJ) that is the single element of the emerging Magnetic Random Access Memories (MRAM). The proposed circuit removes the bias exploited by statistical attacks. In addition, we have duplicated and complemented the permutation of Ascon to enhance the power analysis robustness of the circuit. Besides the security aspect, our circuit can save current manipulated data, ensuring energy saving from 11% to 32.5% in case of power failure. The area overhead, compared to an unprotected circuit, is × 2.43 . [ABSTRACT FROM AUTHOR]

Abstract Cryptography plays consistently an essential role in securing any sort of communications or data broadcast over the network. Since the security of any designed block cipher algorithm is related to its Substitution box (S-box), several efforts have been made by researchers to design a vigorous S-box that maintains flawlessly the cost, performance, and security trade-off. From the literature, we can find a variety of input–output sizes of S-boxes, each of which has its benefits and drawbacks. Therefore, this work introduces a new S-box pattern generation based on the chaotic enhanced logistic map where its chaotic behavior offers good randomness ability, a fact that enhances its unpredictability. In our realization, the intention was the generation of a 5-bit Sbox due to its suitability and cost-effectiveness to be integrated into lightweight cryptosystems. Moreover, the S-box security strength is proved by testing it through numerous cryptanalysis measurements. We can mention non-linearity, bijectivity, linearity, differential cryptanalysis, boomerang attacks resilience, Avalanche effect, and algebraic attacks resilience. The results show that our proposition provides good resistance to the aforementioned attacks and even shows superiority over its 5-bit competitors in terms of non-linearity, differential, Boomerang, and algebraic attack resistance.

Some traditional cryptographic techniques, like the Secure Hash Algorithm (SHA-256 for hashing), Rivest-Shamir-Adleman (RSA/Elliptic Curve for signing) and Advanced Encryption Standard (AES for encryption), perform well on systems with good hardware memory and processing capabilities. However, these techniques engage in conflict to keep up with the world of sensor networks and embedded systems. Lightweight cryptography plays a major role in security constraints, especially in resource-limited devices such as RFID tags, smart cards, sensor nodes and IoT. This paper proposes a flexible hardware architecture of lightweight m-Crypton block cipher for high-speed resource-constrained applications. The proposed architecture enables a single architecture appropriate for the many encryptions' key sizes. Therefore, the proposed architecture changes the security level in resource-constrained applications by integrating several key sizes into a single design. Furthermore, this architecture outperformed the conventional block ciphers in terms of throughput-to-area ratio achieving a 10.37 throughput-to-area ratio better than other lightweight block ciphers. The proposed design can be used in high bandwidth applications, high-end RFID and IoT smart devices. Hence, the proposed design demonstrates that increasing the speed of cipher implementation results in more plaintext transformations into ciphertext. All results have been verified and simulated for several Xilinx design suite families.

In the rapidly evolving landscape of the Internet of Things (IoT) and Wireless Sensor Networks (WSN), the need for secure and efficient data transmission is paramount. Block ciphers, which are fundamental cryptographic algorithms used for encrypting data, play a critical role in ensuring data security within these environments. This study delves into the implementation and performance evaluation of lightweight block ciphers, including PRESENT, Piccolo, RECTANGLE, SPARX, and LED, on various sensor motes. The research scrutinizes these cryptographic solutions within the resource-constrained environments characteristic of IoT and WSN deployments. Our investigation commences with a meticulous selection of sensor motes and platforms, enabling realistic simulations and practical evaluations. The Contiki Cooja framework, a comprehensive operating system (OS), development toolkit, and network simulator, was utilized to facilitate these assessments. Subsequently, we conduct a comprehensive performance assessment, rigorously analyzing each cipher's impact on memory usage, power consumption, and execution time. The results reveal that the SPARX cipher emerged as the most resource-efficient, with the lowest memory footprint, while the RECTANGLE cipher required more memory across platforms.

With the exponential growth of the Internet of Things (IoT), ensuring robust end-to-end encryption is paramount. Current cryptographic accelerators often struggle with balancing security, area efficiency, and power consumption, which are critical for compact IoT devices and system-on-chips (SoCs). This work presents a novel approach to designing substitution boxes (S-boxes) for Advanced Encryption Standard (AES) encryption, leveraging dual quad-bit structures to enhance cryptographic security and hardware efficiency. By utilizing Algebraic Normal Forms (ANFs) and Walsh–Hadamard Transforms, the proposed Register Transfer Level (RTL) circuitry ensures optimal non-linearity, low differential uniformity, and bijectiveness, making it a robust and efficient solution for ASIC implementations. Implemented on 65 nm CMOS technology, our design undergoes rigorous statistical analysis to validate its security strength, followed by hardware implementation and functional verification on a ZedBoard. Leveraging Cadence EDA tools, the ASIC implementation achieves a central circuit area of approximately 199 μm2. The design incurs a hardware cost of roughly 80 gate equivalents and exhibits a maximum path delay of 0.38 ns. Power dissipation is measured at approximately 28.622 μW with a supply voltage of 0.72 V. According to the ASIC implementation on the TSMC 65 nm process, the proposed design achieves the best area efficiency, approximately 66.46% better than state-of-the-art designs. [ABSTRACT FROM AUTHOR]

In resource-intensive Internet of Things applications, Lightweight Stream Ciphers (LWSCs) play a vital role in influencing both the security and performance of the system. Numerous LWSCs have been proposed, each offering certain properties and trade-offs that carefully balance security and performance requirements. This paper presents a comprehensive evaluation of prominent LWSCs, with a focus on their performance and resource consumption, providing insights into efficiency, efficacy, and suitability in the real-world application of resource-intensive live video feed encryption on an ARM processor. The study involves the development of a benchmarking tool designed to evaluate key metrics, including encryption frame rate, throughput, processing cycles, memory footprint, ROM utilization, and energy consumption. In addition, we apply the E−Rank metric, which combines key performance and resource metrics to derive a unified comparative measure for overall software performance. [ABSTRACT FROM AUTHOR]

Midori64 is a lightweight SPN block cipher introduced by Banik et al. at ASIACRYPT 2015 and it operates on 64-bit states through 16 rounds using a 128-bit key. In the last decade, Midori64 has been exposed to several attacks. In this paper, to the best of our knowledge, we provide the first boomerang attack on Midori64 in the literature. For this purpose, firstly, we present a practical single key 7-round boomerang attack on Midori64, improving the mixture idea of Biryukov by a new technique which we call “mixture pool”, and then extend our attack up to 9 rounds with time complexity 2122.3, and memory and data complexity 236. (The authors of Midori stated that they expect much smaller rounds than eight rounds of Midori64 are secure against boomerang-type attacks.) We also emphasize that the mixture pool idea provides a kind of data-memory tradeoff and presents more usefulness for boomerang-type attacks. [ABSTRACT FROM AUTHOR]

The Internet of Things (IoT) will soon penetrate every aspect of human life. Several threats and vulnerabilities are present due to the different devices and protocols used in an IoT system. Conventional cryptographic primitives or algorithms cannot run efficiently and are unsuitable for resource-constrained devices in IoT. Hence, a recently developed area of cryptography, known as lightweight cryptography, has been introduced, and over the years, numerous lightweight algorithms have been suggested. This paper gives a comprehensive overview of the lightweight cryptography field and considers various popular lightweight cryptographic algorithms proposed and evaluated over the past years for analysis. Different taxonomies of the algorithms and other associated concepts were also provided, which helps new researchers gain a quick overview of the field. Finally, a set of 11 selected ultra-lightweight algorithms are analyzed based on the software implementations, and their evaluation is carried out using different metrics.

In this paper, we discuss the quantum circuit implementations of the lightweight authenticated encryption algorithm ASCON by using the NOT gates, CNOT gates, Toffoli gates, measurements, and the dynamic quantum circuits. Firstly, the quantum circuit of addition of constants is realized by adding the NOT gates according to the position of 1 in round constants. Secondly, the quantum circuit of S-box of the permutation is synthesized according to the classical circuit diagram of S-box. Then the linear layer functions are expressed in matrix form, and their quantum circuits are synthesized according to Gaussian elimination. Finally, we synthesize the whole quantum circuits according to the general diagrams of the authenticated encryption algorithm ASCON. The correctness of the quantum circuits of the S-box and the linear layer was verified by the Aer simulator of the IBM Quantum platform. As far as we know, this is the first implementation of the quantum circuits for the Authenticated Encryption with Associated Data (AEAD) of ASCON in-place. The maximum quantum resources for the three ASCON authenticated encryption algorithms were estimated. The quantum circuit of ASCON-128 uses a total of 320 qubits, 30,639 NOT gates, 128,814 CNOT gates, 8064 Toffoli gates, 10,752 measurements, and 5376 dynamic quantum circuits. The quantum circuit of ASCON-128a uses a total of 320 qubits, 23,558 NOT gates, 98,144 CNOT gates, 6144 Toffoli gates, 8192 measurements, and 4096 dynamic quantum circuits. The quantum circuit of ASCON-80pq uses a total of 320 qubits, 30,736 NOT gates, 128,814 CNOT gates, 8064 Toffoli gates, 10,752 measurements, and 5376 dynamic quantum circuits. [ABSTRACT FROM AUTHOR]

As the Internet of Things (IoT) continues to revolutionize value-added services, its conventional architecture exhibits persistent scalability and security vulnerabilities, jeopardizing the trustworthiness of IoT-based services. These architectural limitations hinder the IoT's Sensor-as-a-Service (SEaaS) model, which enables the commercial transmission of sensed data through cloud platforms. This study proposes an innovative computational framework that integrates decentralized blockchain technology into the IoT architectural design, specifically enhancing SEaaS efficiency. This research contributes to an optimized IoT architecture with decentralized blockchain operations and simplified public key encryption. Furthermore, this study introduces an advanced SEaaS model featuring innovative trading operations for sensed data among diverse stakeholders. At its core, this model presents a unique blockchain-based data-sharing mechanism that manages multiple aspects, from enrollment to validation. Evaluations conducted in a standard Python environment indicate that the proposed SEaaS model outperforms existing blockchain-based data-sharing models, demonstrating approximately 40% less energy consumption, 18% increased throughput, 16% reduced latency, and a 25% reduction in algorithm processing time. Ultimately, integrating a lightweight authentication mechanism using simplified public key cryptography within the blockchain establishes the model's potential for efficient and secure data-sharing in IoT. [ABSTRACT FROM AUTHOR]

Ensuring data security and integrity is crucial for achieving the highest level of protection and performance in modern cyber-physical systems (CPS). Authenticated encryption with associated data (AEAD) is an efficient and secure way to encrypt data that ensures confidentiality and authenticity. The proposed work focuses on image encryption using the TinyJAMBU cipher within the AEAD scheme. In this paper, image encryption using the TinyJAMBU cipher with software and hardware modeling has been proposed, and image encryption evaluation over standard matrices has been performed. The hardware architecture for TinyJAMBU has been implemented on the Xilinx Virtex-7 FPGA device. The implementation results are compared with the realization of other contemporary ciphers that make TinyJAMBU-128’s implementation better in terms of look-up tables (LUTs), slice utilization, and power consumption. In the experimentation phase, the results of TinyJAMBU-128/192/256 for image encryption have been compared with existing image encryption techniques. It has been observed that, compared to other implementations, the proposed image encryption application using TinyJAMBU provides better results for PSNR, MSE, RMSE, and UACI. [ABSTRACT FROM AUTHOR]

Cryptographic devices' complexity necessitates fast security simulation environments against fault attacks. SystemC, a promising candidate in Electronic System Levels (ESLs), can achieve higher simulation speeds while maintaining accuracy and reliability, and its modular and hierarchical design allows for efficient modeling of complex cryptographic algorithms and protocols. However, code modification is required for fault injection and detection. Aspect-Oriented Programming (AOP) can test cryptographic models' robustness without modifications, potentially replacing real cryptanalysis schemes and reducing the time and effort required for fault injection and detection. Through the utilization of a fault injection/detection environment, this paper presents a novel approach to simulating the security fault attacks of ASCON cryptographic systems at the ESL. The purpose of this methodology is to evaluate the resistance of ASCON SystemC models against fault attacks. The proposed methodology leverages the advantages of AOP to enhance the fault injection and detection process. By applying AOP techniques, we inject faults into the SystemC models without making any changes to the main codebase. This approach not only improves the efficiency of testing cryptographic systems but also ensures that the main functionality remains intact during the fault injection process. The methodology was validated using three scenarios and SystemC ASCON as a case study. The first simulation involved evaluating fault detection capabilities, the second focused on the impact of AOP on executable file size and simulation time, and the third focused on the ESL impact on the ASCON design process. Simulation results show that this methodology can perfectly evaluate the robustness of the ASCON design against fault injection attacks with no significant impact on simulation time and file executable size. Additionally, the simulation results prove that the ASCON development life cycle at the ESL reduces the amount of time devoted to the design procedure by 83.34%, and the ASCON security attack simulations at the ESL decrease the simulation time by 40% compared to the register transfer level (RTL). [ABSTRACT FROM AUTHOR]

Abstract The Internet of Things (IoT) security is a highly challenging research domain. The IoT user devices frequently function in vulnerable platforms that cause many security problems that can be considered. The model lightweight cryptographic (LWC) method stake place to reflect the importance of cryptographic systems which offer safety with the employ of an effectual count of resources. The purpose of the lightweight system's design is to strike a balance in many features like low resource demand, performance, and cryptographic algorithm stability and strength. Therefore, this study develops a new Improved Lightning Search Algorithm based End-to-End Lightweight Partially Homomorphic Encryption Approach (ILSA-LPHEA) for Securing the IoT Environment. For securing the data in the IoT environment, a lightweight partially homomorphic encryption (PHE) approach is used. Since key generation remains an important process to establish secure data transmission among IoT devices and servers, the ILSA is used. The hybridization of lightweight encryption with PHE strategy provides better security by enhancing privacy, confidentiality, and authentication, enabling end-to-end encryption. A detailed experimental result analysis highlighted the better solution of the ILSA-LPHEA algorithm with recent models.

The efficient execution of a Lightweight Cryptography (LWC) algorithm is essential for edge computing platforms. Dedicated Instruction Set Extensions (ISEs) are often included for this purpose. We propose the CrISA-X-a Cryptography Instruction Set Architecture eXtensions designed to improve cryptographic latency on extendable processors. CrISA-X, provides enhanced speed of various algorithms simultaneously while optimizing ISA adaptability, a feat yet to be accomplished. The extension, diverse for several computation levels, is first tailored explicitly for individual algorithms and sets of LWC algorithms, depending on performance, frequency, and area trade-offs. By diligently applying the Min-Max optimization technique, we have configured these extensions to achieve a delicate balance between performance, area utilization, code size, etc. Our study presents empirical evidence of the performance enhancement achieved on a synthesis modular RISC processor. We offer a framework for creating optimized processor hardware and ISA extensions. The CrISA-X outperforms ISA extensions by delivering significant performance boosts between 3x to 17x while experiencing a relative area cost increase of +12% and +47% in LUTs. Notably, as one important example, the utilization of the ASCON algorithm yields a 10x performance boost in contrast to the base ISA instruction implementation.

Decentralized Edge Computing Networks (DECN) environments have emerged with the advent of the IoT to reduce delays, bringing data processing closer to where the data is generated to improve the processing of volumetric data at high speed instead of being sent to clouds to facilitate real-time applications. However, the security and privacy of the data exchanged among the edge devices need more consideration, considering its sensitivity and importance. Computational Diffie-Hellman (CDH) can be used to protect data exchange from malicious attacks. Unfortunately, CDH is vulnerable to man-in-the-middle attacks and lacks mutual authentication. Therefore, considering the computational power of devices in the DECN environment, this article presents a Modified CDH-based Secure and Lightweight Key Agreement Protocol (MCDH-SKLAP) to secure communication in the DECN. The proposed protocol has undergone a thorough analysis for robustness under ROM and ProVerif threat models, instilling confidence in its security aspects. Furthermore, the performance analysis results show it has low computation and communication overhead, making it suitable for use with resource-limited devices in the DECN environment. The proposed MCDH-SKLAP has achieved a 35% to 81% improvement in computation overhead and an 8.5% to 30% improvement in communication overhead.

In this paper, we present hardware implementations of the lightweight TinyJAMBU cipher with reduced power consumption using a mechanism based on shift register parallelization. The power consumption in digital circuits depends linearly on the switching activity of the logic gates. The parallelization technique reduces the number of switches per clock cycle of the shift registers, which can significantly reduce power consumption. This technique has been applied to the TinyJAMBU cipher, a finalist in the NIST lightweight cryptography standardization process with the lowest resource and power consumption. The implementations we present use the logical parallelization technique in the cipher’s NLFSR, which is the basic block of TinyJAMBU, and in the key register. Measurements with data from various post-place and route simulations, performed for the Xilinx 7-Series family of FPGAs, are presented to demonstrate the effectiveness of the proposed technique in reducing power consumption, achieving a reduction of more than 30% in dynamic power consumption compared to the standard implementation, with almost no increase in resource consumption. Therefore, the ciphers hardware implementations proposed in this paper are highly suitable for use as hardware peripherals in applications with severe constraints on available resources and power, such as low-power microcontrollers that are widely used in the IoT field.

This research work explores the growing role of IoT devices in daily life and the increasing demand for secure data transmission in different sectors like healthcare, military, etc. Moreover, this study focuses on the recent advancements in lightweight cryptography and compares various encryption algorithms in an IoT environment using real-time data. Employing Message Queuing Telemetric Transport (MQTT) protocol, this research work assess the time of encryption, memory usage, and CPU usage as key parameters. By standardizing iterations, key width, and block length, this study aims to identify optimal encryption solutions for IoT applications. [ABSTRACT FROM AUTHOR]

Maximum distance separable (MDS) matrices are often used in the linear layer of a block cipher due to their good diffusion property. A well-designed lightweight MDS matrix, especially an involutory one, can provide both security and performance benefits to the cipher. Finding the corresponding effective linear straight-line program (SLP) of the circuit of a linear layer is still a challenging problem. In this article, first, we propose a new heuristic algorithm called Superior Boyar-Peralta (SBP) in the computation of the minimum number of two-input Exclusive-OR (XOR) gates with the minimum circuit depth for the SLPs. Contrary to the existing global optimization methods supporting only two-input XOR gates, SBP heuristic algorithm provides the best global optimization solutions, especially for extracting low-latency circuits. Moreover, we give a new 4 × 4 involutory MDS matrix over F24, which requires only 41 XOR gates and depth 3 after applying SBP heuristic, whereas the previously best-known cost is 45 XOR gates with the same depth. In the second part of the article, for further optimization of the circuit area of linear layers with multiple-input XOR gates, we enhance the recently proposed BDKCI heuristic algorithm by incorporating circuit depth awareness, which limits the depth of the circuits created. By using the proposed circuit depth-bounded version of BDKCI, we present better circuit implementations of linear layers of block ciphers than those given in the literature. For instance, the given circuit for the AES MixColumn matrix only requires 44 XOR gates/depth 3/240.95 GE in the STM 130 nm (simply called ASIC4) library, while the previous best-known result is 55 XOR gates/depth 5/243.00 GE. Much better, our new 4 × 4 involutory MDS matrix requires only 19 XOR gates/depth3/79.75 GE in the STM 90 nm (simply called ASIC1) library, which is the lightest and superior to the state-of-the-art results. [ABSTRACT FROM AUTHOR]

As the popularity of 3D printing or additive manufacturing (AM) continues to increase for use in commercial and defense supply chains, the requirement for reliable, robust protection from adversaries has become more important than ever. Three-dimensional printing security focuses on protecting both the individual Industrial Internet of Things (I-IoT) AM devices and the networks that connect hundreds of these machines together. Additionally, rapid improvements in quantum computing demonstrate a vital need for robust security in a post-quantum future for critical AM manufacturing, especially for applications in, for example, the medical and defense industries. In this paper, we discuss the attack surface of adversarial data manipulation on the physical inter-device communication bus, Controller Area Network (CAN). We propose a novel, hierarchical tree solution for a secure, post-quantum-supported security framework for CAN-based AM devices. Through using subnet hopping between isolated CAN buses, our framework maintains the ability to use legacy or third-party devices in a plug-and-play fashion while securing and minimizing the attack surface of hardware Trojans or other adversaries. The results of the physical implementation of our framework demonstrate 25% and 90% improvement in message costs for authentication compared to existing lightweight and post-quantum CAN security solutions, respectively. Additionally, we performed timing benchmarks on the normal communication (hopping) and authentication schemes of our framework. [ABSTRACT FROM AUTHOR]

Physical Unclonable Function (PUF) has recently attracted interest from both industry and academia as a potential alternative approach to secure Internet of Things (IoT) devices from the more traditional computational-based approach using conventional cryptography. PUF is a promising solution for lightweight security, where the manufacturing fluctuation process of integrated circuits is used to improve the security of IoT, as it provides low complexity design and preserves secrecy. PUF provides a low-cost low-power solution and can be implemented in both Field Programmable Gate Arrays and Application-Specific Integrated Circuits. In this survey, we provide a comprehensive review of the state of the art of PUF, its architectures, protocols, and security for IoT. [ABSTRACT FROM AUTHOR]

It is known that the sponge construction is tightly indifferentiable from a random oracle up to around 2c/2 queries, where c is the capacity. In particular, it cannot provide generic security better than half of the underlying permutation size. In this paper, we aim to achieve hash function security beating this barrier. We present a hashing mode based on two b-bit permutations named the double sponge. The double sponge can be seen as the sponge embedded within the double block length hashing paradigm, making two permutation calls in parallel interleaved with an efficient mixing function. Similarly to the sponge, the permutation size is split as b = r+c, and the underlying compression function absorbs r bits at a time. We prove that the double sponge is indifferentiable from a random oracle up to around 22c/3 queries. This means that the double sponge achieves security beyond the birthday bound in the capacity. In addition, if c > 3b/4, the double sponge beats the birthday bound in the primitive size, to our knowledge being the first hashing mode based on a permutation that accomplices this feature.

Abstract It is challenging to devise lightweight cryptographic primitives efficient in both hardware and software that can provide an optimum level of security to diverse Internet of Things applications running on low-end constrained devices. Therefore, an efficient hardware design approach that requires some specific hardware resource may not be efficient if implemented in software. Substitution bit Permutation Network based ciphers such as PRESENT and GIFT are efficient, lightweight cryptographic hardware design approaches. These ciphers introduce confusion and diffusion by employing a 4 × 4 static substitution box and bit permutations. The bit-wise permutation is realised by simple rerouting, which is most cost-effective to implement in hardware, resulting in negligible power consumption. However, this method is highly resource-consuming in software, particularly for large block-sized ciphers, with each single-bit permutation requiring multiple sub-operations. This paper proposes a novel software-based design approach for permutation operation in Substitution bit Permutation Network based ciphers using a bit-banding feature. The conventional permutation using bit rotation and the proposed approach have been implemented, analysed and compared for GIFT and PRESENT ciphers on ARM Cortex-M3-based LPC1768 development platform with KEIL MDK used as an Integrated Development Environment. The real-time performance comparison between conventional and the proposed approaches in terms of memory (RAM/ROM) footprint, power, energy and execution time has been carried out using ULINKpro and ULINKplus debug adapters for various code and speed optimisation scenarios. The proposed approach substantially reduces execution time, energy and power consumption for both PRESENT and GIFT ciphers, thus demonstrating the efficiency of the proposed method for Substitution bit Permutation Network based symmetric block ciphers.

In resource-intensive Internet of Things applications, Lightweight Stream Ciphers (LWSCs) play a vital role in influencing both the security and performance of the system. Numerous LWSCs have been proposed, each offering certain properties and trade-offs that carefully balance security and performance requirements. This paper presents a comprehensive evaluation of prominent LWSCs, with a focus on their performance and resource consumption, providing insights into efficiency, efficacy, and suitability in the real-world application of resource-intensive live video feed encryption on an ARM processor. The study involves the development of a benchmarking tool designed to evaluate key metrics, including encryption frame rate, throughput, processing cycles, memory footprint, ROM utilization, and energy consumption. In addition, we apply the E−Rank metric, which combines key performance and resource metrics to derive a unified comparative measure for overall software performance.

The Internet of Things (IoT) has gained popularity in various fields, including components such as embedded devices and wireless sensors. However, ensuring the security of data transmission from these devices is of critical importance. In light of these challenges, a novel lightweight encryption method called DRcipher is proposed in this paper for resource-constrained IoT devices. DRcipher has a 64-bit block size and supports either 96-bit or 128-bit key sizes. In order to improve the security, DRcipher employs a pseudo-random number of encryption rounds determined by the primary key. DRcipher adopts the structure of Generalized Feistel Network (GFN) with 4 branches, and its round functions consist of F-function, FF-function and RP permutation components. In particular, there is a negative feedback mechanism between the FF-function and the overall round of encryption functions. In addition, DRcipher is synthesised using Synopsys Design Compiler version A-2007.12-SP1 and the UMCL18G212T3 standard cell library. DRcipher-96 has an area footprint of 1546 Gate Equivalents (GE), while DRcipher-128 has a slightly larger area footprint of 1646 GE. Moreover, a comprehensive security analysis shows that the proposed DRcipher ensures high-level security redundancy against differential cryptanalysis, linear cryptanalysis, and so on.

Maximum distance separable (MDS) matrices are often used in the linear layer of a block cipher due to their good diffusion property. A well-designed lightweight MDS matrix, especially an involutory one, can provide both security and performance benefits to the cipher. Finding the corresponding effective linear straight-line program (SLP) of the circuit of a linear layer is still a challenging problem. In this article, first, we propose a new heuristic algorithm called Superior Boyar-Peralta (SBP) in the computation of the minimum number of two-input Exclusive-OR (XOR) gates with the minimum circuit depth for the SLPs. Contrary to the existing global optimization methods supporting only two-input XOR gates, SBP heuristic algorithm provides the best global optimization solutions, especially for extracting low-latency circuits. Moreover, we give a new 4 × 4 involutory MDS matrix over F24, which requires only 41 XOR gates and depth 3 after applying SBP heuristic, whereas the previously best-known cost is 45 XOR gates with the same depth. In the second part of the article, for further optimization of the circuit area of linear layers with multiple-input XOR gates, we enhance the recently proposed BDKCI heuristic algorithm by incorporating circuit depth awareness, which limits the depth of the circuits created. By using the proposed circuit depth-bounded version of BDKCI, we present better circuit implementations of linear layers of block ciphers than those given in the literature. For instance, the given circuit for the AES MixColumn matrix only requires 44 XOR gates/depth 3/240.95 GE in the STM 130 nm (simply called ASIC4) library, while the previous best-known result is 55 XOR gates/depth 5/243.00 GE. Much better, our new 4 × 4 involutory MDS matrix requires only 19 XOR gates/depth3/79.75 GE in the STM 90 nm (simply called ASIC1) library, which is the lightest and superior to the state-of-the-art results.

WG-5 is a lightweight stream cipher proposed for usage in the resource-constrained devices, e.g., passive RFID tags, industrial controllers, contactless smart cards and sensors. In this paper, a weakness called slide property of WG-5 which has not been discovered in previous works is for the first time explored and analyzed. The result shows that the probability that two related key-IV pairs of WG-5 generate the shifted keystreams can be up to 2−20, which is significantly high compared with an ideal stream cipher that generates the random keystreams. The correctness and accuracy of this theoretical probability is confirmed experimentally. Based on the slide property of WG-5, some key recovery attacks on WG-5 in the related key setting are proposed. The cryptanalytic result shows that the 80-bit secret key of WG-5 can be recovered with a time complexity of 225.615, requiring 6 related keys and 80 keystream bits for each of 224.585 chosen IVs. The experimental result validates our attack and shows that WG-5 can be broken within about 92.054 seconds on a common PC in the related key setting. These results imply that the design of WG-5 is far from optimal and needs to be strengthened to provide enough security for the lightweight constrained applications.

The IoT technology is currently used in many areas and marked by growing popularity. On the one hand, the IoT makes our lives easier, on the other hand, it presents challenges in terms of security and privacy protection. An IoT infrastructure is characterized by a high level of threats due to, inter alia, numerous technical barriers that make it difficult to use conventional methods to protect information. The aim of this paper is to present a symmetric coding algorithm based on algebraic groups generated by specific trigonometric curves. The algorithm is dedicated to short data sequences transmitted by devices with limited computing power.

Determining bounds on the differential probability of differential trails and the squared correlation contribution of linear trails forms an important part of the security evaluation of a permutation. For Xoodoo, such bounds were proven using the trail core tree search technique, with a dedicated tool (XooTools) that scans the space of all r-round trails with weight below a given threshold Tr. The search space grows exponentially with the value of Tr and XooTools appeared to have reached its limit, requiring huge amounts of CPU time to push the bounds a little further. The bottleneck was the phase called trail extension where short trails are extended to more rounds, especially in the backward direction. In this work, we present a number of techniques that allowed us to make extension much more efficient and as such to increase the bounds significantly. Notably, we prove that the minimum weight of any 4-round trail is 80, the minimum weight of any 6-round trail is at least 132 and the minimum weight of any 12-round trail is at least 264, both for differential and linear trails. As a byproduct we found families of trails that have predictable weight once extended to more rounds and use them to compute upper bounds for the minimum weight of trails for arbitrary numbers of rounds.

In recent years, lightweight cryptography has been a hot field in symmetric cryptography. One of the most crucial problems is to find low-latency implementations of linear layers. The current main heuristic search methods include the Boyar-Peralta (BP) algorithm with depth limit and the backward search. In this paper we firstly propose two improved BP algorithms with depth limit mainly by minimizing the Euclidean norm of the new distance vector instead of maximizing it in the tie-breaking process of the BP algorithm. They can significantly increase the potential for finding better results. Furthermore, we give a new framework that combines forward search with backward search to expand the search space of implementations, where the forward search is one of the two improved BP algorithms. In the new framework, we make a minor adjustment of the priority of rules in the backward search process to enable the exploration of a significantly larger search space. As results, we find better results for the most of matrices studied in previous works. For example, we find an implementation of AES MixColumns of depth 3 with 99 XOR gates, which represents a substantial reduction of 3 XOR gates compared to the existing record of 102 XOR gates.

It is challenging to devise lightweight cryptographic primitives efficient in both hardware and software that can provide an optimum level of security to diverse Internet of Things applications running on low-end constrained devices. Therefore, an efficient hardware design approach that requires some specific hardware resource may not be efficient if implemented in software. Substitution bit Permutation Network based ciphers such as PRESENT and GIFT are efficient, lightweight cryptographic hardware design approaches. These ciphers introduce confusion and diffusion by employing a 4 × 4 static substitution box and bit permutations. The bit-wise permutation is realised by simple rerouting, which is most cost-effective to implement in hardware, resulting in negligible power consumption. However, this method is highly resource-consuming in software, particularly for large block-sized ciphers, with each single-bit permutation requiring multiple sub-operations. This paper proposes a novel software-based design approach for permutation operation in Substitution bit Permutation Network based ciphers using a bit-banding feature. The conventional permutation using bit rotation and the proposed approach have been implemented, analysed and compared for GIFT and PRESENT ciphers on ARM Cortex-M3-based LPC1768 development platform with KEIL MDK used as an Integrated Development Environment. The real-time performance comparison between conventional and the proposed approaches in terms of memory (RAM/ROM) footprint, power, energy and execution time has been carried out using ULINKpro and ULINKplus debug adapters for various code and speed optimisation scenarios. The proposed approach substantially reduces execution time, energy and power consumption for both PRESENT and GIFT ciphers, thus demonstrating the efficiency of the proposed method for Substitution bit Permutation Network based symmetric block ciphers. [ABSTRACT FROM AUTHOR]

Unmanned aerial vehicles (UAVs) have become increasingly popular in recent years and are applied in various fields, from commercial and scientific to military and humanitarian operations. However, their usage presents many challenges, including limited resources, scalability issues, insecure communication, and inefficient solutions. We developed a secure and scalable registration protocol to address these issues using LoRa technology. Our solution involves the usage of the physical unclonable function (PUF) and blockchain technology for key exchange. PUF also ensures security against physical tampering, and blockchain is applied to share the symmetric key among the base stations. After the registration, the later communication messages are encrypted with AES-GCM to provide authentication and confidentiality between the parties. We conducted a security analysis of the registration protocol using the ProVerif tool, and our solution meets the security requirements, including the mutual authentication of entities, key freshness, key secrecy and also key confirmation properties. Besides the Proverif-based analysis, an informal security analysis is also provided that shows that the registration is protected against a variety of well-known active and passive security attacks. As drone resources are limited, we also prepared a proof of concept to test our solution under real-life conditions, focusing on efficiency and lightweight operations. [ABSTRACT FROM AUTHOR]

This research paper presents a study on designing and implementing a robust key management scheme for lightweight block ciphers in Internet of Things (IoT) networks. Key management is a critical concern for IoT devices due to their limited resources and susceptibility to security threats. The proposed scheme utilises partial key pre-distribution to achieve lightweight and secure key management. The protocol's security has been analysed against various attacks, demonstrating its resistance. Performance evaluation results indicate that the proposed key management technique is suitable for resource-constraint IoT networks, as it reduces communication overhead, power consumption, and storage space requirements. The methodology employed in this research includes designing and implementing the proposed key management scheme and conducting scenario-based analyses of its functionality. The results affirm that the proposed solution effectively ensures secure communication in IoT networks. Overall, this research contributes to developing a secure and efficient key management scheme for lightweight block ciphers in IoT networks. [ABSTRACT FROM AUTHOR]

IoT devices and embedded systems are deployed in critical environments, emphasizing attributes like power efficiency and computational capabilities. However, these constraints stress the paramount importance of device security, stimulating the exploration of lightweight cryptographic mechanisms. This study introduces a lightweight architecture for authenticated encryption tailored to these requirements. The architecture combines the lightweight encryption of the LED block cipher with the authentication of the PHOTON hash function. Leveraging shared internal operations, the integration of these bases optimizes area–performance tradeoffs, resulting in reduced power consumption and a reduced logic footprint. The architecture is synthesized and simulated using Verilog HDL, Quartus II, and ModelSim, and implemented on Cyclone FPGA devices. The results demonstrate a substantial 14% reduction in the logic area and up to a 46.04% decrease in power consumption in contrast to the individual designs of LED and PHOTON. This work highlights the potential for using efficient cryptographic solutions in resource-constrained environments. [ABSTRACT FROM AUTHOR]

INTRODUCTION: IoT devices are small, have limited battery and computing capabilities, and cannot tolerate complex encryption. So there is a need for a lightweight cryptographic scheme that can perform well in resource constraint environments. OBJECTIVES: Many encryption algorithms struggle to balance security and complexity. Increasing the level of protection necessitates increasing complexity, which leads to higher encryption and decryption times. The goal of this article is to offer a novel encryption method, the Modified Rijndael Algorithm, which balances security and complexity. METHODS: The classic Rijndael encryption technique has been modified to make it lighter and more secure, suitable for resource-constrained IoT devices. These modifications include adding the novel pre-processing step Crossover based on the two-point crossover operation of genetic algorithms, removing the Sub Byte step, changing the shift column phase, and decreasing the rounds. RESULTS: The proposed scheme provides speed and high security, increasing efficiency and randomness while reducing encryption and decryption times by 21.06% and CPU consumption by 13.2% compared to the traditional method. CONCLUSION: The proposed algorithm reduces encryption time and maintains the complexity needed to protect the data. It is lighter and more secure, making it suitable for IoT devices with limited resources. [ABSTRACT FROM AUTHOR]

This article presents a new hybrid method (combining search based methods and direct construction methods) to generate all 4×4 involutory maximum distance separable (MDS) matrices over F2m. The proposed method reduces the search space complexity at the level of ffiffiffinp, where n represents the number of all 4×4 invertible matrices over F2m to be searched for. Hence, this enables us to generate all 4×4 involutory MDS matrices over F23 and F24. After applying global optimization technique that supports higher Exclusive-OR (XOR) gates (e.g., XOR3, XOR4) to the generated matrices, to the best of our knowledge, we generate the lightest involutory/non-involutory MDS matrices known over F23, F24 and F28 in terms of XOR count. In this context, we present new 4×4 involutory MDS matrices over F23, F24 and F28, which can be implemented by 13 XOR operations with depth 5, 25 XOR operations with depth 5 and 42 XOR operations with depth 4, respectively. Finally, we denote a new property of Hadamard matrix, i.e., (involutory and MDS) Hadamard matrix form is, in fact, a representative matrix form that can be used to generate a small subset of all 2k×2k involutory MDS matrices, where k > 1. For k = 1, Hadamard matrix form can be used to generate all involutory MDS matrices. [ABSTRACT FROM AUTHOR]

Data compression combined with effective encryption is a common requirement of data storage and transmission. Low cost of these operations is often a high priority in order to increase transmission speed and reduce power usage. This requirement is crucial for battery-powered devices with limited resources, such as autonomous remote sensors or implants. Well-known and popular encryption techniques are frequently too expensive. This problem is on the increase as machine-to-machine communication and the Internet of Things are becoming a reality. Therefore, there is growing demand for finding trade-offs between security, cost and performance in lightweight cryptography. This article discusses asymmetric numeral systems— an innovative approach to entropy coding which can be used for compression with encryption. It provides a compression ratio comparable with arithmetic coding at a similar speed as Huffman coding; hence, this coding is starting to replace them in new compressors. Additionally, by perturbing its coding tables, the asymmetric numeral system makes it possible to simultaneously encrypt the encoded message at nearly no additional cost. The article introduces this approach and analyzes its security level. The basic application is reducing the number of rounds of some cipher used on ANS-compressed data, or completely removing an additional encryption layer when reaching a satisfactory protection level.

As the Internet of Things (IoT) continues to revolutionize value-added services, its conventional architecture exhibits persistent scalability and security vulnerabilities, jeopardizing the trustworthiness of IoT-based services. These architectural limitations hinder the IoT’s Sensor-as-a-Service (SEaaS) model, which enables the commercial transmission of sensed data through cloud platforms. This study proposes an innovative computational framework that integrates decentralized blockchain technology into the IoT architectural design, specifically enhancing SEaaS efficiency. This research contributes to an optimized IoT architecture with decentralized blockchain operations and simplified public key encryption. Furthermore, this study introduces an advanced SEaaS model featuring innovative trading operations for sensed data among diverse stakeholders. At its core, this model presents a unique blockchain-based data-sharing mechanism that manages multiple aspects, from enrollment to validation. Evaluations conducted in a standard Python environment indicate that the proposed SEaaS model outperforms existing blockchain-based data-sharing models, demonstrating approximately 40% less energy consumption, 18% increased throughput, 16% reduced latency, and a 25% reduction in algorithm processing time. Ultimately, integrating a lightweight authentication mechanism using simplified public key cryptography within the blockchain establishes the model’s potential for efficient and secure data-sharing in IoT.

Cryptographic devices’ complexity necessitates fast security simulation environments against fault attacks. SystemC, a promising candidate in Electronic System Levels (ESLs), can achieve higher simulation speeds while maintaining accuracy and reliability, and its modular and hierarchical design allows for efficient modeling of complex cryptographic algorithms and protocols. However, code modification is required for fault injection and detection. Aspect-Oriented Programming (AOP) can test cryptographic models’ robustness without modifications, potentially replacing real cryptanalysis schemes and reducing the time and effort required for fault injection and detection. Through the utilization of a fault injection/detection environment, this paper presents a novel approach to simulating the security fault attacks of ASCON cryptographic systems at the ESL. The purpose of this methodology is to evaluate the resistance of ASCON SystemC models against fault attacks. The proposed methodology leverages the advantages of AOP to enhance the fault injection and detection process. By applying AOP techniques, we inject faults into the SystemC models without making any changes to the main codebase. This approach not only improves the efficiency of testing cryptographic systems but also ensures that the main functionality remains intact during the fault injection process. The methodology was validated using three scenarios and SystemC ASCON as a case study. The first simulation involved evaluating fault detection capabilities, the second focused on the impact of AOP on executable file size and simulation time, and the third focused on the ESL impact on the ASCON design process. Simulation results show that this methodology can perfectly evaluate the robustness of the ASCON design against fault injection attacks with no significant impact on simulation time and file executable size. Additionally, the simulation results prove that the ASCON development life cycle at the ESL reduces the amount of time devoted to the design procedure by 83.34%, and the ASCON security attack simulations at the ESL decrease the simulation time by 40% compared to the register transfer level (RTL).

This article presents a new hybrid method (combining search based methods and direct construction methods) to generate all $4 \times 4$4×4 involutory maximum distance separable (MDS) matrices over $\mathbf{F}_{2^m}$F2m . The proposed method reduces the search space complexity at the level of $$\sqrt n $$ n, where n represents the number of all $4 \times 4$4×4 invertible matrices over $\mathbf{F}_{2^m}$F2m to be searched for. Hence, this enables us to generate all $4 \times 4$4×4 involutory MDS matrices over $\mathbf{F}_{2^3}$F23 and $\mathbf{F}_{2^4}$F24 . After applying global optimization technique that supports higher Exclusive-OR (XOR) gates (e.g., XOR3, XOR4) to the generated matrices, to the best of our knowledge, we generate the lightest involutory/non-involutory MDS matrices known over $\mathbf{F}_{2^3}$F23 , $\mathbf{F}_{2^4}$F24 and $\mathbf{F}_{2^8}$F28 in terms of XOR count. In this context, we present new $4 \times 4$4×4 involutory MDS matrices over $\mathbf{F}_{2^3}$F23 , $\mathbf{F}_{2^4}$F24 and $\mathbf{F}_{2^8}$F28 , which can be implemented by 13 XOR operations with depth 5, 25 XOR operations with depth 5 and 42 XOR operations with depth 4, respectively. Finally, we denote a new property of Hadamard matrix, i.e., (involutory and MDS) Hadamard matrix form is, in fact, a representative matrix form that can be used to generate a small subset of all $2^k\times 2^k$2k×2k involutory MDS matrices, where k > 1. For k = 1, Hadamard matrix form can be used to generate all involutory MDS matrices.

We introduce the QARMAv2 family of tweakable block ciphers. It is a redesign of QARMA (from FSE 2017) to improve its security bounds and allow for longer tweaks, while keeping similar latency and area. The wider tweak input caters to both specific use cases and the design of modes of operation with higher security bounds. This is achieved through new key and tweak schedules, revised S-Box and linear layer choices, and a more comprehensive security analysis. QARMAv2 offers competitive latency and area in fully unrolled hardware implementations. Some of our results may be of independent interest. These include: new MILP models of certain classes of diffusion matrices; the comparative analysis of a full reflection cipher against an iterative half-cipher; our boomerang attack framework; and an improved approach to doubling the width of a block cipher.

Lightweight cryptographic algorithms must develop to ensure the confidentiality and integrity of the data in resource-constrained devices. Keys are vital to every cryptography algorithm because they provide randomness, complexity, unexpected nature, and robustness. A light encryption device (LED) is considered a lighter version of advanced encryption standard (AES), but it is vulnerable to related key attacks due to using the same key during the whole encryption process. This paper presents a hybrid chaotic key generator (HCKG) based on 3D Lorenz, and 2D Henon maps to generate a highly randomized key that combines with the LED to provide a high level of secure encryption on resource-constrained devices. We modified the HCKG every four rounds via simple operations to get the subkeys and XORed it with the state to increase the complexity of the ciphertext. Moreover, the HCKG with subkeys allows us to decrease the total number of LED rounds from 32 to 24 to minimize the calculation cost while maintaining a high level of security. National Institute of Science and Technology (NIST) test suite proves that the proposed LED-HCKG demonstrates a high-performance increase by nearly 0.3283 higher than LED concerning data integrity and secrecy. [ABSTRACT FROM AUTHOR]

In medical information systems, image data can be considered crucial information. As imaging technology and methods for analyzing medical images advance, there will be a greater wealth of data available for study. Hence, protecting those images is essential. Image encryption methods are crucial in multimedia applications for ensuring the security and authenticity of digital images. Recently, the encryption of medical images has garnered significant attention from academics due to concerns about the safety of medical communication. Advanced approaches, such as e-health, smart health, and telemedicine applications, are employed in the medical profession. This has highlighted the issue that medical images are often produced and shared online, necessitating protection against unauthorized use. [ABSTRACT FROM AUTHOR]

One of the most significant challenges appears to be securing the Internet of Things (IoT) communication network. As a corollary, information security has become the basis for establishing trustworthiness in IoT network communication. Cryptography is one of the ways for securing information in this case. However, the majority of current approaches are static, making them subject to security threats. As a consequence, a new concept, dynamic encryption, is growing rapidly in IoT communication. In this paper, a dynamic encryption algorithm (DSIT) has been proposed to secure IoT communication. This algorithm is based on Feistel and Substitution–Permutation Network. DSIT is a block cipher that takes the 64-bit block of plaintext, 64-bit secret key, and a secret dynamic box (D-box) as input. It produces a 64-bit ciphertext by performing eight rounds of the DSIT algorithm. For each round, the key and D-box are updated. This dynamic effect provides high security to a dynamic IoT network. The proposed algorithm has been executed in IoT environment using Raspberry Pi 3 Model B + and 50% average Avalanche effect has been achieved. The proposed algorithm efficiently encrypts the image data to secure the communication and high resistant to cryptanalysis attacks. [ABSTRACT FROM AUTHOR]

Lightweight cryptography has been one of such fields which is used in resource constrained environments. XXTEA is a popular and efficient lightweight block cipher that can work on minimum 64-bit block size and provides sufficient security as compared to TEA and XTEA block cipher. In this paper, XXTEA lightweight block cipher with 128 bit block size has been used for image encryption by using pipelined hardware architecture which significantly improved the speed with little area overhead. For the hardware architecture of XXTEA, to store the image data, a high level memory interface has been used. The proposed design has been implemented in FPGA and ASIC platforms. The frequency has been improved by 85.9% and has an efficiency of seven time more than the previous literature in FPGA platform. Security analysis has been performed to estimate the security strength of the XXTEA and derived various parameters like histogram, key sensitivity, key space, pixel correlation co-efficient, differential attack, etc. [ABSTRACT FROM AUTHOR]

The Internet of Things (IoT) has rapidly grown in recent years, making it an integral part of many areas of our lives. Many IoT networks require high data throughput and low latency, allowing for real-time communication and data transmission, enabling improved efficiency, cost savings, and enhanced decision-making capabilities in various industries such as manufacturing, healthcare, transportation, and smart cities. However, with the increasing amount of data being transmitted, the security of high-speed IoT networks becomes a critical concern. In this paper, we proposed a hardware architecture for Ascon, a NIST Lightweight cryptography standard to enable high-throughput, low-latency security services in IPSec protocols. Results show that the ESP protocol can achieve a maximum throughput of 8.806 Gbps and a minimum latency of 427ns for only 2812 Slice. This ESP core together with the proposed Ascon implementation can be used in IoT gateways to provide security services for high-speed, low-latency IoT networks.

Internet of Things (IoT) technologies will interconnect with a wide range of network devices, regardless of their local network and resource capacities. Ensuring the security, communication, and privacy protection of end-users is a major concern in IoT development. Secure communication is a significant requirement for various applications, especially when communication devices have limited resources. The emergence of IoT also necessitates the use of low-power devices that interconnect with each other for essential processing. These devices are expected to handle large amounts of monitoring and control data while having limited capabilities and resources. The algorithm used for secure encryption should protect vulnerable devices. Conventional encryption methods such as RSA or AES are computationally expensive and require large amounts of memory, which can adversely affect device performance. Simplistic encryption techniques are easily compromised. To address these challenges, an effective and secure lightweight cryptographic process is proposed for computer devices. This process utilizes a symmetrical encryption key block, incorporating a custom proxy network (SP) and a modified Feistel architecture. Security analysis and performance evaluation results demonstrate that the proposed protocol is secure and energy-efficient. The symmetric key encryption scheme is based on sequences in the Feistel cipher, with multiple rounds and sub-keys generated using principles derived from genetic algorithms. This proposed algorithm minimizes processing cycles while providing sufficient security.

Maximum Distance Separable (MDS) matrices are used as the main component of diffusion layers in block ciphers. MDS matrices have the optimal diffusion properties and the maximum branch number, which is a criterion to measure diffusion rate and security against linear and differential cryptanalysis. However, it is a challenging problem to construct hardware-friendly MDS matrices with optimal or close to optimal circuits, especially for involutory ones. In this paper, we consider the generalized subfield construction method from the global optimization perspective and then give new $4 \times 4$ involutory MDS matrices over $\mathbb {F}_{2^{3}}$ and $\mathbb {F}_{2^{5}}$ . After that, we present 1,176 ( $=28\times 42$ ) new $4 \times 4$ involutory and MDS diffusion matrices by 33 XORs and depth 3. This new record also improves the previously best-known cost of 38 XOR gates.

Ascon family is one of the finalists of the National Institute of Standards and Technology (NIST) lightweight cryptography standardization process. The family includes three Authenticated Encryption with Associated Data (AEAD) schemes: Ascon-128 (primary), Ascon-128a, and Ascon-80pq. In this paper, we study the resistance of the Ascon family against conditional cube attacks in nonce-misuse setting, and present new state- and key-recovery attacks. Our attacks recover the full state and the secret key of Ascon-128a when reduced to 7 out of 8 rounds of Ascon-permutation for the encryption phase, with 2117 data and 2116.2 time. These are the best known attack results for Ascon-128a as far as we know, while violating the data limit 264 imposed by designers. We also show that the partial state information of Ascon-128 can be recovered with 244.8 data. Finally, by assuming that the full state information of Ascon-80pq was recovered by Baudrin et al.’s attack, we show that the 160-bit secret key of Ascon-80pq can be recovered with 2128 time. Although our attacks do not invalidate designers’ security claim. those allow us to understand the security of Ascon in nonce-misuse setting.

With the development of the Internet of Things (IoT) technology, IoT devices are integrated into many of our daily lives, including industrial, security, medical, and personal applications. Many violations of IoT safety have appeared due to the critical physical infrastructure, and network vulnerabilities. Considering the nature of the restricted and limited resources of these devices in terms of size, capacity, and energy, Security is becoming increasingly important. Lightweight cryptography is one of the directions that offer security solutions in resource-constrained environments such as Radio-frequency identification (RFID) and wireless sensor network (WSN).This paper discusses the security issues of these resource-constrained IoT devices and reviews the most prominent Lightweight Bock Cipher suitable for software implementation. Through studying thespecifications and the inner structure for each cipher and their implementation of the performance evaluation on some kind of platform, we provide a design strategies guideline for cryptographic developers to design improved Lightweight Block cipher solutions and compact software implementation for resource-constrained environments.