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Ring amplifiers enable efficient amplification with less power consumption. These are characterized by fairly power requirements, and innate rail-to-rail output swing and are robust against PVT variations. In this paper, we are presenting an improved self-biased anti-series diode-based ring amplifier (ASD-RAMP) design, implemented on 45-nm CMOS technology. The design uses two diode-connected PMOS transistors that are connected in an anti-series manner to generate a large resistance because of which a high dead-zone voltage is generated. The ASD-RAMP has a settling time of only 4.05 ns, which is nearly half of the conventional self-biased ring amplifier (CSB-RAMP). In comparison to CSB-RAMP, the proposed ASD-RAMP improves the dead-zone voltage by 1. 1 × while requiring 6.76% less power. The circuit is durable and suitable for high-performance applications since it exhibits great resilience to PVT variations in addition to the improved dead zone voltage and reduced settling time. • Anti-Series Diode arrangement based ring amplifier is proposed to improve the dead zone voltage and the settling time. • RC electrical equivalent model for the settling time analysis of the circuit. • Proposed ring amplifier circuit is robust against the PVT variations. [ABSTRACT FROM AUTHOR]

This paper presents a pipelined noise-shaping SAR (PLNS-SAR) ADC for high SNDR, wide bandwidth, and low power consumption. The proposed design achieves a sharp second-order NTF of an error feedback structure, without a multi-input comparator and additional residue amplifier. Additionally, the SNDR is improved via zero optimization. Additionally, the speed is enhanced via prediction logic and alternately using the passive switched capacitor FIR filter. This consequently achieves the high-power efficiency of the ADC. The simulated SNDR is 79.97 dB; it achieves a 12.5-MHz BW at a 175-MHz sampling rate, with OSR of 7. The total power consumption of the ADC is 4.27 mW at a 1.1-V supply. The FoM S , SNDR is 174.6 dB. The proposed structure achieves high resolution and wide bandwidth with good energy efficiency. [ABSTRACT FROM AUTHOR]

This paper presents the design of a 2nd-order Noise-Shaping (NS) Successive-Approximation-Register (SAR) Analog-to-Digital Converter (ADC) employing a cascade of temperature-compensated dynamic amplifier and a ring amplifier in the feedback path to realize a low-power/low-noise loop filter that is robust to temperature variation. A new mismatch calibration technique optimized for a noise-shaping SAR ADC is also presented to overcome the challenge of finding correct digital bit weights for NS SAR ADCs. Fabricated in 65 nm Complementary Metal-Oxide-Semiconductor (CMOS) process, the prototype ADC demonstrates a peak Signal-to-Noise-and-Distortion Ratio (SNDR) of 71.35 dB and a dynamic range of 74 dB with a signal bandwidth of 625 kHz. Over 80-degree of the temperature range, the ADC exhibits only 2 dB drop in SNDR thanks to the temperature-compensated dynamic amplifier. With a total power consumption of $130~\mu \text{W}$ , the ADC achieves Walden Figure-of-Merit (FoM) of FoM $_{\text {W}}= 34.4$ fJ and Schreier FoM of FoM $_{\text {S,DR}}=171$ dB, respectively.

An 8-bit switched-capacitor multiply-and-accumulator (MAC) in 65nm CMOS is presented. Based on a cascaded low-power ring-amplifier-based switched-capacitor DACs, the MAC circuit features a programmable accumulation length in MAC computation. Fabricated in 65nm CMOS, the prototype MAC circuit achieves a precision-scaled energy efficiency of 1.32fJ per MAC operation, which is comparable to other state-of-the-art MAC circuits, along with best-in-class linearity. The noise performance has been verified using four real-world convolutional neural networks (CNNs) and 10,000-image data sets with up to 1,000 classes with an accuracy drop of less than 2% compared to the baseline 32-bit floating-point MAC.

This brief focuses on the robustness of the ring amplifier (RA), an alternative to the operational transconductance amplifier (OTA) in the deep nanoscale CMOS process. The effective gain (EG) of the RA shows diverse characteristics from the DC gain and can be treated as a non-linear gain error (NLGE). The EG shows a notable variation when taking process, supply voltage, and temperature (PVT) into consideration. An improved statistical calibration based on the back-end stage data is proposed to compensate the NLGE. A prototype SAR-assisted pipeline ADC with a quick-start RA is implemented in a 28-nm CMOS process, achieving 60.3 dB SNDR and 76.5 dB SFDR with a 6 MHz input at 625 MS/s. The SNDR and SFDR are 58.6 dB and 70.7 dB with a Nyquist input frequency and consumes 13.2 mW, achieving Walden and Schreier figure-of-merit (FoM) values of 30.4 fJ/conv.-step and 162.2 dB. For a −6 dBFS 50 MHz input, the measured SNDR and SFDR are above 55.5 dB and 68.9 dB with supply voltage and temperature fluctuation. [ABSTRACT FROM AUTHOR]

This brief presents a more detailed model for the slewing behavior of self-biased ring amplifiers and outlines the factors which affect the large signal operation. A set of analytical expressions derived for the self-biased ring amplifier are presented which are valid for a larger portion of a design space than prior expressions. The equations presented are well matched with simulation results and the accuracy of the derived equations is reported. Finally, the paper examines the proposed equations and simulation results to provide insight about design parameter dependence. [ABSTRACT FROM AUTHOR]

This brief presents a novel adaptive slew-rate ring amplifier. The proposed technique enhances the linearity, without stability degradation, using a rail-to-rail controlled feed-forward path used in parallel with the main ring amplifier. It offers additional degrees of freedom to improve the linearity/power consumption trade-off proposed in other reported slew-rate enhancement techniques. The proposed design has been implemented and simulated in a low-cost CMOS 65 nm technology. Operating from a single 0.9 V power supply, it consumes $186~\mu \text{A}$ for switching frequency of 210MHz. For the same current consumption, it achieves an improvement of 10 dB in the total harmonic distortion (THD) compared to state-of-the-art. [ABSTRACT FROM AUTHOR]

This brief presents an ultra-low-power two-channel 12b 140 MS/s 28-nm CMOS analog-to-digital converter (ADC) for use in next-generation mobile communications systems. The proposed ADC employs a two-stage pipelined successive-approximation register (SAR) ADC architecture, where the SAR ADC at each stage determines 5b and 8b, respectively. In the first-stage 5b SAR ADC, the switching power consumption is significantly reduced due to the switching operation by only a separate digital-to-analog converter (DAC) with a small unit capacitance, which generates the comparator decision threshold. When this setup is applied to an actual system, the reference voltage driver of the system is less burdened. Furthermore, the SAR ADC employs a custom-encapsulated capacitor to improve the limited linearity of a DAC caused by parasitic capacitance. A residue amplifier employs an ultra-low power ring amplifier structure. The amplifier is shared by each channel to reduce not only the power consumption and die area but also channel mismatches. The prototype ADC in a 28-nm CMOS process demonstrates a measured differential non-linearity and integral non-linearity within 1.50 LSB and 2.85 LSB at 12b, respectively, with a maximum signal-to-noise-and-distortion ratio and a spurious-free dynamic range of 58.0 dB and 73.7 dB at 140 MS/s, respectively. The ADC occupies an active die area of 0.202 mm2 and consumes 1.1 mW at a 0.8-V supply voltage, corresponding to a figure of merit of 12.1 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

This paper presents an experimental prototype of 2nd-order multi-bit ΔΣAD modulator with dynamic analog components for low power and high signal to noise and distortion (SNDR) application. The integrators in the modulator are realized by ring amplifier without static current. Multi-bit quantizer and analog adder in the feed-forward modulator is realized by a passive-adder embedded successive approximation register analog to digital converter which consists of capacitor array and a dynamic comparator. The dynamic comparator does not dissipate static power at all when a pre-amplifier is not used. Proposed modulator is fabricated in TSMC 90 nm CMOS technology. Measurement results of the modulator dynamic range is over 84 dB. Measured peak SNDR = 77.51 dB, SNR = 80.08 dB are achieved for the bandwidth of BW = 94 kHz while a sinusoid differential -1 dBFS input is sampled at 12 MS/s. The total analog power consumption of the modulator is 0.37 mW while the supply voltage is 1.1 V. [ABSTRACT FROM AUTHOR]

This brief introduces a design approach for Class-AB-style ring amplifiers which differs from the design of conventional amplifiers. The theory of operation of Class-AB-style ring amplifier is discussed as well as the different design tradeoffs that affect its design. Consequently, a systematic design methodology for Class-AB-style ring amplifier is introduced. A design example of a switched-capacitor gain amplifier with a closed-loop gain of 32, using a three-stage self-biased ring amplifier, is presented. This example has been designed and implemented in UMC 130-nm CMOS technology. It achieves an spurious-free dynamic range of 72 dB with a clock frequency of 25 MHz. It operates from a single 1.2-V supply and consumes 400 $\boldsymbol \mu \text{A}$. [ABSTRACT FROM AUTHOR]

This paper presents a new non-clocked standalone bulk-driven ring amplifier based on master-slave technique that ensures stable operation under process, supply voltage and temperature variations. Unlike the conventional ring amplifier the proposed topology operates without the switched capacitor technique under extremely low supply voltage. The bulk-driven ring amplifier was designed using a triple-well 0.18 µm CMOS technology. The simulation results show a 91 dB gain with 13 μW power dissipation from a 0.5 V supply voltage and the total harmonic distortion was equal to 0.29 %. [ABSTRACT FROM AUTHOR]

A 2.5-GS/s 12-bit four-way time-interleaved pipelined-SAR ADC is presented in 28-nm CMOS. A bias-enhanced ring amplifier is utilized as the residue amplifier to achieve high bandwidth and excellent power efficiency compared with a traditional operational amplifier. A high linearity front-end is proposed to alleviate the non-linearity of the diode for ESD protection in the input PAD. The embedded input buffer can suppress the kickback noise at high input frequencies. A blind background calibration based on digital-mixing is used to correct the mismatches between channels. Additionally, an optional neural network calibration is also provided. The prototype ADC achieves a low-frequency SNDR/SFDR of 51.0/68.0 dB, translating a competitive FoM w of 0.48 pJ/conv.-step at 250 MHz input running at 2.5 GS/s. [ABSTRACT FROM AUTHOR]

In this study, a pipelined noise-shaping successive-approximation register analog-to-digital converter (PLNS-SAR ADC) structure was proposed to achieve high resolution and to be free from comparator design requirements. The inter-stage amplifier and integrator of the PLNS-SAR ADC were implemented through a ring amplifier with high gain and speed. The ring amplifier was designed to improve power efficiency and be tolerant to process–voltage–temperature (PVT) variation, and uses a single loop common-mode feedback (CMFB) circuit. By processing residual signals with a single ring amplifier, power efficiency can be maximized, and a low-power system with 30% lower power consumption than that of a conventional PLNS-SAR ADC is implemented. With a high-gain ring amplifier, noise leakage is greatly suppressed, and a structure can be implemented that is tolerant of mismatches between the analog loop and digital correction filters. The measured signal to noise distortion ratio (SNDR) is 70 dB for a 5.15 MHz bandwidth (BW) at a 72 MS/s sampling rate (Fs) with an oversampling ratio (OSR) of 7, and the power consumption is 2.4 mW. The FoM S , SNDR   (= SNDR + 10 log 10 BW/Power) is 163.5 dB. The proposed structure in this study can achieve high resolution and wide BW with good power efficiency, without a filter calibration process, through the use of a ring amplifier in the PLNS-SAR ADC. [ABSTRACT FROM AUTHOR]