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We proposed a novel measurement method and system to measure the electrical characteristics of non-patterned semiconductor films to estimate the final device’s properties. The proposed method is based on measuring bottom-gate structure thin-film transistor (TFT) using the probe pins as source and drain electrodes. We carefully designed the array structure and material of the probe pin to effectively detect extremely low-level currents without patterned electrodes on the semiconductor film. The contact pressure was also carefully controlled through continuous monitoring using an implemented pressure sensor to ensure the reliability and reproducibility of the measured data. In addition, we developed a method of extracting device parameters, such as the threshold voltage and field-effect mobility, from the measured data, considering the geometric factor of the proposed method. Comparative analysis between the measurement results of the film sample using the proposed system and that of the final TFT sample exhibited similar results with slight deviations. Furthermore, the proposed system provided similar results under repetitive measurements. Consequently, the proposed method and system successfully demonstrated the estimation of the final TFT’s properties by measuring the electrical characteristics of the non-patterned semiconductor film with excellent reliability, highlighting the possibility of effectively reducing costs for development and fabrication.

With the continuous expansion of pixel arrays in digital microfluidics (DMF) chips, precise droplet control has emerged as a critical issue requiring detailed consideration. This paper proposes a novel capacitance-based droplet sensing system for thin-film transistor DMF. The proposed circuit features a distinctive inner and outer dual-pixel electrode structure, integrating droplet driving and sensing functionalities. Discharge occurs exclusively at the inner electrode during droplet sensing, effectively addressing droplet perturbation in existing sensing circuits. The circuit employs a novel fan-shaped structure of thin-film transistors. Simulation results show that it can provide a 48 V pixel voltage and demonstrate a sensing voltage difference of over 10 V between deionized water and silicone oil, illustrating its proficiency in droplet driving and accurate sensing. The stability of threshold voltage drift and temperature was also verified for the circuit. The design is tailored for integration into active matrix electrowetting-on-dielectric (AM-EWOD) chips, offering a novel approach to achieve precise closed-loop control of droplets. [ABSTRACT FROM AUTHOR]

Monolithic three‐dimensional (M3D) integration advances integrated circuits by enhancing density and energy efficiency. Ferroelectric thin‐film transistors (Fe‐TFTs) attract attention for neuromorphic computing and back‐end‐of‐the‐line (BEOL) compatibility. However, M3D faces challenges like increased runtime temperatures due to limited heat dissipation, impacting system reliability. This work demonstrates the effect of temperature impact on single‐gate (SG) Fe‐TFT reliability. SG Fe‐TFTs have limitations such as read‐disturbance and small memory windows, constraining their use. To mitigate these, dual‐gate (DG) Fe‐TFTs are modeled using technology computer‐aided design, comparing their performance. Compute‐in‐memory (CIM) architectures with SG and DG Fe‐TFTs are investigated for deep neural networks (DNN) accelerators, revealing heat's detrimental effect on reliability and inference accuracy. DG Fe‐TFTs exhibit about 4.6x higher throughput than SG Fe‐TFTs. Additionally, thermal effects within the simulated M3D architecture are analyzed, noting reduced DNN accuracy to 81.11% and 67.85% for SG and DG Fe‐TFTs, respectively. Furthermore, various cooling methods and their impact on CIM system temperature are demonstrated, offering insights for efficient thermal management strategies. [ABSTRACT FROM AUTHOR]

Many advanced technologies have been employed in high-performance active matrix displays, including liquid crystal displays, organic light-emitting diode displays, and micro-light-emitting diode displays. On the other side, there exists a strong demand for cost reduction, and it is one of the low-cost schemes for integrating the driver circuit in a panel based on thin-film transistor technologies. This paper reviews the overall concept, operation principles, and various circuit approaches in shift registers for scanning pulse generation. In addition, it deals with the implementation of additional functionalities in gate drivers to support pixel compensation, multi-line driving, in-cell capacitive touch screen, pixel sensing, and adaptive scanning region control. [ABSTRACT FROM AUTHOR]

The thin film of indium gallium tin oxide (IGTO) was deposited by the RF magnetron sputtering system with different oxygen flow ratios, which controls the numbers of defects and free carriers to change the characteristics of thin-film transistors ((TFTs). We determined the subgap density-of-states (DOS) from the transfer characteristics curve by the unified subthreshold coupling factor technique to analyze the response of oxygen-related trap sites within the thin films fabricated under different oxygen flows. We used Python to fit the DOS data with a combination of two exponential forms, inferring that, during the increase in the oxygen flow ratio, acceptor-like oxygen-related trap sites can be gradually compensated. The IGTO TFTs exhibit optimized performance when subjected to annealing at 200 °C for 1 h with a 5% oxygen flow ratio, showing a threshold voltage (Vth) of 1.76 V, a field-effect mobility of 0.355 cm2/V s, an impressive on/off drain current ratio of 1.42 × 106, and a subthreshold swing (SS) of 0.665 V/decade. [ABSTRACT FROM AUTHOR]

CO2 monitoring is important for achieving net-zero emissions. Here, we report on a CO2 gas sensor based on an In2O3 thin-film transistor (TFT), which is expected to realize both low-temperature operation and high sensitivity. The effect of channel thickness on TFT performance is well known; however, its effect on CO2 sensitivity has not been fully investigated. We fabricated In2O3 TFTs of various thicknesses to evaluate the effect of channel thickness on CO2 sensitivity. Consequently, TFT gas sensors with thinner channels exhibited higher CO2 sensitivity. This is because the surface effect is more prominent for a thinner film, suggesting that charge transfer between gas molecules and the channel surface through gas adsorption has a significant impact on changes in the TFT parameters in the subthreshold region. The results showed that the In2O3 TFT in thin channels is a promising candidate for CO2-sensitive TFT gas sensors and is useful for understanding an effect of gas adsorption in oxide TFTs with a very thin channel as well. [ABSTRACT FROM AUTHOR]

Atomic-layer-deposited (ALD) zinc-tin-oxide (ZTO) thin films offer promising electronic properties for many applications, but their development has been limited by their tendency to experience significant nucleation delay—which tends to introduce impurity—during deposition. This study utilized in-situ quartz crystal microbalance (QCM) analysis combined with ex-situ compositional analysis to examine the nucleation-delay characteristics of ZTO ALD and their dependence upon the oxidant-precursor settings. The results indicated that nucleation delay occurred solely during the ZnO-on-SnO 2 deposition step as a result of persisting ethyl ligands of the organozinc precursor, diethylzinc, which could be mitigated by using H 2 O 2 instead of H 2 O as the oxidant precursor and introducing a discrete-feeding or exposure procedure for the H 2 O 2 half cycle to increase the effective oxidant dose. The effects of nucleation delay on the electronic properties of ALD ZTO films was examined with thin-film transistor (TFT) devices, where suppression of nucleation delay yielded substantial improvement in the device performance, achieving a high field-effect mobility of 21.5 cm2/V s, low sub-threshold swing of 0.16, high on/off ratio of 2 × 108, and enhance-mode operation without needing elevated-temperature post-processing. The findings present valuable improvements over the state of the art and provide insights useful for the development of other types of ALD multi-component films. [ABSTRACT FROM AUTHOR]

Ultra-thin ZnO thin-film transistors with a channel thickness of <10 nm have disadvantages of a high threshold voltage and a low carrier mobility due to a low carrier concentration. Although these issues can be addressed by utilizing the strong reducing power of tri-methyl-aluminum, a method is required to control parameters such as the threshold voltage. Therefore, we fabricated a ZnO/Al2O3 thin-film transistor with a thickness of 6 nm and adjusted the threshold voltage and carrier mobility through the modulation of carrier generation by varying the growth temperature of Al2O3. As the growth temperature of Al2O3 increased, oxygen vacancies generated at the hetero–oxide interface increased, supplying a free carrier into the channel and causing the threshold voltage to shift in the negative direction. The optimized device, a ZnO/Al2O3 thin-film transistor with a growth temperature of 140 °C, exhibited a μsat of 12.26 cm2/V∙s, Vth of 8.16 V, SS of 0.65 V/decade, and ION/OFF of 3.98 × 106. X-ray photoelectron spectroscopy was performed to analyze the properties of ZnO/Al2O3 thin films. [ABSTRACT FROM AUTHOR]

Monolithic three‐dimensional (M3D) integration advances integrated circuits by enhancing density and energy efficiency. Ferroelectric thin‐film transistors (Fe‐TFTs) attract attention for neuromorphic computing and back‐end‐of‐the‐line (BEOL) compatibility. However, M3D faces challenges like increased runtime temperatures due to limited heat dissipation, impacting system reliability. This work demonstrates the effect of temperature impact on single‐gate (SG) Fe‐TFT reliability. SG Fe‐TFTs have limitations such as read‐disturbance and small memory windows, constraining their use. To mitigate these, dual‐gate (DG) Fe‐TFTs are modeled using technology computer‐aided design, comparing their performance. Compute‐in‐memory (CIM) architectures with SG and DG Fe‐TFTs are investigated for deep neural networks (DNN) accelerators, revealing heat's detrimental effect on reliability and inference accuracy. DG Fe‐TFTs exhibit about 4.6x higher throughput than SG Fe‐TFTs. Additionally, thermal effects within the simulated M3D architecture are analyzed, noting reduced DNN accuracy to 81.11% and 67.85% for SG and DG Fe‐TFTs, respectively. Furthermore, various cooling methods and their impact on CIM system temperature are demonstrated, offering insights for efficient thermal management strategies.

In this paper, we propose a bidirectional gate driver on array (GOA) circuit design based on indium gallium zinc oxide (IGZO) thin-film transistor (TFT) to support time-division driving method (TDDM) for in-cell touch displays. The proposed circuit allows the touch panel to pause the display for touch sensing operations to achieve a touch reporting rate as twice as the frame rate of a display. A dual low-level maintaining unit design is used to suppress influence of the threshold voltage shift of TFTs through alternately turning on the devices. Owing to recovery of threshold voltage shift under negative bias, this design can maintain stable performance during long time operation. A narrow border 6.5” in-cell LCD panel of 90 Hz display with a 180 Hz touch reporting rate is finally demonstrated.

To fabricate oxide thin-film transistors (TFTs) with high performance and excellent stability, preparing high-quality semiconductor films in the channel bulk region and minimizing the defect states in the gate dielectric/channel interfaces and back-channel regions is necessary. However, even if an oxide transistor is composed of the same semiconductor film, gate dielectric/channel interface, and back channel, its electrical performance and operational stability are significantly affected by the thickness of the oxide semiconductor. In this study, solution process-based nanometer-scale thickness engineering of InZnO semiconductors was easily performed via repeated solution coating and annealing. The thickness-controlled InZnO films were then applied as channel regions, which were fabricated with almost identical film quality, gate dielectric/channel interface, and back-channel conditions. However, excellent operational stability and electrical performance suitable for oxide TFT backplane was only achieved using an 8 nm thick InZnO film. In contrast, the ultrathin and thicker films exhibited electrical performances that were either very resistive (high positive VTh and low on-current) or excessively conductive (high negative VTh and high off-current). This investigation confirmed that the quality of semiconductor materials, solution process design, and structural parameters, including the dimensions of the channel layer, must be carefully designed to realize high-performance and high-stability oxide TFTs. [ABSTRACT FROM AUTHOR]

With the increase in electronic devices across various applications, there is rising demand for selective carrier control. The split-gate consists of a gate electrode divided into multiple parts, allowing for the independent biasing of electric fields within the device. This configuration enables the potential formation of both p- and n-channels by injecting holes and electrons owing to the presence of the two gate electrodes. Applying voltage to the split-gate allows for the control of the Fermi level and, consequently, the barrier height in the device. This facilitates band bending in unipolar transistors and allows ambipolar transistors to operate as if unipolar. Moreover, the split-gate serves as a revolutionary tool to modulate the contact resistance by controlling the barrier height. This approach enables the precise control of the device by biasing the partial electric field without limitations on materials, making it adaptable for various applications, as reported in various types of research. However, the gap length between gates can affect the injection of the electric field for the precise control of carriers. Hence, the design of the gap length is a critical element for the split-gate structure. The primary investigation in this review is the introduction of split-gate technology applied in various applications by using diverse materials, the methods for forming the split-gate in each device, and the operational mechanisms under applied voltage conditions. [ABSTRACT FROM AUTHOR]

The density of donor-like state distributions in solution-processed indium–zinc-oxide (IZO) thin-film transistors (TFTs) is thoroughly analyzed using photon energy irradiation. This study focuses on quantitatively calculating the distribution of density of states (DOS) in IZO semiconductors, with a specific emphasis on their variation with indium concentration. Two calculation methods, namely photoexcited charge collection spectroscopy (PECCS) and photocurrent-induced DOS spectroscopy (PIDS), are employed to estimate the density of the donor-like states. This dual approach not only ensures the accuracy of the findings but also provides a comprehensive perspective on the properties of semiconductors. The results reveal a consistent characteristic: the Recombination–Generation (R-G) center energy ET, a key aspect of the donor-like state, is acquired at approximately 3.26 eV, irrespective of the In concentration. This finding suggests that weak bonds and oxygen vacancies within the Zn-O bonding structure of IZO semiconductors act as the primary source of R-G centers, contributing to the donor-like state distribution. By highlighting this fundamental aspect of IZO semiconductors, this study enhances our understanding of their charge-transport mechanisms. Moreover, it offers valuable insight for addressing stability issues such as negative bias illumination stress, potentially leading to the improved performance and reliability of solution-processed IZO TFTs. The study contributes to the advancement of displays and technologies by presenting further innovations and applications for evaluating the fundamentals of semiconductors. [ABSTRACT FROM AUTHOR]

The zinc-tin-oxide (ZTO) thin-film transistor (TFT) is one of the most promising candidates for advanced display applications, though its popularity is limited by its performances. In this work, a heterojunction channel strategy was adopted to regulate the electron transport behaviors and the TFT performances by manipulating the concentration and the distribution of oxygen vacancies, and a reasonable physical model was proposed based on experimental and simulation results. It is difficult to mediate the contradiction between mobility and threshold voltage for the single channel. Via a heterojunction channel strategy, desirable TFT performances, with mobility of 12.5 cm2/Vs, threshold voltage of 1.2 V and Ion/Ioff of 3 × 109, are achieved when the oxygen-vacancy-enriched layer gets close to the gate insulator (GI). The enhanced performances can be mainly attributed to the formation of two-dimensional electron gas (2DEG), the insensitive potential barrier and the reasonable distribution of oxygen vacancy. On the contrary, when the oxygen-vacancy-enriched layer stays away from GI, all the main performances degenerate due to the vulnerable potential well. The findings may facilitate the development and application of heterojunction channels for improving the performances of electronic devices. [ABSTRACT FROM AUTHOR]

With the continuous expansion of pixel arrays in digital microfluidics (DMF) chips, precise droplet control has emerged as a critical issue requiring detailed consideration. This paper proposes a novel capacitance-based droplet sensing system for thin-film transistor DMF. The proposed circuit features a distinctive inner and outer dual-pixel electrode structure, integrating droplet driving and sensing functionalities. Discharge occurs exclusively at the inner electrode during droplet sensing, effectively addressing droplet perturbation in existing sensing circuits. The circuit employs a novel fan-shaped structure of thin-film transistors. Simulation results show that it can provide a 48 V pixel voltage and demonstrate a sensing voltage difference of over 10 V between deionized water and silicone oil, illustrating its proficiency in droplet driving and accurate sensing. The stability of threshold voltage drift and temperature was also verified for the circuit. The design is tailored for integration into active matrix electrowetting-on-dielectric (AM-EWOD) chips, offering a novel approach to achieve precise closed-loop control of droplets.

Many advanced technologies have been employed in high-performance active matrix displays, including liquid crystal displays, organic light-emitting diode displays, and micro-light-emitting diode displays. On the other side, there exists a strong demand for cost reduction, and it is one of the low-cost schemes for integrating the driver circuit in a panel based on thin-film transistor technologies. This paper reviews the overall concept, operation principles, and various circuit approaches in shift registers for scanning pulse generation. In addition, it deals with the implementation of additional functionalities in gate drivers to support pixel compensation, multi-line driving, in-cell capacitive touch screen, pixel sensing, and adaptive scanning region control.

This review aims to provide a technical roadmap and an overview of recent progress in the development of backplane thin film transistors (TFTs) for organic light-emitting diodes flat panel displays and next-generation flexible displays. In the introduction, we provide a general overview of the research trends for backplane TFTs. The main part describes the current technical level and prospects for amorphous metal oxide semiconducting, metal halide perovskites, and 2D transition metal dichalcogenides TFTs. The summary and prospects are provided in the conclusion section.

The detection of Hydrogen sulfide (H2S) gas at room temperature measurement has gained interest owing to its low-power consumption, high stability and reducing the risk of explosion within the sight of flammable gases. In this study, we present a novel low-cost and environmental-friendly approach in developing SnO2 and CuO nanoparticles (green approach) and their deployment in transistor (bi-layer approach) for the detection of hydrogen sulfide (H2S) vapors. The crystallite size of as-synthesized SnO2 and CuO NPs were revealed with aid of diffraction peaks which were found to be 14 nm and 19 nm respectively and the elemental composition with structural morphology (spherical) were determined by EDAX and Fe-SEM analysis respectively. The CuO nanoparticles interaction with the surface of SnO2 affirms a p-n junction formation with large electron-hole movements, while the interaction of H2S gas molecules on to the surface of CuO leads to the formation of CuS which awfully reduces electrical resistance enhancing the electrical conductivity and the sensor response. The high sensitivity of 1.86 μA/ppm and selectivity response of 89.46 % was achieved for the exposure of H2S analyte among other analytes exposed such as NO2, CO, C2H5OH and C3H8. The results demonstrate that sensor designed is potent for the use in industrial, environmental, and safety applications, contributing to the mitigation of H2S-related risks.

We studied the impact of NF3 plasma treatment on the HfO2 gate insulator of amorphous tin oxide (a-SnOx) thin-film transistors (TFTs). The plasma treatment was for 0, 10, or 30 s. The HfO2 insulator demonstrated a slightly higher breakdown voltage, whereas the capacitance value remained almost constant (~150 nF/cm2). The linear mobility slightly increased from ~30 to ~35 cm2/Vs when the treatment time increased from 0 to 10 s, whereas a 30 s-treated TFT demonstrated a decreased mobility of ~15 cm2/Vs. The subthreshold swing and the threshold voltage remained in the 100–120 mV/dec. range and near 0 V, respectively. The hysteresis dramatically decreased from ~0.5 V to 0 V when a 10 s treatment was applied, and the 10 s-treated TFT demonstrated the best stability under high current stress (HCS) of 100 μA. The analysis of the tin oxide thin film crystallinity and oxygen environment demonstrated that the a-SnOx remained amorphous, whereas more metal–oxygen bonds were formed with a 10 s NF3 plasma treatment. We also demonstrate that the density of states (DOS) significantly decreased in the 10 s-treated TFT compared to the other conditions. The stability under HCS was attributed to the HfO2/a-SnOx interface quality. [ABSTRACT FROM AUTHOR]

In this work, indium silicon oxide (ISO) thin-film transistors (TFT) were developed with molybdenum as the source and drain contact using sputtering and lithography techniques. The influence of channel length on the electrical properties of the ISO TFTs was studied by varying the channel length from ultra-short 5 µm to 100 µm. The highest mobility of 13.23 cm2/V s with an on/off ratio of 108 order was obtained for the ISO TFT post-annealed at 150°C with a channel length of 5 µm and width of 250 µm. In addition, the bias stress stability of the ISO TFT was measured. [ABSTRACT FROM AUTHOR]

In contrast to lift-off and shadow mask processes, the back-channel wet etching (BCWE) process is suitable for industrial-scale metallization processes for the large-area and mass production of oxide thin-film transistors (TFTs). However, chemical attacks caused by the corrosive metal etchants used in the BCWE process cause unintended performance degradation of oxide semiconductors, making it difficult to implement oxide TFT circuits through industrial-scale metallization processes. Herein, we propose composition engineering of oxide semiconductors to enhance the chemical durability and electrical stability of oxide semiconductors. The chemical durability of InZnO against Al etchants can be improved by increasing the content of indium oxide, which has a higher chemical resistance than zinc oxide. As a result, A damage-free BCWE-based metallization process was successfully demonstrated for oxide TFTs using In-rich InZnO semiconductors. Furthermore, In-rich InZnO TFTs with wet-etched Al electrodes exhibited electrical performance comparable to that of lift-off Al electrodes, without chemical attack issues. [ABSTRACT FROM AUTHOR]

Metal-oxide-semiconductor (MOS)-based thin-film transistors (TFTs) are gaining significant attention in the field of flexible electronics due to their desirable electrical properties, such as high field-effect mobility (μFE), lower IOFF, and excellent stability under bias stress. TFTs have widespread applications, such as printed electronics, flexible displays, smart cards, image sensors, virtual reality (VR) and augmented reality (AR), and the Internet of Things (IoT) devices. In this study, we approach using a low-temperature solution-processed hafnium zirconium oxide (HfZrOx) gate insulator (GI) to improve the performance of lanthanum zinc oxide (LaZnO) TFTs. For the optimization of HfZrO GI, HfZrO films were annealed at 200, 250, and 300 °C. The optimized HfZrO-250 °C GI-based LaZnO TFT shows the μFE of 19.06 cm2V−1s−1, threshold voltage (VTH) of 1.98 V, hysteresis voltage (VH) of 0 V, subthreshold swing (SS) of 256 mV/dec, and ION/IOFF of ~108. The flexible LaZnO TFT with HfZrO-250 °C GI exhibits negligible ΔVTH of 0.25 V under positive-bias-temperature stress (PBTS). The flexible hysteresis-free LaZnO TFTs with HfZrO-250 °C can be widely used for flexible electronics. These enhancements were attributed to the smooth surface morphology and reduced defect density achieved with the HfZrO gate insulator. Therefore, the HfZrO/LaZnO approach holds great promise for next-generation MOS TFTs for flexible electronics. [ABSTRACT FROM AUTHOR]

This review aims to provide a technical roadmap and an overview of recent progress in the development of backplane thin film transistors (TFTs) for organic light-emitting diodes flat panel displays and next-generation flexible displays. In the introduction, we provide a general overview of the research trends for backplane TFTs. The main part describes the current technical level and prospects for amorphous metal oxide semiconducting, metal halide perovskites, and 2D transition metal dichalcogenides TFTs. The summary and prospects are provided in the conclusion section. [ABSTRACT FROM AUTHOR]

Indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs) with a 1 um channel length were successfully fabricated by i-line lithography with a stepper process, resulting in high throughput. The a-IGZO TFT with a channel length of 1 μm exhibits high mobility of 8.77 cm2/Vs with an on/off current ratio of >3 × 1010. The stepper lithography process is capable of defect-free patterning given its precise layer-to-layer alignment and high image resolutions of the types required for large-area high-PPI displays. Consequently, IGZO TFTs can be fabricated on an 8-inch wafer with only minor electrical property deviations in the turn-on voltage, mobility, and on/off ratio. These results indicate that i-line lithography with a stepper process is a promising process for use in cutting-edge large-area electronics industries.

Understanding the density of state (DOS) distribution in solution-processed indium-zinc-oxide (IZO) thin-film transistors (TFTs) is crucial for addressing electrical instability. This paper presents quantitative calculations of the acceptor-like state distribution of solution-processed IZO TFTs using thermal energy analysis. To extract the acceptor-like state distribution, the electrical characteristics of IZO TFTs with various In molarity ratios were analyzed with respect to temperature. An Arrhenius plot was used to determine electrical parameters such as the activation energy, flat band energy, and flat band voltage. Two calculation methods, the simplified charge approximation and the Meyer–Neldel (MN) rule-based carrier–surface potential field-effect analysis, were proposed to estimate the acceptor-like state distribution. The simplified charge approximation established the modeling of acceptor-like states using the charge–voltage relationship. The MN rule-based field-effect analysis validated the DOS distribution through the carrier–surface potential relationship. In addition, this study introduces practical and effective approaches for determining the DOS distribution of solution-processed IZO semiconductors based on the In molarity ratio. The profiles of the acceptor-like state distribution provide insights into the electrical behavior depending on the doping concentration of the solution-processed IZO semiconductors. [ABSTRACT FROM AUTHOR]

Indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs) with a 1 um channel length were successfully fabricated by i-line lithography with a stepper process, resulting in high throughput. The a-IGZO TFT with a channel length of 1 μm exhibits high mobility of 8.77 cm2/Vs with an on/off current ratio of >3 × 1010. The stepper lithography process is capable of defect-free patterning given its precise layer-to-layer alignment and high image resolutions of the types required for large-area high-PPI displays. Consequently, IGZO TFTs can be fabricated on an 8-inch wafer with only minor electrical property deviations in the turn-on voltage, mobility, and on/off ratio. These results indicate that i-line lithography with a stepper process is a promising process for use in cutting-edge large-area electronics industries. [ABSTRACT FROM AUTHOR]

This paper presents a compact model for organic thin-film transistors fabricated in the staggered or coplanar device architecture which includes short-channel effects related to the potential barrier in the channel region, which manifest themselves as threshold voltage roll-off, drain-induced barrier lowering, and subthreshold swing degradation. Furthermore, the effect of non-linear injection due to a work-function mismatch between the source/drain contacts and the semiconductor is considered. The model includes a charge-based capacitance model considering overlap and fringing regions in short-channel multi-finger layout structures. Extensions include a model for drain-current variability, low-frequency noise and non-quasistatic effects. The introduction of physically meaningful fitting parameters provides a high degree of flexibility to the model. The equation package is verified using the results of measurements performed on transistors fabricated on flexible substrates and is available in Verilog-A for an efficient circuit simulation on different design platforms.

Tin monoxide (SnO) has been studied widely over the past several decades due to its promising theoretical p‐type performance. However, limited fabrication processes due to the low thermal and air stability of SnO have resulted in poor performance in thin‐film transistors (TFTs). Here, it is suggested that in situ atomic layer deposition (ALD) of an Al2O3 capping layer can improve the electrical performance in SnO TFTs. By adopting an in situ stacking process, which protects vulnerable SnO thin films from exposure to air and contamination, SnO exhibits enhanced crystallinity, electrical performance, and improved scaling limitation of channel thickness. Especially, in situ stacked Al2O3 on a 7 nm SnO TFT has an exceptionally low subthreshold swing (0.15 V decade−1), high on/off ratio (6.54 × 105), and reasonable mobility (1.14 cm2 V−1 s−1) while the bare SnO TFT is not activated. Computational thermodynamics such as chemical potential analysis, nucleation Gibbs free‐energy calculations, and various analytical techniques are used to reveal the origin of highly crystallized SnO formations via in situ deposition of Al2O3. Finally, state‐of‐the‐art all‐ALD‐channel complementary metal–oxide–semiconductor inverters using n‐type indium gallium zinc oxide and p‐type SnO TFTs are integrated, which exhibit a maximum voltage gain of 240 V V−1 and a noise margin of 89.3%. [ABSTRACT FROM AUTHOR]

To realize oxide semiconductor-based complementary circuits and better transparent display applications, the electrical properties of p-type oxide semiconductors and the performance improvement of p-type oxide thin-film transistors (TFTs) are required. In this study, we report the effects of post-UV/ozone (O3) treatment on the structural and electrical characteristics of copper oxide (CuO) semiconductor films and the TFT performance. The CuO semiconductor films were fabricated using copper (II) acetate hydrate as a precursor material to solution processing and the UV/O3 treatment was performed as a post-treatment after the CuO film was fabricated. During the post-UV/O3 treatment for up to 13 min, the solution-processed CuO films exhibited no meaningful change in the surface morphology. On the other hand, analysis of the Raman and X-ray photoemission spectra of solution-processed CuO films revealed that the post-UV/O3 treatment induced compressive stress in the film and increased the composition concentration of Cu–O lattice bonding. In the post-UV/O3-treated CuO semiconductor layer, the Hall mobility increased significantly to approximately 280 cm2 V−1 s−1, and the conductivity increased to approximately 4.57 × 10−2 Ω−1 cm−1. Post-UV/O3-treated CuO TFTs also showed improved electrical properties compared to those of untreated CuO TFTs. The field-effect mobility of the post-UV/O3-treated CuO TFT increased to approximately 6.61 × 10−3 cm−2 V−1 s−1, and the on-off current ratio increased to approximately 3.51 × 103. These improvements in the electrical characteristics of CuO films and CuO TFTs can be understood through the suppression of weak bonding and structural defects between Cu and O bonds after post-UV/O3 treatment. The result demonstrates that the post-UV/O3 treatment can be a viable method to improve the performance of p-type oxide TFTs. [ABSTRACT FROM AUTHOR]

Metal halide perovskites have attracted a considerable amount of research attention with significant progress made in the field of optoelectronics. Despite their outstanding electrical characteristics, structural defects impede their potential performance due to the polycrystalline nature of solution‐processed perovskite films. Herein, the effective p‐type doping and defect passivation of phenethylammonium tin iodide ((PEA)2SnI4) perovskite films using xanthate additives as a sulfur source is reported. Sulfur can be introduced to the iodine vacancies mainly at the grain boundaries of the perovskite film, passivating the electrical defects originating from the iodine vacancy and increasing the hole concentration. The Fermi‐level shift toward the valence band maximum of the sulfur‐doped perovskite film is confirmed using ultraviolet photoemission spectroscopy, resulting in p‐type doping. Finally, the electrical performance improvement for the 0.2% sulfur‐doped (PEA)2SnI4 thin‐film transistor with a mobility of 1.45 cm2 V−1 s−1, an on/off ratio of 2.9 × 105 is demonstrated, and hysteresis of 10 V is reduced. [ABSTRACT FROM AUTHOR]

Devising a high-throughput additive manufacturing method (HTAM) could aid in fabricating flexible electronic devices with marginal greenhouse gas (GG) emissions and net zero by-products. A roll-to-roll (R2R) gravure printing method is considered a typical platform of HTAM to fabricate carbon nanotube-based flexible electronic devices. However, the large variation in threshold voltage (Vth) in the printed carbon nanotube devices restricts device yield, thereby limiting their practical applications. In this study, the authors would like to show a way of minimizing the variation of Vth in the R2R gravure printed carbon nanotube thin-film transistors (TFTs) by understanding how the morphology of the printed dielectric layer can be controlled during ink drying. Since the formation of an uneven morphology after drying with higher edge thickness, also known as the coffee ring effect (CRE), is one of the key factors causing the variation in Vth, regulating the morphology of the dielectric ink is vital in minimizing the Vth variation of the TFTs printed via R2R gravure. By optimizing the rheological characteristics of the dielectric ink, a homogeneous morphology was attained without CRE, consequently minimizing the Vth variation from 19.6% to 6.9%. Furthermore, the printed device stability was improved by removing the CRE and avoiding the localized bias stress during device operation. Based on this work, the yield, and the stability of R2R gravure printed devices could be improved, enabling the rapid commercialization of additively manufactured flexible devices without the emission of GG or any harmful by-products.

A facile method for chemical doping of conducting polymers is demonstrated with an ionic liquid containing FeCl _4 ^− anions as the oxidizing agents. A drop of the ionic liquid on the film of a typical semicrystalline polymer immediately changed the room temperature conductivity to 500 S cm ^−1 . The highly conductive state originated from both the high doping level and the high crystallinity of the doped film, as confirmed by optical absorption and X-ray diffraction measurements, respectively. Furthermore, the doping level was continuously controlled by the gate voltage of the ionic-liquid-gated transistor structure through an electrochemical dedoping process.

To fabricate oxide thin-film transistors (TFTs) with high performance and excellent stability, preparing high-quality semiconductor films in the channel bulk region and minimizing the defect states in the gate dielectric/channel interfaces and back-channel regions is necessary. However, even if an oxide transistor is composed of the same semiconductor film, gate dielectric/channel interface, and back channel, its electrical performance and operational stability are significantly affected by the thickness of the oxide semiconductor. In this study, solution process-based nanometer-scale thickness engineering of InZnO semiconductors was easily performed via repeated solution coating and annealing. The thickness-controlled InZnO films were then applied as channel regions, which were fabricated with almost identical film quality, gate dielectric/channel interface, and back-channel conditions. However, excellent operational stability and electrical performance suitable for oxide TFT backplane was only achieved using an 8 nm thick InZnO film. In contrast, the ultrathin and thicker films exhibited electrical performances that were either very resistive (high positive VTh and low on-current) or excessively conductive (high negative VTh and high off-current). This investigation confirmed that the quality of semiconductor materials, solution process design, and structural parameters, including the dimensions of the channel layer, must be carefully designed to realize high-performance and high-stability oxide TFTs.

With the increase in electronic devices across various applications, there is rising demand for selective carrier control. The split-gate consists of a gate electrode divided into multiple parts, allowing for the independent biasing of electric fields within the device. This configuration enables the potential formation of both p- and n-channels by injecting holes and electrons owing to the presence of the two gate electrodes. Applying voltage to the split-gate allows for the control of the Fermi level and, consequently, the barrier height in the device. This facilitates band bending in unipolar transistors and allows ambipolar transistors to operate as if unipolar. Moreover, the split-gate serves as a revolutionary tool to modulate the contact resistance by controlling the barrier height. This approach enables the precise control of the device by biasing the partial electric field without limitations on materials, making it adaptable for various applications, as reported in various types of research. However, the gap length between gates can affect the injection of the electric field for the precise control of carriers. Hence, the design of the gap length is a critical element for the split-gate structure. The primary investigation in this review is the introduction of split-gate technology applied in various applications by using diverse materials, the methods for forming the split-gate in each device, and the operational mechanisms under applied voltage conditions.

Abstract Tin monoxide (SnO) has been studied widely over the past several decades due to its promising theoretical p‐type performance. However, limited fabrication processes due to the low thermal and air stability of SnO have resulted in poor performance in thin‐film transistors (TFTs). Here, it is suggested that in situ atomic layer deposition (ALD) of an Al2O3 capping layer can improve the electrical performance in SnO TFTs. By adopting an in situ stacking process, which protects vulnerable SnO thin films from exposure to air and contamination, SnO exhibits enhanced crystallinity, electrical performance, and improved scaling limitation of channel thickness. Especially, in situ stacked Al2O3 on a 7 nm SnO TFT has an exceptionally low subthreshold swing (0.15 V decade−1), high on/off ratio (6.54 × 105), and reasonable mobility (1.14 cm2 V−1 s−1) while the bare SnO TFT is not activated. Computational thermodynamics such as chemical potential analysis, nucleation Gibbs free‐energy calculations, and various analytical techniques are used to reveal the origin of highly crystallized SnO formations via in situ deposition of Al2O3. Finally, state‐of‐the‐art all‐ALD‐channel complementary metal–oxide–semiconductor inverters using n‐type indium gallium zinc oxide and p‐type SnO TFTs are integrated, which exhibit a maximum voltage gain of 240 V V−1 and a noise margin of 89.3%.

Abstract Metal halide perovskites have attracted a considerable amount of research attention with significant progress made in the field of optoelectronics. Despite their outstanding electrical characteristics, structural defects impede their potential performance due to the polycrystalline nature of solution‐processed perovskite films. Herein, the effective p‐type doping and defect passivation of phenethylammonium tin iodide ((PEA)2SnI4) perovskite films using xanthate additives as a sulfur source is reported. Sulfur can be introduced to the iodine vacancies mainly at the grain boundaries of the perovskite film, passivating the electrical defects originating from the iodine vacancy and increasing the hole concentration. The Fermi‐level shift toward the valence band maximum of the sulfur‐doped perovskite film is confirmed using ultraviolet photoemission spectroscopy, resulting in p‐type doping. Finally, the electrical performance improvement for the 0.2% sulfur‐doped (PEA)2SnI4 thin‐film transistor with a mobility of 1.45 cm2 V−1 s−1, an on/off ratio of 2.9 × 105 is demonstrated, and hysteresis of 10 V is reduced.

Here, we report the high-performance amorphous gallium indium tin oxide (a-IGTO) thin-film transistor (TFT) with zirconium aluminum oxide (ZAO) gate insulator by spray pyrolysis. The Ga ratio in the IGTO precursor solution varied up to 20%. The spray pyrolyzed a-IGTO with a high-k ZAO gate insulator (GI) exhibits the field-effect mobility (μFE) of 16 cm2V−1s−1, threshold voltage (VTH) of −0.45 V subthreshold swing (SS) of 133 mV/dec., and ON/OFF current ratio of ~108. The optimal a-IGTO TFT shows excellent stability under positive-bias-temperature stress (PBTS) with a small ΔVTH shift of 0.35 V. The enhancements are due to the high film quality and fewer interfacial traps at the a-IGTO/ZAO interface. Therefore, the spray pyrolyzed a-IGTO TFT can be a promising candidate for flexible TFT in the next-generation display. [ABSTRACT FROM AUTHOR]

Tin (Sn2+)‐based halide perovskites have been developed as the most promising alternatives to their toxic Pb‐based counterparts in optoelectronic devices. However, the facile tin vacancy formation and easy oxidization characteristics make Sn2+‐based perovskites highly p‐doped with excessive hole concentrations, which significantly hinder their applications. Herein, we demonstrate a potent hole inhibitor of antimony fluoride (SbF3), which possesses a higher hole‐suppression capability than conventional tin fluoride (SnF2). A small amount of SbF3 allows a wide range of hole‐density modulation with no or less SnF2 addition, thus mitigating the negative effects of using only SnF2. A SnF2/SbF3 co‐additive approach was further developed to achieve high‐performance Sn2+ perovskite thin‐film transistors operated in the enhancement mode with a five‐fold enhancement of the field‐effect mobility and improved operational stability compared to using only SnF2. We expect that the SbF3 hole suppressor and co‐additive approach can provide opportunities for the development of high‐efficiency Sn2+‐perovskite optoelectronic devices. [ABSTRACT FROM AUTHOR]

The printability of reliable gate dielectrics and their influence on the stability of the device are some of the primary concerns regarding the practical application of printed transistors. Major ongoing research is focusing on the structural properties of dielectric materials and deposition parameters to reduce interface charge traps and hysteresis caused by the dielectric–semiconductor interface and dielectric bulk. This research focuses on improving the dielectric properties of a printed polymer material, cross-linked polyvinyl phenol (crPVP), by optimizing the cross-linking parameters as well as the aerosol jet printability. These improvements were then applied to the fabrication of completely printed carbon nanotube (CNT)-based thin-film transistors (TFT) to reduce the gate threshold voltage (Vth) and hysteresis in Vth during device operation. Finally, a fully aerosol-jet-printed CNT device was demonstrated using a 2:1 weight ratio of PVP with the cross-linker poly(melamine-co-formaldehyde) methylated (PMF) in crPVP as the dielectric material. This device shows significantly less hysteresis and can be operated at a gate threshold voltage as low as −4.8 V with an on/off ratio of more than 104. [ABSTRACT FROM AUTHOR]

The preparation of thin-film transistors (TFTs) with InGaZnO (IGZO) channels using sol–gel technology has the advantages of simplicity in terms of process and weak substrate selectivity. We prepared a series of TFT devices with a top contact and bottom gate structure, in which the top contact was divided into rectangular and circular structures of drain/source electrodes. The field-effect performance of TFT devices with circular pattern drain/source electrodes was better than that with a traditional rectangular structure on both substrates. The uniform distribution of the potential in the circular electrode structure was more conducive to the regulation of carriers under the same channel length at different applied voltages. In addition, with the development of transparent substrate devices, we also constructed a hafnium oxide (HfO2) insulation layer and an IGZO active layer on an indium tin oxide conductive substrate, and explored the effect of circular drain/source electrodes on field-effect properties of the semitransparent TFT device. The IGZO deposited on the HfO2 dielectric layer by spin-coating can effectively reduce the surface roughness of the HfO2 layer and optimize the scattering of carriers at the interface in TFT devices. [ABSTRACT FROM AUTHOR]

The current mobile devices are moving towards flexible electronics. Introducing crystalline oxide semiconductors on flexible substrates is important to satisfy the requirements of high-resolution displays on flexible substrates. This study investigates the low-cost, as-grown polycrystalline (Poly) InGaO thin film transistor by spray pyrolysis on polyimide (PI) substrate. Grazing Incidence X-ray Diffraction (GI-XRD) measurements demonstrate that In 0.8 Ga 0.2 O, In 0.7 Ga 0.3 O, and In 0.5 Ga 0.5 O compositions exhibit crystallization on-set temperatures of ∼330, ∼350, and ∼415°C, respectively. Poly-In 0.7 Ga 0.3 O thin film with lower oxygen-vacancy (∼15 %) and less than 5 % O-H group could be achieved at the substrate temperature of 370°C. The hysteresis-free device performance with an average saturation mobility of 43.73 cm2V−1s−1 has been obtained using the poly-In 0.7 Ga 0.3 O with optimized N 2 O plasma treatment on the poly-oxide thin film. The TFTs show remarkable stability under humid environments and various stress conditions such as positive bias temperature, negative bias temperature, and mechanical stresses. In addition, the 96-stage gate shift register made of poly-In 0.7 Ga 0.3 O TFTs by spray pyrolysis exhibits the rising and falling times of less than 820 ns. Therefore, the poly-In 0.7 Ga 0.3 O TFTs by spray pyrolysis could be used for high-resolution, cost-effective, flexible active-matrix light-emitting displays. [Display omitted] • Growth of polycrystalline InGaO thin films by spray pyrolysis. • High mobility (>50 cm2/Vs), coplanar crystalline InGaO TFT on PI substrate. • Excellent stability of poly-InGaO TFTs under bias, humidity, and mechanical stress. • Controlling the carrier concentration of poly-In 0.7 Ga 0.3 O by N 2 O plasma treatment. • Fully operation of 96-stage gate driver circuit made of InGaO TFTs. [ABSTRACT FROM AUTHOR]

The 2T2C circuits based on LTPS-TFTs adopts a small TFT W/L to reduce switch error and effectively avoid the impact of I OFF , acting as driving circuits for e-paper with perfect image sticking performance. [Display omitted] • LTPS-TFTs with small W/L is adopted in e-paper to reduce switch error, and thus significantly improving image sticking performance. • LTPS-TFTs with extremely low off-state leakage current (I OFF) even at a large source-drain voltage (V DS) of 30 V were obtained through detailed explorations of LTPS process technology. • The aging test results of the LTPS-TFTs exhibits a new physical phenomenon, that is, the I OFF of the LTPS-TFTs has a strict matching characteristic with the aging direction. • A novel 2T2C driving circuit for the e-paper was reported to effectively avoid the adverse effects of I OFF on the frame holding period. In this work, we systematically investigate low-temperature polycrystalline silicon (LTPS)-based driving circuits of electronic paper for the aim of adopting small width/length ratio (W/L) of LTPS-based thin film transistors (TFTs) to reduce switch error and thus improve image sticking. Firstly, LTPS-TFTs with extremely low off-state leakage current (I OFF) even at a large source-drain voltage (V DS) of 30 V were obtained through detailed explorations of LTPS process technology. Meanwhile, the high on-state current (I ON) of LTPS-TFTs also meet the requirements of fast signal writing to the storage capacitor due to their extremely high field-effect mobility (approximately 100 cm2/V⋅s), making it possible to fabricate TFTs with relatively small W/L, thereby minimizing switch error. The I D -V D test results reveal that the produced LTPS-TFTs can effectively withstand the maximum voltage difference of 30 V during product operation. Subsequently, the optimal W/L of the LTPS-TFT was determined through experimental results. Then, reliability test was conducted on the obtained LTPS-TFTs, revealing that the threshold voltage (V TH) of the LTPS-TFTs shifted by 0.08 V after 7200 s under negative bias temperature stress (NBTS), and only by 0.19 V under positive bias temperature stress (PBTS). The aging test results of the aforementioned LTPS-TFTs exhibits a new physical phenomenon, that is, the I OFF of the LTPS-TFTs has a strict matching characteristic with the aging direction. Next, we proposed a novel 2T2C driving circuit for the e-paper, which can effectively avoid the adverse effects of I OFF on the frame holding period, and plotted it into an array layout. Finally, we combined the optimal fabricating process of the LTPS-TFTs with the 2T2C driving circuit design scheme to produce an e-paper with outstanding image sticking performance. [ABSTRACT FROM AUTHOR]

• Low temperature polycrystalline silicon. • Thin-film transistor. • Pixel compensation circuit. • Short-time image sticking. • Luminance fluctuation. Accurate compensation operation of low-temperature polycrystalline-silicon (LTPS) thin-film transistor (TFT) in pixel circuits is crucial to achieve steady and uniform luminance in organic light-emitting diode (OLED) display panels. However, the device characteristics fluctuate over time due to various traps in the LTPS thin film transistor and at the interface with the gate insulator, resulting in abnormal phenomena such as short-time image sticking and luminance fluctuation, which degrade display quality during image change. Considering these phenomena, transient analysis was conducted through device simulation to optimize the pixel compensation circuit. In particular, we analyzed the behavior of traps within LTPS TFT in correlation with compensation circuit operation, and based on this, proposed a methodology for designing a reset voltage scheme for the driver TFT to reduce the image sticking phenomenon. [ABSTRACT FROM AUTHOR]

The zinc-tin-oxide (ZTO) thin-film transistor (TFT) is one of the most promising candidates for advanced display applications, though its popularity is limited by its performances. In this work, a heterojunction channel strategy was adopted to regulate the electron transport behaviors and the TFT performances by manipulating the concentration and the distribution of oxygen vacancies, and a reasonable physical model was proposed based on experimental and simulation results. It is difficult to mediate the contradiction between mobility and threshold voltage for the single channel. Via a heterojunction channel strategy, desirable TFT performances, with mobility of 12.5 cm2/Vs, threshold voltage of 1.2 V and Ion/Ioff of 3 × 109, are achieved when the oxygen-vacancy-enriched layer gets close to the gate insulator (GI). The enhanced performances can be mainly attributed to the formation of two-dimensional electron gas (2DEG), the insensitive potential barrier and the reasonable distribution of oxygen vacancy. On the contrary, when the oxygen-vacancy-enriched layer stays away from GI, all the main performances degenerate due to the vulnerable potential well. The findings may facilitate the development and application of heterojunction channels for improving the performances of electronic devices.

The density of donor-like state distributions in solution-processed indium–zinc-oxide (IZO) thin-film transistors (TFTs) is thoroughly analyzed using photon energy irradiation. This study focuses on quantitatively calculating the distribution of density of states (DOS) in IZO semiconductors, with a specific emphasis on their variation with indium concentration. Two calculation methods, namely photoexcited charge collection spectroscopy (PECCS) and photocurrent-induced DOS spectroscopy (PIDS), are employed to estimate the density of the donor-like states. This dual approach not only ensures the accuracy of the findings but also provides a comprehensive perspective on the properties of semiconductors. The results reveal a consistent characteristic: the Recombination–Generation (R-G) center energy ET, a key aspect of the donor-like state, is acquired at approximately 3.26 eV, irrespective of the In concentration. This finding suggests that weak bonds and oxygen vacancies within the Zn-O bonding structure of IZO semiconductors act as the primary source of R-G centers, contributing to the donor-like state distribution. By highlighting this fundamental aspect of IZO semiconductors, this study enhances our understanding of their charge-transport mechanisms. Moreover, it offers valuable insight for addressing stability issues such as negative bias illumination stress, potentially leading to the improved performance and reliability of solution-processed IZO TFTs. The study contributes to the advancement of displays and technologies by presenting further innovations and applications for evaluating the fundamentals of semiconductors.

We studied the impact of NF3 plasma treatment on the HfO2 gate insulator of amorphous tin oxide (a-SnOx) thin-film transistors (TFTs). The plasma treatment was for 0, 10, or 30 s. The HfO2 insulator demonstrated a slightly higher breakdown voltage, whereas the capacitance value remained almost constant (~150 nF/cm2). The linear mobility slightly increased from ~30 to ~35 cm2/Vs when the treatment time increased from 0 to 10 s, whereas a 30 s-treated TFT demonstrated a decreased mobility of ~15 cm2/Vs. The subthreshold swing and the threshold voltage remained in the 100–120 mV/dec. range and near 0 V, respectively. The hysteresis dramatically decreased from ~0.5 V to 0 V when a 10 s treatment was applied, and the 10 s-treated TFT demonstrated the best stability under high current stress (HCS) of 100 μA. The analysis of the tin oxide thin film crystallinity and oxygen environment demonstrated that the a-SnOx remained amorphous, whereas more metal–oxygen bonds were formed with a 10 s NF3 plasma treatment. We also demonstrate that the density of states (DOS) significantly decreased in the 10 s-treated TFT compared to the other conditions. The stability under HCS was attributed to the HfO2/a-SnOx interface quality.

In contrast to lift-off and shadow mask processes, the back-channel wet etching (BCWE) process is suitable for industrial-scale metallization processes for the large-area and mass production of oxide thin-film transistors (TFTs). However, chemical attacks caused by the corrosive metal etchants used in the BCWE process cause unintended performance degradation of oxide semiconductors, making it difficult to implement oxide TFT circuits through industrial-scale metallization processes. Herein, we propose composition engineering of oxide semiconductors to enhance the chemical durability and electrical stability of oxide semiconductors. The chemical durability of InZnO against Al etchants can be improved by increasing the content of indium oxide, which has a higher chemical resistance than zinc oxide. As a result, A damage-free BCWE-based metallization process was successfully demonstrated for oxide TFTs using In-rich InZnO semiconductors. Furthermore, In-rich InZnO TFTs with wet-etched Al electrodes exhibited electrical performance comparable to that of lift-off Al electrodes, without chemical attack issues.

The theory of oxygen vacancy related deep energy defects and valence band offset (VBO) between gate insulator and channel codetermining the threshold voltage shift $(\Delta {V}_{\mathbf {\mathrm {TH}}})$ of ZnO thin film transistor under negative gate bias and illumination stress (NBIS) is proposed and investigated systematically. Two kinds of ZnO thin film transistors are fabricated by atomic layer deposition with different gate oxide structures, a control sample with Al2O3 gate oxide and an improved sample with SiO2/Al2 ${\text{O}}_{3 }$ gate oxide structures. Among two kinds of devices, the device with SiO2/Al2 ${\text{O}}_{3 }$ gate oxide achieves a smaller $\mathbf {\mathrm {\Delta }}{V}_{\mathbf {\mathrm {TH}}}$ under the NBIS with SiO2 thin film acting as a holes-blocking layer, despite the existence of more defects than control device. The improvement in stability is attributed to large VBO up to 3.08 eV. Moreover, the device with SiO2/Al2 ${\text{O}}_{3 }$ gate oxide is evaluated on a 500-nit LCD back light to simulate the practical working environment in displays, which exhibits good stability of ${\mathbf {\Delta }{V}}_{\mathbf {\mathrm {TH}}}\,\,=\,\,-0.3$ V for 3600 seconds.

A gate driver in array (GIA) design based on the amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) is developed for narrow border displays. In the design, each TFT in the gate driver circuits is divided into a certain number of smaller size devices, which can be placed in different subpixels. Therefore, the pixel aperture ratio loss is minimized, and uniform placement of the gate driver circuits over the pixel array area is able to be achieved. The proposed step-like repeating block structure further reduces the occupied area of the signal interconnects. A 12.4-inch fringe field switching (FFS) liquid crystal display (LCD) panel of ultra-narrow border (0.5 mm) is demonstrated with reliable operation based on this GIA design, proving its potential for practical applications.