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The conventional three-level active-neutral-point-clamped (ANPC) inverter requires high dc-link voltage at least twice the peak of ac output. To reduce the dc-link voltage, a recent topology that enhanced the voltage gain from half to unity has been presented. In this letter, an alternative ANPC topology is established by using two T-type inverters. Two floating capacitors with self-voltage balancing capability are integrated to achieve a voltage-boosting gain of 1.5. In addition, the proposed topology is capable of generating seven voltage levels. Its operation is validated through circuit analysis followed by experimental results of a prototype. [ABSTRACT FROM AUTHOR]

This paper proposes the new clamping angle control (CAC) pulse width modulation (PWM) method to restore its maximum linear modulation range of voltage source inverters (VSIs) reduced by the duty ratio limitation in hardware implementation, which makes the VSIs to operate nonlinearly in the high modulation range. The deadtime and the bootstrap gate driver circuit mainly cause this duty ratio limitation in practice. In particular, the bootstrap gate driver circuit is used in many industrial applications by avoiding the additional power supply to apply the gate-source voltage of power switches, and therefore making the VSIs to be small size with the low cost. First, the proposed CACPWM method is theoretically analyzed. Then, it is applied in the high modulation range to overcome the limitation of the duty ratio due to the use of the bootstrap gate driver circuit. Thereafter, its practical effectiveness is verified by both simulation and experimental tests. Also, the resulting harmonic distortions are compared with those by the conventional PWM methods. [ABSTRACT FROM AUTHOR]

The purpose of neutral-point voltage balancing algorithms in the three-level neutral-point clamped (3L-NPC) topology is to eliminate the voltage unbalance of top- and bottom-side dc-link voltages (neutral-point voltage). These algorithms are divided into dc unbalance and ac unbalance compensation methods. The dc unbalance causes distortion of output currents; therefore, this problem has to be solved. The ac unbalance implies that there is an ac ripple in the top- and bottom-side dc-link voltages. In applications using 3L-NPC topology, a large dc-link capacitor value is required to mitigate this ac unbalance problem. As a result, the size and the cost of applications become large and expensive. In this paper, a compensation method for mitigating the ac unbalance of the neutral-point voltage is proposed, which causes the dc-link capacitor value to be small, when a carrier-based pulse width modulation method is applied. The proposed method compensates the ac unbalance of the neutral-point voltage by adding an optimal compensation value to the reference duty signals. This compensation value is calculated simply by currents and reference duty signals. The calculation process of the optimal compensation value is discussed, and the effectiveness of the proposed method is verified with simulations and experiments. [ABSTRACT FROM PUBLISHER]

This paper presents a new direct torque controlled space vector modulated method to improve the sensorless performance of matrix converter drives using a parameter estimation scheme. The flux and torque error are geometrically combined in a new flux leakage vector to make a stator command voltage vector in a deadbeat manner. A new sensorless method of estimating the rotor speed, flux, stator resistance, and rotor resistance is derived and verified with experimental results. Common terms in the error dynamics are utilized to find a simpler error model involving some auxiliary variables. Using this error model, the state estimation problem is converted into a parameter estimation problem assuming the rotor speed is constant. The proposed adaptive schemes are determined so that the whole system is stable in the sense of Lyapunov. The effectiveness of the proposed algorithm is verified by experiments. [ABSTRACT FROM AUTHOR]

This paper presents a new sensorless vector control system for high-performance induction motor drives fed by a matrix converter with nonlinearity compensation. The nonlinear voltage distortion that is caused by commutation delay and ON-state voltage drop in the switching devices is corrected by a new matrix converter model. A reduced-order extended Luenberger observer is employed to bring better response in the whole speed operation range, and a method to select the observer gain is presented. Experimental results are shown to illustrate the performance of the proposed system. [ABSTRACT FROM AUTHOR]

The utilization of three-level T-type (3L T-type) inverters in finite set-model predictive control (FS-MPC) of grid-connected systems yielded good performance in terms of current ripples and total harmonic distortions. To further improve the system's performance, discrete space vector modulation (DSVM) was utilized to synthesize a higher number of virtual voltage vectors. A deadbeat control (DBC) method was used to alleviate the computational burden and provide the optimum voltage vector selection. However, 3L inverters are known to suffer from voltage deviation, owing to the imbalance of the neutral-point voltage. We have proposed a simplified control strategy for balancing the neutral point in the FS-MPC with DSVM and DBC of grid-connected systems, not requiring a weighting factor or additional cost function calculation. The effectiveness of the proposed method was validated using simulation and experiment results. Our experimental results show that the execution time of the proposed algorithm was significantly reduced, while its current quality performance was not affected. [ABSTRACT FROM AUTHOR]

This paper presents an improved rotating restart method for a sensorless permanent magnet synchronous motor (PMSM) drive system using repetitive zero voltage vectors. To restart the sensorless PMSM drive system, a method for estimating initial rotor position and speed is required due to the absence of sensors such as encoders and resolvers. The rotor position and speed can be estimated using the short-circuit current vectors generated by applying zero voltage vectors. However, the estimated rotor position and speed can be inaccurate. The inaccurate rotor position that causes the current is distorted by the back-electromotive force of the PMSM, and it is impossible to precisely control the system. Therefore, an improved rotating restart method for the sensorless PMSM drive system using repetitive zero voltage vectors is proposed. The effectiveness of the proposed method is verified through simulation and experimental results using a 5-kW PMSM drive system. [ABSTRACT FROM AUTHOR]

This paper proposes a novel discontinuous pulse-width modulation (DPWM) method to reduce the current harmonics and improve the system efficiency for a single-phase three-level neutral-point clamped inverter. In single-phase inverters, the unipolar pulse-width modulation (UP-PWM) method is commonly used. However, this method has the disadvantage of power losses due to numerous switching operations. Conventional DPWM methods reduce the power losses and improve efficiency but increase the current total harmonic distortion (THD). To overcome these weaknesses, this paper proposes a hybrid DPWM switching method combining two PWM methods: the UP-PWM method and the conventional DPWM method called one-pole clamped PWM method. Since the proposed DPWM method offers all the advantages of both PWM methods, the optimal performance—with regard to the power losses and current THD—is obtained. The combination of two PWM methods is investigated by analyzing the power losses and current THD. Based on the analysis, the process determining the optimal operating condition is introduced. The effectiveness of the proposed DPWM method is demonstrated through simulations and experiments. [ABSTRACT FROM AUTHOR]

A new pulsewidth modulation (PWM) strategy which is an alternative approach of the discontinuous PWM (DPWM) for a three-level neutral-point-clamped (NPC) inverter is proposed in this paper. A three-level NPC inverter is completely mature and very well-established topology in high-power applications. However, the three-level NPC inverter has an inheritance problem of the neutral-point voltage unbalancing due to the split dc-link capacitors. This structure can cause large neutral-point voltage ripple. Furthermore, output currents of the three-level NPC inverter are distorted by the neutral-point voltage ripple. Therefore, the neutral-point voltage must be controlled. In this paper, a new DPWM method using two different offsets for the neutral-point ripple reduction is proposed and the effectiveness of the proposed DPWM method is verified by using the simulation and the experimental results. [ABSTRACT FROM PUBLISHER]

Multilevel rectifier topologies are commonly used in wide-power range applications. The T-type rectifier topology, which is a three-level topology, has an advantage in terms of efficiency compared to a neutral-point clamped (NPC)-type topology. In applications using the T-type rectifier topology, improving reliability has gained increased attention recently. A tolerance control for T-type rectifiers is necessary to improve the reliability of applications. When an open fault of switches connected to the neutral-point occurs, the NPC-type rectifier cannot restore distorted input currents, on the other hand, the T-type rectifier can eliminate the input current distortion completely. In this paper, we report two studies: 1) a three-level switching-oriented tolerance control, which is advantageous in terms of efficiency, for the Sx2 and Sx3 open-switch faults of the T-type rectifier and 2) comparison of the proposed tolerance control with two existing tolerance controls. In particular, the current total harmonic distortion, dc-link voltage ripple, and switch losses of these tolerance controls are analyzed by using simulation and experimental results. [ABSTRACT FROM AUTHOR]

This paper proposes a method to reduce the low-frequency neutral-point voltage oscillations. The neutral-point voltage oscillations are considerably reduced by adding a time offset to the three-phase turn-on times. The proper time offset is simply calculated considering the phase currents and dwell time of small- and medium-voltage vectors. However, if the power factor is lower, there is a limitation to eliminate neutral-point oscillations. In this case, the proposed method can be improved by changing the switching sequence properly. Additionally, a method for neutral-point voltage balancing is also proposed. The change in switching frequency by the proposed method and its effects on the outputs are negligible. Simulation and experimental results verify the validity and feasibility of the proposed strategy. [ABSTRACT FROM PUBLISHER]

This paper proposes a neutral-point voltage balancing method for a three-level inverter that uses discontinuous pulse width modulation (DPWM). The performance of a three-level inverter system is affected by the neutral-point voltage unbalancing. Therefore, the voltages of series connected dc-link capacitors should be equal. Generally, the offset voltage is added to reference voltages in the conventional voltage balancing method. However, when using DPWM, the performance of conventional balancing method is limitary because turn-on and turn-off switching occurs at regular intervals. The proposed method is implemented by adjusting the discontinuous pulsewidth of positive and negative cycle. The proposed method maintains low switching losses and achieves the effective voltage balancing, without additional hardware and complex calculations. Simulation and experimental results confirm the feasibility and effectiveness of the proposed method. [ABSTRACT FROM PUBLISHER]

The switched-capacitor-based cascaded multilevel inverters (CMI) have been emerging due to their voltage boosting capability. Unfortunately, they suffer from impulse charging current and nonuniform operation. This article presents a topology termed as dual-T-type five-level CMI to resolve these problems without compromising the desirable voltage boosting characteristic. The main idea is to integrate a half bridge and an inductor to soft charge a capacitor that is connected in series with the dc source. The capacitor enables the voltage gain boosted to two, while the control of eight power switches that constitutes a dual-T structure enables five voltage levels generation. In addition, uniform operation is achieved for cascaded extensions. The operating principle of the proposed topology is analyzed and elaborated. For validation, simulation, and experimental results of a prototype are presented. [ABSTRACT FROM AUTHOR]

This paper presents an optimized switching strategy to reduce the dc-link ripple current for three-level photovoltaic (PV) inverters. The large electrolytic capacitors are commonly used for the dc link of power electronics applications to stabilize the dc-link voltage. The most important factor of designing the dc-link capacitor is the allowable current ripple. The over-ripple current flowing through the capacitor causes a high heat loss, shortened lifespan, low stability, and reliability. The proposed switching scheme selects voltage vectors and reconfigures dwelling order of the vectors to reduce the capacitor ripple current. This switching method is able to extend the lifetime of the dc-link capacitors by simple software programming. In addition, this switching method reduces the common-mode voltage and leakage current that represent high reliability and safety of the system. The effectiveness of the proposed method is verified with simulations and experimental results. [ABSTRACT FROM AUTHOR]

This paper proposes a generalized scheme of new soft-switching interleaved boost converters that is suitable for high step-up and high-power applications. The proposed converter is configured with proper numbers of series and parallel connected basic cells in order to fulfill the required output voltage and power levels, respectively. This leads to flexibility in device selection resulting in high component availability and easy thermal distribution. Design examples of determining the optimum circuit configuration for given output voltage and power level are presented. Experimental results from a 1.5-kW prototype are provided to validate the proposed concept. [ABSTRACT FROM AUTHOR]