Search

An algorithm that is suitable for the computation of symmetrical components is presented in this paper. The structure of the algorithm consists of four decupled linear modules: the first for adaptive filtering of input signals, the second for frequency estimation, the third for symmetrical components estimation, and the fourth for the amplitudes of the component estimation. Filters are used to minimize the noise effect and to eliminate the presence of harmonics. A simple method for online designing of digital filters of sinusoidal signals is used in this paper. This method uses closed forms for calculation of filter coefficients and requires modest computations. The symmetrical components estimation through adaptive transformation matrix of phase shifters used in this paper makes it possible to get instantaneous symmetrical components independently on the frequency variation with modest-computation requirements. The technique used in this paper provides accurate frequency estimates with the maximum error of 0.002 Hz and symmetrical components estimation with the maximum error of 0.03% for SNR = 60 dB in about 25 ms. The algorithm is not sensitive to power-system frequency changes and to the harmonic distortion of the input signals. To demonstrate the performance of the developed algorithm, computer-simulated data records have been processed. It has been found that the proposed algorithm is suitable for real-time applications. [ABSTRACT FROM AUTHOR]

In this paper, efficient architectures for realizing the recursive discrete cosine transform (DCT) and the recursive inverse DCT (IDCT) are proposed. By respectively folding the inputs of the DCT and the outputs of the IDCT, efficient formulations of the DCT and IDCT are derived to construct a transform kernels. The data throughout per transformation is twice that of the existing methods by spending only half of the computational cycles used by the single folding algorithms. To further improve efficiency, the double folding recursive architectures of the DCT and IDCT are developed. The computational cycles of the DCT are half of the single folding method, and the data throughout of the IDCT is twice that of the single folding method. The regular and modular properties of the proposed recursive archietectures are suitable for very scale integration (VLSI) implementation. With high throughout advantage, the proposed structures could be implemented with less power consumption, which could be applied to low rate video in mobile and portable information appliances. [ABSTRACT FROM AUTHOR]