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In [Y.B. Jun, S.S. Ahn, On pseudo BCH-algebras, Applied Mathematical Sciences, 39 (2015), 1931-1939], the authors introduced pseudo BCH-algebras and defined in such algebras a binary relation , but it is not well defined. Mathematics Subject Classification: 06F35, 03G25

It is well-known that cyclic codes have efficient encoding and decoding algorithms. In recent years, antiprimitive BCH codes have attracted a lot of attention. The objective of this paper is to study BCH codes of this type over finite fields and analyse their parameters. Some lower bounds on the minimum distance of antiprimitive BCH codes are given. The BCH codes presented in this paper have good parameters in general, containing many optimal linear codes. In particular, two open problems about the minimum distance of BCH codes of this type are partially solved in this paper.

Generalized integrated interleaved (GII) error-correcting codes nest sub-codewords to form codewords of more powerful codes. They can achieve hyper-speed decoding with good error correction capability. For GII codes built on BCH codes, the first decoding stage is to decode individual BCH sub-words. This stage largely determines the throughput and dominates the area of the overall decoder. Unlike that in traditional BCH decoding, longer polynomials need to be kept in the key-equation solver (KES) step of the first stage in order to continue the KES step in the second-stage nested decoding of GII codes. To take advantage of the very fast storage class memories (SCMs), GII codes with 3-error-correcting BCH sub-codewords can be utilized. This paper proposes a low-complexity and high-speed design for the KES of 3-error-correcting BCH sub-word decoding. Formulas are developed to compute the KES results directly instead of utilizing the traditional iterative process. More importantly, through analyzing the properties of the involved variables, the coefficients are scaled and reformulated to substantially reduced the complexity. Detailed hardware implementation architectures are also developed in this paper. Our design achieves three times throughput with 20.2% smaller area than the best prior design for a code over GF(210).

Self-orthogonal codes are an important type of linear codes due to their wide applications in communication and cryptography. The Euclidean (or Hermitian) hull of a linear code is defined to be the intersection of the code and its Euclidean (or Hermitian) dual. It is clear that the hull is self-orthogonal. The main goal of this paper is to obtain self-orthogonal codes by investigating the hulls. Let $\mathcal {C}_{(r,r^{m}-1,\delta,b)}$ be the primitive BCH code over $\mathbb {F}_{r}$ of length $r^{m}-1$ with designed distance $\delta $ , where $\mathbb {F}_{r}$ is the finite field of order $r$ . In this paper, we will present Euclidean (or Hermitian) self-orthogonal codes and determine their parameters by investigating the Euclidean (or Hermitian) hulls of some primitive BCH codes. Several sufficient and necessary conditions for primitive BCH codes with large Hermitian hulls are developed by presenting lower and upper bounds on their designed distances. Furthermore, some Hermitian self-orthogonal codes are proposed via the hulls of BCH codes and their parameters are also investigated. In addition, we determine the dimensions of the code $\mathcal {C}_{(r,r^{2}-1,\delta,1)}$ and its hull in both Hermitian and Euclidean cases for $2 \le \delta \le r^{2}-1$ . We also present two sufficient and necessary conditions on designed distances such that the hull has the largest dimension.

Generalized integrated interleaved (GII) codes nest linear block codewords to generate codewords belonging to stronger linear block codes. They can achieve very high throughput with excellent error-correcting capability. GII codes can be based on either Reed-Solomon (RS) or BCH codes. GII-BCH codes are the most promising candidate for error correction in next-generation terabit/s Flash and storage class memories, and optical communications. On the other hand, GII decoder implementation faces many challenges. In particular, the key equation solver (KES) in the nested decoding process causes not only clock frequency bottleneck but also large area. Although techniques have been developed recently to address these issues for GII-RS codes, they cannot be directly extended for binary GII-BCH codes if every other iteration of the nested KES is skipped to reduce the latency. Two instead of one higher-order syndromes need to be incorporated into each nested KES iteration and this makes the implementation much more challenging. In this paper, algorithmic reformulations and architectural modifications are developed to eliminate the clock frequency bottleneck and reduce the area of GII-BCH nested KES. Additionally, the number of processing elements is substantially reduced by analyzing the minimum number of coefficients to keep for the involved polynomials without undesirable degradation on the error-correcting performance. The critical path of the proposed scaled nested BCH KES architecture with reduced processing elements is only one multiplier and three adders. For an example GII-BCH code over ${GF}(2^{12})$ that has a ${t}_{v}=58$ -error-correcting code as the most powerful code generated by the nesting, our design also further reduces the area by 33%.

In this paper, a novel architecture of an SRAM-based Physical Unclonable Function (PUF) whose unstable cells are identified and masked by a “capacitive tilt” preselection test is proposed. During the preselection test, either one of the cross-coupled inverter nodes is loaded with a digitally controlled capacitance, which can tilt the PUF towards a “1” or a “0”. Any cell which maintains its value during this test is deemed stable. Each capacitor bank is shared between four PUF cells, such that the additional area required is only 20%. This test does not require precision analog voltages, as did previous tests, and can thus be implemented by the user during key enrollment. In a test-chip implementation in TSMC 65nm node, the preselection test identified and disqualified all the cells that were measured as unstable in 18 PUF arrays, of 800 bits each. An overall scheme for PUF stabilization is proposed, composed of two error-reductions steps, comprising Inner and Outer error control blocks. The outer error control is typically a BCH code, which guarantees a required key error rate. The inner error control can either be the proposed tilt test, a BCH code, or another error correction scheme. To maximize the ratio of reliable key bits to physical PUF cells, i.e., the overall PUF code rate, several solutions were analyzed. It is shown that in order to achieve a key error rate of 1E-9, the most efficient construction is a tilt test followed by BCH[184,128,15], with a PUF code rate of 0.49. In addition, the tilt test is more efficient in terms of power, area and execution time than the other inner error correction mechanisms. Therefore, this construction is not only efficient by its overall code rate, but also by its area and its power, and further, it enables a more lightweight BCH implementation for the outer code.

In this paper, a family of $[{q}^{2}-1, 4, {q}^{2}-{q}-2]$ cyclic codes over ${\mathbb F}_{{q}}$ meeting the Griesmer bound is presented. Their duals are $[{q}^{2}-1,{q}^{2}-5,4]$ almost MDS codes and are optimal with respect to the sphere-packing bound. The ${q}_{0}$ -ary subfield codes of this family of cyclic codes are also investigated, where ${q}_{0}$ is any prime power such that q is power of ${q}_{0}$ . Some of the subfield codes are optimal and some have the best known parameters. It is shown that the subfield codes are equivalent to a family of primitive BCH codes and thus the parameters of the BCH codes are solved. The duals of the subfield codes are also optimal with respect to the sphere-packing bound. A family of $[{q}^{2}, 4, {q}^{2}-{q}-1]$ linear codes over ${\mathbb F}_{{q}}$ meeting the Griesmer bound is presented. Their duals are $[{q}^{2},{q}^{2}-4,4]$ almost MDS codes and are optimal with respect to the sphere-packing bound. The ${q}_{0}$ -ary subfield codes of this family of linear codes are also investigated, where ${q}_{0}$ is any prime power such that q is power of ${q}_{0}$ . Five infinite families of 2-designs are also constructed with three families of linear codes of this paper.

This paper presents an advanced key-equation solver (KES) algorithm that can reduce the computing latency of BCH decoding for the high-speed storage class memory (SCM). Adopting the unfolding algorithm as a factor of two, compared to the conventional iterative KES scheme, the proposed work potentially halves the number of processing cycles for KES module, which is normally dominates the overall BCH decoding latency. In contrast that the straight-forward unfolding method increases the critical delay, we accelerate the major computing path that is activated at the most of SCM lifetime, preserving the critical delay of the proposed KES module as similar to that of the original one. When the minor cases are detected, the recovery processing is added at the end of the corresponding iteration. In order to reduce the additional energy consumption due to the unfolded architecture, we carefully deactivate the internal modules during the accelerated processing, which only necessitate for the recovery cycle. Implementation results show that the proposed KES architecture greatly reduces the decoding latency of arbitrary BCH decoder, leading to the high-speed and reliable emerging storages.

This paper concerns the problem of phase reference estimation with noise, introduced by the imperfect phase-locked loop (PLL) circuit, or the imperfect channel estimation, or both. Prior solutions for suppressing phase noise focus on improving the accuracy of phase reference estimation. The accuracy of phase reference estimation is not high enough due to the following two limitations. First, since the PLL circuit works in radio-frequency (RF), a PLL circuit with high accuracy leads to high cost and high complexity, which makes the deployment difficult. Second, as data rates increase and wireless channels become more complex, the receiver is more difficult to obtain an ideal channel estimation and the negative effect of phase noise becomes more apparent. In this paper, we propose a machine learning approach to mitigate the negative effect of phase noise by using clustering algorithms. The key intuition of our approach is that the clustering algorithm can adaptively trace the shifted constellation point due to the phase noise. Our approach is adaptive because it can adaptively find each received symbol belongs to its original constellation point if the phase noise is not too large, e.g. , no larger than $0.25 \pi $ . While the shifted distance is not too large, we can map the received symbols into the correct constellation point to mitigate the negative effect of phase noise. Instead of directly using conventional clustering algorithms into the proposed machine learning approach, we propose a new weighted ensemble clustering algorithm to further improve the performance of our approach. In comparison with prior approaches based on RF circuits, our approach has comparable reception performance but with low complexity and low cost. Our experimental results show that, for a QPSK system, our approach improves the demodulation performance and the decoding performance about 10 dB, 8 dB under BCH codes, and 3 dB under Turbo codes, respectively. Even the demodulation performance of our approach without channel coding is better than the decoding performance of the system with channel coding about 5 dB under BCH codes.

This paper proposes a generator polynomial model-based eye diagram estimation method for the error-correction codes (ECCs), which are the Bose–Chaudhuri–Hocquenghem (BCH) code and the Reed–Solomon (RS) code. The ECCs compensate for the channel loss at the bit level, so most of the systems include the ECC block. The BCH and RS codes are the generator polynomial-based ECCs; this paper proposes the generator polynomial model-based method. The model provides the accurate probability density function of the code words for the BCH and RS code. Thus, the proposed method is capable of achieving the signal integrity analysis for the system level. For verification, we design the BCH and RS encoders. The estimated eye diagrams are nearly the same as that of the transient simulation for the BCH and RS codes. Furthermore, the voltage bathtub curves are the same up to 10−8. For a smaller bit-error rate value, the proposed method only provides the bathtub curve. This paper successfully verifies the eye diagram estimation method for the BCH and RS codes.

Orthogonal frequency division multiplexing (OFDM) is a widely used modulation and multiplexing technology applied in many telecommunications standards due to its spectral efficiency and robustness against multipath fading. The multicarrier aspect of OFDM signal is characterized by high peak-to-average power ratio (PAPR), which renders the power amplifier (PA) inefficient and causes distortion in the transmitted signal. Several techniques to overcome and reduce PAPR such as signal distortion, signal scrambling, coding etc. are proposed and implemented on multipath fading channels. Coding methods does not affect system complexity as forward error correction is an inherent block in any digital communication system. The frequency diversity benefits of OFDM is not utilized well unless channel coding is used. Several codes like Hamming, Golay, BCH, RS, Reed Muller etc. have been investigated so far. Goppa codes were needed to be explored in OFDM systems. In this paper, its ability to reduce the peak power is studied for conventional OFDM signal. These codes are used in computer and telecommunication based applications owing to its useful properties required for cryptography. The PAPR reduction of Goppa coded OFDM (GOFDM) is found to be satisfactory for higher order constellation mapping of binary information. A look up table can also be created to select Goppa code words on the basis of a desired threshold of PAPR in dB. A mathematical analysis of the relationship of input data and its PAPR is also executed and certain conclusions are drawn as shown in the lemmas. But coding methods solely cannot achieve substantial PAPR reduction and therefore most of the literature on PAPR reduction methods have combined coding with other techniques. In this paper, G-OFDM is extended to a hybrid method of constant amplitude modulated (CAM)-G-OFDM to completely mitigate the PAPR problem. But it is achieved at the cost of transmitter and receiver complexity and performance parameters like bit error rate (BER), dependency on modulation index etc. which can be taken care of by making some amendments in the system design.

In this paper, we propose an image tampering localization algorithm using semi-fragile watermarking and Error-Locating codes in the DWT domain. By introducing different families of codes, we show the benefit in terms of image tampering localization and complexity of using control code error localization as an authentication function. Indeed, we first experimentally show that error localization block codes is as precise as using classical error correcting codes (Reed-Solomon and BCH codes) to locate image tampering. However, their corresponding decoding algorithms complexity is at least quadratic which make them impractical for some real time applications. To solve this problem, we introduce error-control codes called Error-Locating codes where error localization is reduced to a single syndrome computation performed with low number of binary operations (detailed later in the paper). We provide comparisons of image quality and tampering localization performances using error-detection, error-localization and error-correction approaches with different error control codes.

One of the most popular computer programs for designing interior engineering systems for buildings, including ventilation systems, is the MagiCAD program of the Finnish company MagiCAD Group. MagiCAD allows easily and quickly create three-dimensional models of ventilation systems, selecting area sections of air pipelines sections, to perform aerodynamic and acoustic calculations and balancing of air duct networks, making detailed specifications and etc. Despite the detailed documentation on the program, the MagiCAD mechanism remains hidden from the user. The method of pressure losses definition in MagiCAD is significantly different from the national standards, especially for definition of pressure losses of components. This difference should be taken into account when doing aerodynamic computations designing ventilation systems. The paper considers the mathematical dependencies used by the MagiCAD program for aerodynamic computations of air pipelines. The comparison of these dependencies with the used for national design practice is also provided in the paper. The comparison of computation results is made for specific values of friction pressure losses, pressure losses of components such as bends of round and rectangular sections of different angles, diffusers and confusers, tee fittings, etc. Despite the significant differences in the methods, the computed values of the pressure losses are quite close, the significant differences in the results of the calculations were observed only for confusers. Obviously, significant differences can be expected in the results of the calculation of the distribution nodes operating in the pressure (flow separation) mode, since its computation according to BCH 353-86 is similar to the confusers’ computation, but this issue needs further research.

Recently, symmetric block-wise concatenated-BCH (SBC-BCH) codes are proposed as strong error-correcting codes (ECCs) based on hard-decision channel outputs, which is especially suited for storages using NAND flash memories. Targeting energy-efficient NAND flash memory applications, this paper presents an energy-optimized decoder architecture which includes an iterative decoder for a SBC-BCH code as a main decoder and a low-complexity auxiliary decoder for a block-wise single parity-check (BSPC) code. The auxiliary decoder is opportunistically in action to break the dominant error bound associated with the SBC-BCH code, which allows one to lower the uncorrectable bit-error-rate (UBER) to 10−15 in an energy efficient way. This work presents several design-level optimizations for further enhancing the energy-efficiency of the iterative SBC-BCH decoder. More precisely, the new initialization scheme is proposed for ensuring the energy-efficient seamless decoding scenario. The syndrome tracking is applied to eliminate the previous syndrome calculation and the reordered Chien search further enhances the energy-efficiency as well as the decoding throughput. Targeting a 0.9-rate 4KB SBC-BCH code for commercialized storages using NAND flash memories, a prototype decoder consisting of both the iterative main and auxiliary decoders is designed in a 65-nm CMOS process. By applying the proposed optimizations, the prototype decoder achieves an energy-efficiency of 3.43 pJ/b while providing a decoding throughput of 13.2 Gb/s, which is superior to the previous state-of-the-art decoders for mobile storages.

As technology continues to scale down, NAND Flash memory has been increasingly relying on error-correction codes (ECCs) to ensure the overall data storage integrity. Although advanced ECCs such as low-density parity-check (LDPC) codes can provide significantly stronger error-correction capability over BCH codes being used in current practice, their decoding requires soft-decision log-likelihood ratio (LLR) information. This results in two critical issues. First, accurate calculation of LLR demands fine-grained memory-cell sensing, which nevertheless tends to incur implementation overhead and access latency penalty. Hence, it is critical to minimize the fine-grained memory sensing precision. Second, accurate calculation of LLR also demands the availability of a memory-cell threshold-voltage distribution model. As the major source for memory-cell threshold-voltage distribution distortion, cell-to-cell interference must be carefully incorporated into the model. However, these two critical issues have not been ever addressed in the open literature. This paper attempts to address these open issues. We derive mathematical formulations to approximately model the threshold-voltage distribution of memory cells in the presence of cell-to-cell interference, based on which the calculation of LLRs is mathematically formulated. This paper also proposes a nonuniform memory sensing strategy to reduce the memory sensing precision and, thus, sensing latency while still maintaining good error-correction performance. In addition, we investigate these design issues under the scenario when we can also sense interfering cells and hence explicitly estimate cell-to-cell interference strength. We carry out extensive computer simulations to demonstrate the effectiveness and involved tradeoffs, assuming the use of LDPC codes in 2-bits/cell NAND Flash memory.

BCH codes are an important class of cyclic codes which have applications in satellite communications, DVDs, disk drives, and two-dimensional bar codes. Although BCH codes have been widely studied, their parameters are known for only a few special classes. Recently, Ding et al. made some new progress in BCH codes. However, we still have very limited knowledge on the dimension of BCH codes, not to mention the weight distribution of BCH codes. In this paper, we generalize the results on BCH codes from several previous papers. 1) The dimension of narrow-sense BCH codes of length $((q^{m}-1)/{\lambda })$ with designed distance $2\leq \delta \leq (({q^{\lceil (m+1)/2 \rceil }-1})/(\lambda)+1)$ is settled, where $\lambda $ is any factor of $(q-1)$ . 2) The weight distributions of two classes of narrow-sense BCH codes of length $(({q^{m}-1})/2)$ with designed distance $\delta =(({(q-1)q^{m-1}-q^{\lfloor (m-1)/2\rfloor }-1})/2)$ and $\delta =(({(q-1)q^{m-1}-q^{\lfloor (m+1)/2\rfloor }-1})/2)$ are determined. 3) The weight distribution of a class of BCH codes of length $((q^{m}-1)/({q-1}))$ is determined. In particular, a subclass of this class of BCH codes is optimal with respect to the Griesmer bound. Some optimal linear codes obtained from this class of BCH codes are characterized.

Bose–Chaudhuri–Hocquenghem (BCH) and low-density-parity-check (LDPC) are two popular error correcting codes for non-volatile memories. However, the BCH has limited error correction ability, while the LDPC requires multiple sensing operations per read. In this paper, an advanced bit flip (ABF) scheme is proposed to obtain high-correctable raw bit error rate (BER), fast decoding, and one sensing per read, simultaneously. During write, first, the ABF uses data mapping to correct major program errors. Then, the BCH is used to correct the remaining errors. The performance of concatenated ABF + BCH is calculated by using 108 writes data from a nano-random access memory array. On 32 768 user data bits, ABF + BCH reduces 54% parity size and 17% decoding latency compared with only using BCH. Furthermore, ABF + BCH performances are calculated and analyzed statistically on a hypothetical memory array with binominal error distribution. By using fixed 512 bytes parity, ABF + BCH obtains 0.93% correctable raw BER when set + retention BER is 0.1%. Moreover, ABF + BCH shows less decoding latency than only using BCH.

Due to its large peak to average power ratio (PAPR) and high out of band emission (OOBE), OFDM doesn't meet the requirements of 5G services. Additionally, it supports only one type of waveform parameters in entire bandwidth. In contrast, f-OFDM is dividing the system's bandwidth into a number of subbands to support several waveform parameters based on various service scenarios. So, Filtered-OFDM (f-OFDM) is considered as a modern enabler of the flexible waveform to overcome the OFDM drawbacks while remaining its advantages as well as, to encounter the new challenges that faced 5G. Nonetheless, there is a trade-off among OOBE, PAPR and SNR performance. Meanwhile, channel coding technology is one of the most important issue in physical layer which is playing an essential role in order to achieve the reliability and latency. So, BCH code has been suggested in this paper for f-OFDM system to achieve the reliability of transmission information and thus improving BER performance over multipath fading channel. Whilst, BCH-LTE system is introduced as a baseline in this paper that using for comparison purpose with proposed system. Simulation results showed that the proposed BCH-f-OFDM system was significantly better than BCH-LTE system in terms of decreasing OOBE and achieving improving in BER performance. Although, PAPR levels was stilling high in proposed system due to the trade-off among OOBE, PAPR and SNR performance. However, the proposed system is considered a promising candidate to meet the requirements of 5G services because of its ability to solve two important issues in between three trade-offs'.

Cyclic codes are an interesting type of linear codes and have wide applications in communication and storage systems due to their efficient encoding and decoding algorithms. It was proved that asymptotically good Hermitian LCD codes exist. The objective of this paper is to construct some cyclic Hermitian LCD codes over finite fields and analyse their parameters. The dimensions of these codes are settled and the lower bounds on their minimum distances are presented. Most Hermitian LCD codes presented in this paper are not BCH codes.

Cyclic codes are widely employed in communication systems, storage devices, and consumer electronics, as they have efficient encoding and decoding algorithms. BCH codes, as a special subclass of cyclic codes, are in most cases among the best cyclic codes. A subclass of good BCH codes are the narrow-sense BCH codes over $ {\mathrm {GF}}(q)$ with length $n=(q^{m}-1)/(q-1)$ . Little is known about this class of BCH codes when $q>2$ . The objective of this paper is to study some of the codes within this class. In particular, the dimension, the minimum distance, and the weight distribution of some ternary BCH codes with length $n=(3^{m}-1)/2$ are determined in this paper. A class of ternary BCH codes meeting the Griesmer bound is identified. An application of some of the BCH codes in secret sharing is also investigated.

Several algorithms have been proposed to avoid the error floor region, such as the concatenation codes that requires high computational demands in addition to high complexity. This paper proposes a technique based on using cascaded BCH and convolutional codes that leads to better error correction performance. Moreover, an adaptive method based on sensing the channel's noise to determine the number of the parity bits that will be added to the used BCH that reduces the consumed bandwidth and the transmitted parity bits is presented. A further enhancement is fulfilled by using parallel processing branches, resulting in reducing the consumed time and speed up the performance. The results show that the proposed code presents a better performance. A high reduction in the number of cycles that will be used in the encoding and decoding compared with the classical method and finally a flexible parity bits method based on the signal-to-noise ratio of the channel that reduced the parity bits which leads to reduce the consumed bandwidth. The MATLAB simulation and the field programmable gate array (FPGA) implementation will be provided in this paper to validate the proposed concept.