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Intelligent reflecting surface (IRS) has been regarded as a promising and revolutionary technology for future wireless communication systems owing to its capability of tailoring signal propagation environment in an energy/spectrum/ hardware-efficient manner. However, most existing studies on IRS optimizations are based on a simple and ideal reflection model that is impractical in hardware implementation, which thus leads to severe performance loss in realistic wideband/multi-band systems. To deal with this problem, in this paper we first propose a more practical and more tractable IRS reflection model that describes the difference of reflection responses for signals at different frequencies. Then, we investigate the joint transmit beamforming and IRS reflection beamforming design for an IRS-assisted multi-cell multi-band system. Both power minimization and sum-rate maximization problems are solved by exploiting popular second-order cone programming (SOCP), Riemannian manifold, minimization-majorization (MM), weighted minimum mean square error (WMMSE), and block coordinate descent (BCD) methods. Simulation results illustrate the significant performance improvement of our proposed joint transmit beamforming and reflection design algorithms based on the practical reflection model in terms of power saving and rate enhancement. [ABSTRACT FROM AUTHOR]

The difficulty in acquiring fault label data is a major obstacle to the application of data-driven fault isolation in DC microgrids. To remove this barrier, this paper introduces an approach of generating synthetic data with the line currents measured during normal operation as the substitute for fault label data in training an ensemble model, which is aimed to isolate line short-circuit faults in DC microgrids. Based on a high-frequency model of DC microgrids, we prove that the line currents during the closing of unloaded DC lines have similar high-frequency features as those during a line short-circuit fault. On this basis, the synthetic data are obtained through performing discrete wavelet packet transform on the line currents measured during the circuit breaker operation. With normal operating data and synthetic data, an ensemble model is trained as the fault classifier. In the verification tests of different fault scenarios in a three-terminal DC microgrid model, the detection rates of the proposed ensemble model are over 90% while the false positive rates are below 0.5%. These results prove the effectiveness of using synthetic data as the fault labels in the ensemble learning-based fault isolation in DC microgrids. [ABSTRACT FROM AUTHOR]

This paper introduces a novel frequency domain technique to globally evaluate the accuracy of electro-magnetic transient simulations. It is shown that simulation accuracy at low frequencies can sometimes be poorer than at high frequency. A modified approach which quantifies accuracy from a driving point as a function of frequency is also introduced that uses the Bilinear Transformation and Norton equivalents, to produce a “simulation accuracy spectrum”. This approach can be applied to large systems without explicitly forming state space equations. It also permits the accuracy analysis of networks with distributed components such as frequency dependent transmission lines. Two examples are used to verify the proposed technique, a small network with a frequency dependent transmission line modeled by the universal line model; and the IEEE 39 bus system connected with an LCC-HVdc system. [ABSTRACT FROM AUTHOR]

The high temperature superconducting (HTS) cable has shown promising prospects in megacities for the advantages of high transmission power density and low loss. However, when HTS cable is working on grid, various kinds of faults may cause irreversible damage, resulting in the failure of reclosing. In this paper, the resistive superconducting fault current limiter (R-SFCL) is introduced into the power system to cooperate with the HTS cable, so as to reduce the potential damage caused by fault current. Firstly, the equivalent circuit models are established, and then transient response of HTS cables under fault condition is analyzed, the recovery time of HTS tapes are used to define the design of R-SFCL. Finally, the operating reliability of HTS cable has been evaluated and measures about adaptive reclosing times were proposed under different fault currents. [ABSTRACT FROM AUTHOR]

This paper presents a novel leakage model for transformers that includes losses. This new model is physically based (topological) and it is possible to connect it to a topological core model without using any fictitious windings. The methods to calculate its parameters from standard test data and from design data are detailed within the paper. The results show that the new coupled leakage model with losses is able to match exactly the test report, when using standard test data. Preliminary investigations show that the results are very close to measurements, when using design data. [ABSTRACT FROM AUTHOR]

This paper exhibits systematic results for lateral light emitting diodes (LEDs) with various conditions. The simulation results and circuit model are both included to describe the current spreading effect at the same time. A fully 2-D model that solves Poisson and drift-diffusion equations to investigate the current flow and radiative recombination distribution specifies the uniformity of the carrier distribution, which is combined with the Monte Carlo ray tracing technique to calculate the light extraction efficiency (LEE). This paper focuses on the modulation of the transparent conducting layer. In addition, this paper will discuss bottom emission LEDs addressing the current spreading effect and LEE compared with top emission LEDs. We also examine the droop effect to verify our discussion. A thorough analysis provides deep insights for achieving high efficiency lateral LEDs. [ABSTRACT FROM PUBLISHER]

In this paper, we propose a circuit yield prediction method to improve the efficiency of circuit yield prediction. Both traditional Monte Carlo simulation and the current popular machine learning for yield prediction require a large number of circuit simulation results, which increases production costs. This method finds the data boundary points through high-dimensional kernel density estimation, and performs simulation calculations on these boundary values instead of the overall simulation. Experiments show that, compared with machine learning and Monte Carlo methods, the proposed algorithm can efficiently predict the yield of circuits. [ABSTRACT FROM AUTHOR]

Harmonic resonances in DFIG-based wind parks can be investigated by using extensive electromagnetic transient simulations, which is a time-consuming process. This paper shows that not all wind parks need such a detailed analysis. In response, the paper proposes a practical, easy-to-use method for a first-cut assessment of the risk of harmonic resonance of DFIG-based wind parks. First, simple equations are obtained to estimate resonance frequency and amplification in terms of wind park parameters readily available in practice. These equations reveal combinations of wind park parameters that cause problematic resonance. Such combinations are used to trace regions of concern in a chart. If the wind park is out of all regions of concern of the chart, one can directly declare this park is resonance-free, without running any simulation study. In addition to the analytic (model-based) method, a measurement-based method is provided for obtaining the resonance chart without running any simulation. Examples show how the proposed approach can be applied to facilitate resonance assessment during the wind park planning and operation. [ABSTRACT FROM AUTHOR]

An increasingly important trend in the design of industry-strength embedded systems is the integration of multiple services with varying criticality levels into a common computing platform. Such systems are characterized as mixed-criticality multiservice systems (MCMSs). An MCMS has to survive in rigorous environments posed by industry-level requirements. Such survival, however, is becoming continuously more challenging due to the growing system complexity and integrating more and more services. While existing works typically target reliability-driven design optimization to improve the system robustness rather than deal with the surviving problem of the system in extreme physical environments, this paper addresses the problem by enabling the service capability transitions of an MCMS to adapt to the environments. This paper proposes a service capability model to capture the importance of functional modules for the criticality of different services. A model-based service-capability transition mechanism is designed to automatically identify the maximum allowed service capability under a given physical environment. A case study of the proposed techniques was performed on an industrial Ethernet switch which is a typical MCMS, to validate the capability of adaptation to high and low temperatures. The experimental results demonstrate the significant potential of our approach to improve system survivability under extreme physical environments. [ABSTRACT FROM AUTHOR]

This paper addresses theoretical aspects of arithmetic circuit verification based on algebraic rewriting. Its goal is to advance the understanding of algebraic techniques for arithmetic circuit verification in the context of symbolic computer algebra. The paper offers a new insight into the arithmetic circuit verification problem, by viewing the computation performed by the circuit as the flow of digital data. In the proposed bit-flow model, the circuit is modeled as a network of logic components satisfying a bit-flow conservation law. We prove that the value of the flow of data in the circuit is invariant throughout the circuit and use this to prove soundness and completeness of the rewriting technique, independently from the computer algebra arguments. The efficiency of the method is illustrated with impressive results for large integer multipliers. The verification system and benchmarks are offered in an open source software environment. [ABSTRACT FROM AUTHOR]

In this paper, a new look-up table (LUT) method is proposed to reduce the simulation time and the run time memory requirement for large logic and mixed signal simulations. In the proposed method, for the first time, circuit with multiple devices is replaced by one LUT model, called circuit LUT. The replacement results in significant reduction of the run time memory requirement. The replacement also reduces the number of interpolation steps to be performed at every Newton–Raphson iteration during the simulation that results in significant reduction of simulation time. With the proposed method, the simulation speed is improved by two times over the conventional LUT models developed for devices. In addition, 25% reduction in the run time memory requirement is also achieved by the proposed method. [ABSTRACT FROM AUTHOR]

Brushless doubly fed induction machine (BDFIM) which is able to operate in both induction mode and synchronous mode, has received increasing attention of researchers, in the last three decades. It could be considered as an emerging competitor for older structures, due to the substantial features such as brushless structure and requiring a fractionally rated frequency converter. The iron loss which constitutes a significant portion of total power losses is higher in BDFIM in contrast with standard induction machine. Even though it is essential to consider the iron loss effect on dynamic behavior of BDFIM, there is still no comprehensive study in the literature. The aim of this paper is to propose a dynamic model of BFIM in general reference frame in which the iron loss is taken into account. This model which is credible for all BDFIM operation modes including synchronous one, facilitates the performance analysis of BDFIM and implementation of the various control techniques. The supplementary simulations and experiments confirm that the proposed model is an appropriate candidate for BDFIM drives. Because of the complex structure of BDFIM, determination of the iron loss isn't straightforward. In this paper, a practical approach is introduced to calculate the iron loss of BDFIM in terms of frequency variations. The experimental data derived from a D132s prototype BDFIM is then compared with the calculated data from the finite element analysis (FEA). [ABSTRACT FROM AUTHOR]

Energy management is a critical challenge in multicore processors due to continuous technology scaling. Previous methods have mostly focused on the energy minimization of the processor cores. However, energy overhead of the off-chip voltage regulator (VR) has recently shown to be a nontrivial part of the total energy consumption and has been previously overlooked. In this paper, we propose an overall energy optimization method for the system that minimizes both per-core energy consumption and VR energy consumption using dynamic voltage frequency scaling and VR phase scaling by solving a comprehensive convex model. In order to improve the accuracy of the task latency model, a new task model considering both computation and memory access of the task is also developed. Furthermore, for better scalability and lower online overhead, we decompose our proposed convex method into two stages: 1) an offline stage and 2) an online stage. During the offline stage, we explore the convex model by assuming different numbers of active phases of the VR, various workload pressures and workload characteristics to collect the optimal frequency assignments under different scenarios. During the online stage, the specific frequency assignment for cores and optimal active phase number of the VR are selected and applied based on the actual workload pressure and its characteristics running on the cores. Experiments on real benchmarks show that when compared with the state-of-the-art approaches, which are oblivious to VR overheads and exploit slack time to achieve energy minimization, our method can achieve a significant energy saving of up to 22.4% with negligible online overhead. [ABSTRACT FROM AUTHOR]

In recent years there has been a growing interest in electronic design automation methodologies for the optimization-based design of radio frequency (RF) circuits and systems. While for simple circuits several successful methodologies have been proposed, these very same methodologies exhibit significant deficiencies when the complexity of the circuit is increased. The majority of the published methodologies that can tackle RF systems are either based on high-level system specification tools or use models to estimate the system performances. Hence, such approaches do not usually provide the desired accuracy for RF systems. In this paper, a methodology based on hierarchical multilevel bottom-up design approaches is presented, where multiobjective optimization algorithms are used to design an entire RF system from the passive component level up to the system level. Furthermore, each level of the hierarchy is simulated with the highest accuracy possible: electromagnetic simulation accuracy at device-level and electrical simulations at circuit/system-level. [ABSTRACT FROM AUTHOR]

In this paper, a dynamic model based on the sampled-data method is presented for a wireless power transfer (WPT) system. The orders of the derived model are equal to the orders of a system. The modeling is different from the existing dynamic modeling for WPT systems, which almost double the model's order. Furthermore, the systematic analysis process is suitable for any WPT topologies and without the higher harmonics neglected and low-frequency approximation. Meanwhile, the state variables are allowed to vary up to twice the switching frequency, since the half-period symmetry property is exploited. In this paper, the series–series (SS) compensated WPT system is chosen as an example and the large-signal model and the steady-state operation point are determined. The small-signal responses perturbed by the phase-shift angle, switching frequency, and input voltage are obtained. The derived model is more adequate with simulation and experimental validation. [ABSTRACT FROM AUTHOR]

An electrical transient model (ETM) of insulated-gate bipolar transistor (IGBT)-diode switching cell is developed by coupling a temperature-dependent IGBT model with power loss model. The nonlinear behavior of IGBT and the reverse recovery characteristic of the diode are considered in this model to simulate the transient switching waveforms. Based on the transient waveforms of ETM under various operating conditions, the power loss estimation method (PLEM) for IGBT is developed. In addition to traditional modeling techniques that only uses ideal switch, this paper uses the model to replicate the power loss behaviors of semiconductor devices in circuit simulation by looking up tables. The proposed ETM is simulated in PSCAD/EMTDC with nanosecond time step, whereas the overall system application can be simulated with conventional time step in range of microsecond. By this way, the model can promise reasonable accuracy as well as an acceptable fast solving speed. The proposed ETM and PLEM have been implemented in PSCAD/EMTDC simulator and validated by experimental results using a double pulse test bench and boost converter test platform. [ABSTRACT FROM AUTHOR]

A novel method for semantic action recognition through learning a pose lexicon is presented in this paper. A pose lexicon comprises a set of semantic poses, a set of visual poses, and a probabilistic mapping between the visual and semantic poses. This paper assumes that both the visual poses and mapping are hidden and proposes a method to simultaneously learn a visual pose model that estimates the likelihood of an observed video frame being generated from hidden visual poses, and a pose lexicon model establishes the probabilistic mapping between the hidden visual poses and the semantic poses parsed from textual instructions. Specifically, the proposed method consists of two-level hidden Markov models. One level represents the alignment between the visual poses and semantic poses. The other level represents a visual pose sequence, and each visual pose is modeled as a Gaussian mixture. An expectation-maximization algorithm is developed to train a pose lexicon. With the learned lexicon, action classification is formulated as a problem of finding the maximum posterior probability of a given sequence of video frames that follows a given sequence of semantic poses, constrained by the most likely visual pose and the alignment sequences. The proposed method was evaluated on MSRC-12, WorkoutSU-10, WorkoutUOW-18, Combined-15, Combined-17, and Combined-50 action datasets using cross-subject, cross-dataset, zero-shot, and seen/unseen protocols. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel post-bond through-silicon via (TSV) test method for post-bond TSV manufacture test. The proposed method can measure the RGC parameters of TSVs using switched-capacitor circuits and calibration method and detect TSV leakage fault, open fault, high-resistance fault, and delay fault based on the measured RGC parameters. The test process has a high resolution and is robust. The fault-detection effectiveness is evaluated via HSPICE simulations. The results of the TSV capacitance measurement have a relative error within 1%, the TSV resistance measurement results have a relative error within 5%, and the TSV conductance measurement results have a relative error within 8.5%. We also perform an Monte Carlo simulation to prove that even under process variation, the proposed method can obtain a TSV capacitance within an absolute error of ±3 fF, obtain a TSV resistance with a relative error of no more than 18.4%, and obtain a TSV conductance of less than 100 ${\mu \Omega }^{{-1}}$ with a relative error of no more than 13%. [ABSTRACT FROM AUTHOR]

In this paper, the modeling of storage elements and a unified theory liberated of the I–V characteristics of a specific technology is developed. First, the definition of an ideal storage element with limited energy capacity is presented, then the semiideal storage properties are discussed. The addition of power conservative two-port network denoted POPI (Pout = Pin) is added in order to define a flexible storage element in terms of characteristics. The paper demonstrates the theory by examples of storage elements integrated in power electronics systems. The ideas and methodology presented in this work can be applied to power electronics applications as well as power systems, smart grids, and microgrids, where storage is an important factor. [ABSTRACT FROM AUTHOR]

Good knowledge of internal circuit states are crucial for efficient post-silicon debug. Due to the area, power, routing, and bandwidth limitations trace buffer-based design for debug hardware provides execution traces of a limited number of state elements which are then usually expanded through signal restoration. In this paper, we propose to record combinational execution traces and show that combined with signal restoration better knowledge of internal circuit states are obtained. Our experiment with benchmark circuits show that restoration quality in terms of state restoration ratio is improved up to 48% on average. Extending the solution space by, including combinational gates drastically increases signal selection runtime. Using hybrid signal selection methods, we also provide good tradeoff between restoration quality and runtime. By dynamically updating some metrics in state-of-the-art hybrid selection method, we achieve 65% reduction in runtime with only 2% penalty in solution quality. Using the proposed signal selection algorithms, designers can better explore the circuit states and achieve more efficient post-silicon debug. [ABSTRACT FROM AUTHOR]

This paper presents fuzzy ${c}$ -means-based yield estimation (FUZYE), a methodology that reduces the time impact caused by Monte Carlo (MC) simulations in the context of analog integrated circuits (ICs) yield estimation, enabling it for yield optimization with population-based algorithms, e.g., the genetic algorithm (GA). MC analysis is the most general and reliable technique for yield estimation, yet the considerable amount of time it requires has discouraged its adoption in population-based optimization tools. The proposed methodology reduces the total number of MC simulations that are required, since, at each GA generation, the population is clustered using a fuzzy ${c}$ -means (FCMs) technique, and, only the representative individual (RI) from each cluster is subject to MC simulations. This paper shows that the yield for the rest of the population can be estimated based on the membership degree of FCM and RIs yield values alone. This new method was applied on two real circuit-sizing optimization problems and the obtained results were compared to the exhaustive approach, where all individuals of the population are subject to MC analysis. The FCM approach presents a reduction of 89% in the total number of MC simulations, when compared to the exhaustive MC analysis over the full population. Moreover, a ${k}$ -means-based clustering algorithm was also tested and compared with the proposed FUZYE, with the latest showing an improvement up to 13% in yield estimation accuracy. [ABSTRACT FROM AUTHOR]

In deep submicron nodes, the final design patterning quality depends profoundly on the optical proximity correction (OPC) quality. The required pattern fidelity and CD uniformity can never be achieved without good OPC. However, OPC runtime-resource factor has been exponentially increasing every technology node reaching alarming levels, where the OPC cost in terms of resources and turn-around-time is becoming very expensive. In this paper, we present a novel approach for speeding up the OPC convergence process using our model-based initial bias methodology. Our proposed methodology is based on building generic compact bias-models that can predict the final OPC shapes with a good accuracy using the optical simulation parameters. As a result, the OPC initial condition is much closer to the final solution and more than half of the OPC iterations can be saved as a result. In this paper, we present the details of our methodology and our compact initial-bias model we are proposing. We also present our testing results on a 10 nm metal level, where almost 50% of the OPC iterations could be saved when we apply our methodology. [ABSTRACT FROM AUTHOR]

In this paper, we propose a single probability density function for the distributions of the delay in the presence of the process variation for different regions of operation. The delay variation model is inspired by considering the analytical current models for each operating region. Based on these models, we suggest using the log-skew-normal distribution for modeling the delay variation for a wide range of supply voltages from the subthreshold to above-threshold regions. To assess the accuracy of the proposed delay distribution, the mean, standard deviation, skewness, 99th percentile, and yield of the proposed distribution are compared with those of the normal and log-normal distributions using the Monte Carlo (MC) simulations for different circuits in both bulk and FinFET technologies. The results show a higher accuracy for the proposed distribution in all regions of operation. Also, the proposed model enables us to obtain the 3 \sigma yield of the distribution using up to 3.4 times less MC simulation time. [ABSTRACT FROM PUBLISHER]

Efficient performance modeling of today’s analog and mixed-signal circuits is an important yet challenging task, due to the high-dimensional variation space and expensive circuit simulation. In this paper, we propose a novel performance modeling algorithm that is referred to as Bayesian model fusion (BMF) to address this challenge. The key idea of BMF is to borrow the information collected from an early stage (e.g., schematic level) to facilitate efficient performance modeling at a late stage (e.g., post layout). Such a goal is achieved by statistically modeling the performance correlation between early and late stages through Bayesian inference. Furthermore, to make the proposed BMF method of practical utility, four implementation issues, including: 1) prior mapping; 2) missing prior knowledge; 3) fast solver; and 4) prior and hyper-parameter selection, are carefully considered in this paper. Two circuit examples designed in a commercial 32 nm CMOS silicon on insulator process demonstrate that the proposed BMF method achieves up to $9\times $ runtime speed-up over the traditional modeling technique without surrendering any accuracy. [ABSTRACT FROM AUTHOR]

This paper presents a circuit performance benchmarking using the large-signal model of graphene FET reported in Part I of this two-part paper. To test the model, it has been implemented in a circuit simulator. In particular, we have simulated a high-frequency performance amplifier, together with other circuits that take the advantage of the ambipolarity of graphene, such as a frequency doubler, an RF subharmonic mixer, and a multiplier phase detector. A variety of simulations comprising dc, transient dynamics, Bode diagram, S parameters, and power spectrum have been compared with experimental data to assess the validity of the model. [ABSTRACT FROM PUBLISHER]

This paper presents a methodology to construct an equivalent circuit model of a packaged integrated circuit mounted on a field-induced charged device model electrostatic discharge tester. Circuit simulation is used to obtain the full-component current and voltage distributions. This paper focuses on predicting overvoltage stress at power domain crossing circuits. [ABSTRACT FROM PUBLISHER]

This paper presents the magnetic and electrical equivalent circuits of a hysteresis interior permanent magnet (IPM) motor. A hysteresis IPM motor is a solid rotor hybrid synchronous motor combining hysteresis phenomena and permanent excitation in the rotor. When installed in thousands of feet under the sea to drive an electric submersible pump (ESP), it can self-start the ESP without the need of any position sensors, and can improve the efficiency, the performance, and the reliability of the ESP. In this paper, equivalent circuit models are used to predict the transient run-up responses of a 2.5 kW prototype hysteresis IPM motor. Analysis results are compared with 2-D finite-element analysis (FEA) results as well as experimental results. There exists a reasonably close agreement between analytical, FEA, and experimental results, which validates the accuracy of the equivalent circuit models of a hysteresis IPM motor. [ABSTRACT FROM PUBLISHER]

Circuit-level models are developed to determine the upper bound on the performance of a 3-D IC link with through silicon vias (TSVs). It is shown that the performance of a 3-D link is limited not only by the on-chip interconnect RC, driver resistance, and TSV capacitance, but also by the current carrying capacity of the on-chip wires connecting the TSV to the input/output (I/O) driver. The models developed in this paper are used to optimize the I/O driver size, the number of on-chip wires connecting the TSV to the driver, and the data-rate to maximize the aggregate bandwidth per unit energy. Furthermore, in order to maximize the aggregate bandwidth of a 3-D link, it is shown that splitting the TSV array into smaller subarrays and placing the I/O drivers closer to the TSVs is better compared with having large TSV arrays. [ABSTRACT FROM AUTHOR]

Transient behavior in grounding systems related to electric arc furnaces (EAF) might be studied using an approach to Kron’s circuit model to solve Maxwell’s differential equations in electromagnetic field theory. This paper presents a circuit model designed using Kron’s approach implemented in alternative transient program (ATP). The model is suitable to describe accurately the behavior of real complex grounding systems dealing with continuous operation of an EAF. Some ideas about the behavior of the power quality are evaluated by simulation of the grounding system in ATP. [ABSTRACT FROM AUTHOR]

Medical imaging systems (MIS) constitute an important emergent subdiscipline of engineering studies. In the context of electrical and electronics engineering (EEE) education, MIS courses cover physics, instrumentation, data acquisition, image formation, modeling, and quality assessment of various modalities. Many well-structured MIS courses are available for EEE curricula, providing introduction to all modern diagnostic imaging systems. However, in these courses the laboratory component is limited to image formation and analysis. This paper proposes a wide range of experiments that incorporate various disciplines of EEE education into MIS courses. These experiments are designed to integrate knowledge that students have acquired previously from key EEE courses (such as circuit theory, differential equations, wave theory, energy conversion, control theory, and signal processing) into their new MIS knowledge. The proposed laboratory was adapted to a senior-year MIS class in the EEE Department of Dokuz Eylül University, Turkey. This paper presents the application of these new laboratory experiments, along with the assessment results. [ABSTRACT FROM PUBLISHER]

This paper presents a simple modulation index-dependent Thévenin equivalent circuit model of the voltage-source converters (VSCs) and the associated anti-parallel diode rectifier. The model derivation uses orthogonal transformation and a transformer analogy to transfer impedances to the dc side of the converter. The paper proposes a switched equivalent representation of a three-phase diode rectifier formed due to the antiparallel diodes when VSC switching is inhibited. The proposed model is implemented in Alternate Transients Program–Electromagnetic Transients Program and simulation results are compared with the switched model. The proposed model is shown to under predict the fault currents for pole-ground (PG) faults and to provide a nearly exact match for pole-pole faults. The rectifier equivalent provides increased accuracy in the transient region with the inclusion of the source inductance. A multiterminal dc (MTDC) system model is used to study effects of aggregation which gives increased accuracy of the equivalent circuit. It is shown that the MTDC system simulation with the proposed Thévenin equivalent is about 3 times faster than full-switched circuit simulation for a time step of 5 \mus. The MTDC system simulation with the Thévenin equivalent circuit is still accurate and 126 times faster when the time step is increased to 750 \mus. [ABSTRACT FROM AUTHOR]

This paper presents a practical robust controller that solves the problem of accurate motion control of ultrasonic motors (USMs) over prolonged durations, where temperature increases pose a significant challenge. This paper focuses on USMs with driver circuits that have a single user-controllable input. Prior to developing the robust controller, a nonlinear model of the system was identified by experimentally measuring the temporal relationship between motor speed and temperature to the applied input control signal. A linear approximation of this model was used to design two robust inverse dynamic controllers: one used temperature feedback and the other did not. Both control methods were implemented on a custom designed embedded control system and achieved highly consistent and accurate performance while under load over a range of working frequencies. Step-response experiments (1 rad) demonstrated a rise time of 0.1 s without any overshoot or steady-state error. A normalized RMSE below 3% with a delay of 25 ms was achieved for reference inputs with frequencies up to 1 Hz. This performance was maintained during prolonged continuous dynamic operation of several minutes, despite the great variation in the motor’s dynamics due to the temperature effects (over a range of 25 °C–45 °C) and modeling uncertainties. [ABSTRACT FROM AUTHOR]

This paper presents the wideband modeling and analysis of differential through-silicon vias (D-TSVs) in 3-D ICs. An equivalent-circuit model of the ground–signal–signal–ground-type D-TSVs is given and validated against a commercial full-wave electromagnetic simulation tool. The common- and differential-mode impedances are extracted using the partial-element equivalent-circuit method, while the admittances are calculated analytically, with the MOS effects considered and treated appropriately. The circuit model can also be used for studying the differential annular TSVs (ATSVs). It is shown that the ATSVs are more suitable for transmitting differential signals in comparison with the cylindrical TSVs. Based on the equivalent-circuit model, the characteristic impedances and the forward transmission coefficients of the D-TSVs made of Cu and carbon nanotubes are characterized and compared under different settings of frequencies and temperatures. [ABSTRACT FROM PUBLISHER]

Bidirectional inductive power transfer (BIPT) systems enable power transfer between stationary electricity sources and movable consumers in each direction through electromagnetic coupling. Due to its complexity, a mathematical model is required to design and to control these systems. This paper presents the mathematical analysis and the frequency-domain analysis for two different compensated (series–series and parallel–parallel) BIPT systems. This paper contains the modeling procedure of the BIPT system’s coils in the frequency domain. The prediction of its equivalent circuit values, magnetic stray field values, and coil positioning tolerance are determined as well using the JMAG field simulation software. Furthermore, the transmission characteristics and the efficiency of the two compensation topologies are discussed. [ABSTRACT FROM AUTHOR]

This paper presents a novel technique for suppressing cable noise currents, the quadruplet-resonator-based ferrite-free choke (QR-based FFC), to eliminate the gigahertz (GHz) electromagnetic interference caused by noise currents flowing on the cable shielding. This problem is difficult to handle with conventional ferrite materials since their permeabilities dramatically degrade when the operating frequency goes up to several GHz. In this paper, with the aid of QR surrounding on the cable shielding, the FFC forms bandstop responses against the noise currents. The corresponding equivalent lumped circuit model is proposed and investigated. Furthermore, the synthesis procedure is established using microwave filter theory. The QR-based FFC can achieve a high-level current suppression at the desired frequency band. This technology is experimentally verified: a given design example is demonstrated at the operating center frequency of 2.57 GHz. The frequency range of 3-dB current suppression is measured from 2.47 to 2.75 GHz (FBW = 10.8%), where the highest suppression level is up to 36 dB. The FFC-added cable also demonstrates a good result in the reduction of far-field radiation, where the reduction level of radiation peak gain is measured as 7 dB compared with that of a bare cable. [ABSTRACT FROM AUTHOR]

This paper proposes a detailed equivalent model for electromagnetic transient simulation of a modular multilevel converter with embedded battery energy storage in its submodules. The model offers an accuracy identical to that of a detailed switching model (DSM), while it markedly reduces the computational complexity of simulations. This is achieved by modeling each multivalve as a Thevenin equivalent considering the full dynamics of each constituent submodule, which results in a significant reduction in the number of switchable nodes in the converter model and hence the dimensions of the system's admittance matrix. The paper presents the mathematical development of the model and validates it against detailed switching models through several case studies. Experimental results from a scaled-down laboratory setup are also presented for further verification. [ABSTRACT FROM AUTHOR]

This paper proposes a new equivalent magnetic network (EMN) model for vehicular dual-permanent-magnet vernier (DPMV) machines by applying a generalized modeling method. First, the magnetic circuit method and the meshing method are combined together to improve the modeling efficiency of the DPMV machine. The magnetic circuit method is used to generate conventional lumped parameter permeances to shorten time consumption, whereas the mesh method is utilized in disordered magnetic fields to obtain high precision. Second, a meshing solution for oblique region is proposed to enhance modeling flexibility. Moreover, the flux distributions in meshes are represented without magnetic field pre-delineation, which enables its utilization as a self-adaptive reluctance network model in design optimization. Finally, the proposed EMN model is used to predict the performance of the DPMV machine, considering leakage magnetic flux, local iron saturation, and magnetic field modulation effect simultaneously. Meanwhile, the effectiveness of the proposed EMN model is verified by comparison with finite-element analysis and experimental tests. [ABSTRACT FROM AUTHOR]

One of the more intriguing applications of wireless power transfer is power delivery for low-power Internet of Things (IoT) devices. By utilizing RF near-field coupling (NFC), an improved combination of small receiver coil area and system efficiency can be achieved, as is ideal for wireless charging for low-power IoT platforms. However, utilizing high efficiency RF NFC comes with a cost—various electromagnetic effects can lead to detuning of the resonant frequency if not properly modeled. In addition, integrating power regulation with high frequency ac–dc conversion can create large ripple voltage supply to a power distribution unit (PDU). This paper investigates the system level issues that arise in efficient, regulated RF NFC systems for milliwatt-scale output power. A method for modeling the various electromagnetic, frequency detuning effects is presented, as well as a selection process for the circuit component values in the design. Furthermore, a reverse power distribution network is designed to integrate the rectifier with a PDU, introducing a target impedance and phase considerations for an RF rectifier. The modeling and integration solutions are experimentally verified through two different RF NFC systems. The systems have measured peak efficiency of 68.4% at 3.3 V output and 58.6% for 1 V output with less than 100 mm $^2$ receiver coil area, demonstrating a unique combination of small coil area and high efficiency compared to other NFC systems to better support low-power IoT devices. [ABSTRACT FROM AUTHOR]

Complex networks have now become integral parts of modern information infrastructures. This paper proposes a user-centric method for detecting anomalies in heterogeneous information networks, in which nodes and/or edges might be from different types. In the proposed anomaly detection method, users interact directly with the system and anomalous entities can be detected through queries. Our approach is based on tensor decomposition and clustering methods. We also propose a network generation model to construct synthetic heterogeneous information network to test the performance of the proposed method. The proposed anomaly detection method is compared with state-of-the-art methods in both synthetic and real-world networks. Experimental results show that the proposed tensor-based method considerably outperforms the existing anomaly detection methods. [ABSTRACT FROM AUTHOR]

In this paper, a dual-slot power pickup suitable for an inductive power track system was developed using contactless power transmission techniques. A new strip-type inductive power track with high magnetic flux density and magnetic field uniformity is proposed. A dual-slot type power-pickup structure with high magnetic flux linkage was designed using equivalent magnetic circuit model analysis to improve the power transmission capacity and transmitting efficiency. To verify the contactless transmission characteristics of the proposed strip-type inductive power track system, a 1.2 m long laboratory-scale inductive power track was constructed. The SPLSC topology was used as the compound resonant circuit of a full-bridge inverter. According to the experimental results, the maximum transmitting efficiency of overall system is 72.52% at an output power of 289.52 W. [ABSTRACT FROM AUTHOR]

There currently exists a mature literature on modeling the aggregate load of a distribution feeder by making use of measurements at its feeder-head at substation. The primary application of such feeder-aggregated load models is in sub-transmission or transmission system analysis. However, there is a growing need in practice also to model each individual load across the feeder. If available, such individual load models have applications in power distribution system analysis, e.g., to better integrate distributed energy resources or to improve power quality and reliability. Motivated by this observation, in this paper, we propose a new method for individual load modeling in power distribution systems. It works by using the measurements only at the feeder-head. It takes an innovative approach to analyzing the load switching events across the distribution feeder itself, instead of or in addition to relying on upstream voltage events that are commonly used in feeder-aggregated load modeling. By tracking the downstream load switching events, the proposed method can make a robust estimation of the ZIP load model parameters for all individual loads. The proposed method is examined on small illustrative test-feeders as well as the IEEE 33-bus test system under various operating scenarios. The adverse impact of errors in measurements and system parameters are also investigated on the performance of the developed load modeling method. [ABSTRACT FROM AUTHOR]

This paper proposes a method for calculating short-circuit current in distribution systems with inverter interfaced distributed generators (IIDG). It is capable of calculating the short circuit in a multi-phase distribution systems based on the symmetrical components without obtaining the complete impedance matrix. Furthermore, it considers the load effect and the pre-fault state of the system for the fault analysis and is able to handle unbalanced systems with mutually coupled phases. The problem is formulated as an iterative linear system calculation and is solved by generalized minimal residual (GMRES) approach. The validity of the proposed algorithm is verified through the simulation of IEEE 13-node, 123-node, 478-node, 954-node, and 1430-node distribution systems. Simulation results demonstrate the effectiveness of the proposed algorithm and the advantages of using the GMRES method to calculate the short circuit current in a distribution system with IIDG. [ABSTRACT FROM AUTHOR]

Assembly of power-flow equations has traditionally begun from a nodal analysis formulation of the underlying transmission circuit's behavior. Most power-flow formulations encapsulate network constraints in the bus admittance matrix, $Y_{\text{bus}}$. From a circuit perspective, this admittance representation restricts the network elements to be voltage controlled; resulting drawbacks treating zero-impedance branches in such applications as state estimation have long been recognized. This paper explores the advantages of the alternatives to $Y_{\text{bus}}$ -based formulations in power flow. It proposes a sparse tableau formulation (STF), and it demonstrates its computational efficiency, robustness, and generality in detailed comparison to traditional $Y_{\text{bus}}$ -based solution algorithms. In the examples of power networks ranging from 1888 to 82 000 buses, computational case studies indicate that STF provides comparable computational speed, while allowing simple treatment of zero-impedance branches and more reliably converging to solutions in many cases for which $Y_{\text{bus}}$ -based Newton algorithms diverge. [ABSTRACT FROM AUTHOR]

In this paper, we identify the level shifter (LS) for voltage up-conversion from the ultralow-voltage regime as a key application domain of tunnel FETs (TFETs). We propose a mixed TFET–MOSFET LS design methodology, which exploits the complementary characteristics of TFET and MOSFET devices. Simulation results show that the hybrid LS exhibits superior dynamic performance at the same static power consumption compared with the conventional MOSFET and pure TFET solutions. The advantage of the mixed design with respect to the conventional MOSFET approach is emphasized when lower voltage signals have to be up-converted, reaching an improvement of the energy-delay product up to three decades. When compared with the full MOSFET design, the mixed TFET–MOSFET solution appears to be less sensitive toward threshold voltage variations in terms of dynamic figures of merit, at the expense of higher leakage variability. Similar results are obtained for four different LS topologies, thus indicating that the hybrid TFET–MOSFET approach offers intrinsic advantages in the design of LS for voltage up-conversion from the ultralow-voltage regime compared with the conventional MOSFET and pure TFET solutions. [ABSTRACT FROM PUBLISHER]

This paper shows that existing delay-based testing techniques for power gating exhibit both fault coverage and yield loss due to deviations at the charging delay introduced by the distributed nature of the power-distribution-networks (PDNs). To restore this test quality (TQ) loss, which could reach up to 67.7% of false passes and 25% of false fails due to stuck-open faults, we propose a design-for-testability logic that accounts for a distributed PDN. The proposed logic is optimized by an algorithm that also handles uncertainty due to process variations and offers tradeoff flexibility between test application time and area cost. A calibration process is proposed to bridge model-to-hardware discrepancies and increase TQ when considering systematic variations. Through SPICE simulations, we show complete recovery of the TQ lost due to PDNs. The proposed method is robust, sustaining 80.3%–98.6% of the achieved TQ under high random and systematic process variations. To the best of our knowledge, this paper presents the first analysis of the PDN impact on TQ and offers a unified test solution for both ring and grid power gating styles. [ABSTRACT FROM PUBLISHER]

In this paper, a new circuit model is proposed to simulate plasma-induced damage (PID). It includes the two sheaths of the plasma, the blocking capacitor, and the RF power source coupled with the victim device. As a result, this model accounts for both the ac behavior of the plasma and the local voltage imbalance induced by differences in shading factors. The advantage of this approach, compared with the previous works, is that it can yield the waveform impinged by the plasma on the transistor gate, which is known to influence the amount of reliability degradation experienced by the device. Finally, this model is also utilized to elucidate the impact of a parasitic capacitance connected to the transistor gate on the extent of the PID inflicted on the victim device. [ABSTRACT FROM AUTHOR]

A general equivalent circuit model for the metal/organic semiconductor (OSC)/liquid/metal system is presented. Each circuital element, representative of a physically observable phenomenon associated with the device working principle, is analyzed and discussed. Two case studies of electrochemical impedance spectroscopy of devices featuring NaCl (concentration of 0.1 M) and MilliQ water as liquid are reported, showing that both cases can be considered as a particular case of the general model presented in this paper. Experimental verification of the two practical cases is achieved by performing measurements onto electrodes coated by either an n-type or a p-type OSC deposited by sublimation or drop casting, respectively. The good agreement with the experimental data makes our model a useful tool for the characterization and failure analysis of electronic devices, such as water-gated transistors, electrophysiological interfaces, fuel cells, and others electrochemical systems. [ABSTRACT FROM AUTHOR]

This paper presents a physics-based analytical model for the MOS transistor operating continuously from room temperature down to liquid-helium temperature (4.2 K) from depletion to strong inversion and in the linear and saturation regimes. The model is developed relying on the 1-D Poisson equation and the drift-diffusion transport mechanism. The validity of the Maxwell–Boltzmann approximation is demonstrated in the limit to 0 K as a result of dopant freezeout in cryogenic equilibrium. Explicit MOS transistor expressions are then derived, including incomplete dopant ionization, bandgap widening, mobility reduction, and interface charge traps. The temperature dependence of the interface trapping process explains the discrepancy between the measured value of the subthreshold swing and the thermal limit at deep-cryogenic temperatures. The accuracy of the developed model is validated by experimental results on long devices of a commercial 28-nm bulk CMOS process. The proposed model provides the core expressions for the development of physically accurate compact models dedicated to low-temperature CMOS circuit simulation. [ABSTRACT FROM AUTHOR]