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Quantum Key Distribution (QKD) has garnered significant attention due to its unconditional security based on the fundamental principles of quantum mechanics. While QKD has been demonstrated by various groups and commercial QKD products are available, the development of a fully chip-based QKD system, aimed at reducing costs, size, and power consumption, remains a significant technological challenge. Most researchers focus on the optical aspects, leaving the integration of the electronic components largely unexplored. In this paper, we present the design of a fully integrated electrical control chip for QKD applications. The chip, fabricated using 28 nm CMOS technology, comprises five main modules: an ARM processor for digital signal processing, delay cells for timing synchronization, ADC for sampling analog signals from monitors, OPAMP for signal amplification, and DAC for generating the required voltage for phase or intensity modulators. According to the simulations, the minimum delay is 11ps, the open-loop gain of the operational amplifier is 86.2 dB, the sampling rate of the ADC reaches 50 MHz, and the DAC achieves a high rate of 100 MHz. To the best of our knowledge, this marks the first design and evaluation of a fully integrated driver chip for QKD, holding the potential to significantly enhance QKD system performance. Thus, we believe our work could inspire future investigations toward the development of more efficient and reliable QKD systems. [ABSTRACT FROM AUTHOR]

Digital Signal Processing (DSP) finds a wide range of applications in various fields, including telecommunications, audio and video processing, biomedical engineering, radar systems, and image processing. Previous DSP designs faced limitations in available processing power and computational resources. Insufficient processing power could result in slower execution times, an inability to handle complex algorithms, or limited capacity to process high-speed or large-scale signals. As the demand for minimal power consumption in DSP circuits continues to grow, reversible logic and quantum-dot cellular automata (QCA) have emerged as promising technologies due to their inherent ability to reduce energy loss. Within this landscape, the arithmetic and logic unit (ALU) plays a vital role in complex circuitry, serving as a key component in digital signal processing applications. However, challenges persist, including high quantum cost and the need to limit the number of cells in the ALU design. To address these challenges, our research aims to develop an efficient ALU by integrating reversible logic and QCA technology. Our focus will be on generating essential components, such as Feynman gates, Fredkin gates, and full adder circuits, which serve as foundational building blocks for reversible logic and QCA designs. These components will be combined to construct a comprehensive ALU capable of performing 20 different operations. Our implementation efforts will be centered around QCADesigner, with a specific emphasis on digital signal processing systems that prioritize energy efficiency and optimal utilization of occupied areas. [ABSTRACT FROM AUTHOR]

In the modern technological era of sophisticated applications and high-quality communications, a platform of clever strategy and quickly updated systems is needed. It should be capable of withstanding the fastest emerging problems like signal attenuation and hostile actions intended to harm the whole network. The main contributions of this work are the production of an OFDM system (with low cost) that can sustain high-speed communications and be easily adjusted with new integrated code while exhibiting the feasibility of implementing a transmitter–receiver system in the same DSP and demonstrating the holistic approach with the qualitative integration of such an architecture in a warfare scenario. Specifically, in this research, the point of view is toward three facts. The first is to show a method of quick self-checking the operational status of a digital signal processor (DSP) platform and then the pedagogical issues of how to fast check and implement an updated code inside DSPs through simple schematics. The second point is to present the prototype system that can easily be programmed using a graphical user interface (GUI) and can change its properties (such as the transmitted modulated sinusoids—orthogonal frequency division multiplexing subcarriers). Alongside the presentation, the measurements are presented and discussed. These were acquired with the use of an oscilloscope and spectrum analyzer. The third point is to qualitatively show the application of such a system inside a modern warfare environment and to recommend various potential system responses according to the development of such a platform of reconfigurable implemented OFDM systems. The implementation was performed for two types of systems: (1) transmitter and (2) transmitter–receiver system. Notably, the system acts quickly with a delay of about 1 msec in the case of transmitting and receiving in the same DSP, suggesting excellent future results under real conditions. [ABSTRACT FROM AUTHOR]

The advantageous applications of magnetic bistable microwires have emerged during long-lasting research. They have a wide range of applications in the scientific sphere or technical practice. They can be used for various applications, including magnetic memories, biomedicine, and sensors. This manuscript is focused on the last-mentioned application of microwires—sensors—discussing various digital signal processing techniques used in practical applications. Thanks to the highly sensitive properties of microwires and their two stable states of magnetization, it is possible to perform precise measurements with less demanding digital processing. The manuscript presents four practical signal-processing methods of microwire response using three different experiments. These experiments are focused on detecting the signal in a simple environment without an external magnetic background, measuring with the external background of a ferromagnetic core, and measuring in harsh conditions with a strong magnetic background. The experiments aim to propose the best method under various conditions, emphasizing the quality and signal processing speed of the microwire signal. [ABSTRACT FROM AUTHOR]

Due to their user-friendliness and reliability, biometric systems have taken a central role in everyday digital identity management for all kinds of private, financial and governmental applications with increasing security requirements. A central security aspect of unsupervised biometric authentication systems is the presentation attack detection (PAD) mechanism, which defines the robustness to fake or altered biometric features. Artifacts like photos, artificial fingers, face masks and fake iris contact lenses are a general security threat for all biometric modalities. The Biometric Evaluation Center of the Institute of Safety and Security Research (ISF) at the University of Applied Sciences Bonn-Rhein-Sieg has specialized in the development of a near-infrared (NIR)-based contact-less detection technology that can distinguish between human skin and most artifact materials. This technology is highly adaptable and has already been successfully integrated into fingerprint scanners, face recognition devices and hand vein scanners. In this work, we introduce a cutting-edge, miniaturized near-infrared presentation attack detection (NIR-PAD) device. It includes an innovative signal processing chain and an integrated distance measurement feature to boost both reliability and resilience. We detail the device's modular configuration and conceptual decisions, highlighting its suitability as a versatile platform for sensor fusion and seamless integration into future biometric systems. This paper elucidates the technological foundations and conceptual framework of the NIR-PAD reference platform, alongside an exploration of its potential applications and prospective enhancements. [ABSTRACT FROM AUTHOR]

In signal processing applications, the multipliers are essential component of arithmetic functional units in many applications, like digital signal processors, image/video processing, Machine Learning, Cryptography and Arithmetic & Logical units (ALU). In recent years, Profuse multipliers are there. In that, Vedic multiplier is one of the high-performance multiplications and it is used to signal/image processing applications. In order to ameliorate the performance of this multiplier further, by proposed a novel multiplier using hybrid compressor. The proposed hybrid compressor-based multiplier is designed and implemented in Field programmable Gate Array (FPGA—spartan 6). The synthesis result shows that the speed of proposed hybrid compressor-based multiplier gets improved as compared to Array multiplier (35.83%), Wallace tree multiplier (34.58%), Vedic Multiplier based on Carry look ahead adder (CLA) (28.49%), Vedic Multiplier based on Ripple carry adder (RCA) (20.65%), Booth Multiplication (21.65%) and Vedic Multiplication based on Han-Carlson Adder (HCA) (20.10%) and Hybrid multiplier using Carry Select Adder (CSELA) (17.81%) and Hybrid Vedic Multiplier (7.15%). [ABSTRACT FROM AUTHOR]

Emotion recognition systems from speech signals are realized with the help of acoustic or spectral features. Acoustic analysis is the extraction of digital features from speech files using digital signal processing methods. Another method is the analysis of time-frequency images of speech using image processing. The size of the features obtained by acoustic analysis is in the thousands. Therefore, classification complexity increases and causes variation in classification accuracy. In feature selection, features unrelated to emotions are extracted from the feature space and are expected to contribute to the classifier performance. Traditional feature selection methods are mostly based on statistical analysis. Another feature selection method is the use of metaheuristic algorithms to detect and remove irrelevant features from the feature set. In this study, we compare the performance of metaheuristic feature selection algorithms for speech emotion recognition. For this purpose, a comparative analysis was performed on four different datasets, eight metaheuristics and three different classifiers. The results of the analysis show that the classification accuracy increases when the feature size is reduced. For all datasets, the highest accuracy was achieved with the support vector machine. The highest accuracy for the EMO-DB, EMOVA, eNTERFACE'05 and SAVEE datasets is 88.1%, 73.8%, 73.3% and 75.7%, respectively. [ABSTRACT FROM AUTHOR]

Blind source separation (BSS), as a digital signal processing approach, focuses on estimating the underlying source signals from their linear mixtures without any prior information about the source signals and mixing matrix. Conventional methods for the BSS, however, are incapable of separating the complex-valued source signals. By leveraging the negative conjugate gradient to minimize the least mean square error reconstruction (LMSER) principle in complex domain, this paper proposes a collection of least-squares algorithms for complex-valued BSS (CBSS), including least-mean square (LMS)-type algorithms and recursive least-squares (RLS)-type algorithms. We demonstrate the availability of the proposed algorithms in both circular and non-circular source signals separation. Especially, the RLS algorithm for the CBSS without prewhitening is superior in cross-talking criterion to the others, as verified by computer simulations on artificial source signals. [ABSTRACT FROM AUTHOR]

This paper investigates optimizing the power exchange between electric vehicles (EVs) and the grid, with a specific focus on the DC-DC converters utilized in vehicle-to-grid (V2G) systems. It specifically explores using model predictive control (MPC) in synchronous boost converters to enhance efficiency and performance. Through experiments and simulations, this paper shows that replacing diodes with SIC MOSFETs in boost converters significantly improves efficiency, particularly in synchronous mode, by minimizing the deadtime of SIC MOSFETs during switching. Additionally, this study evaluates MPC's effectiveness in controlling boost converters, highlighting its advantages over traditional control methods. Real-world validations further validate the robustness and applicability of MPC in V2G systems. This study utilizes TMS320F28379D, one of Texas Instruments' leading digital signal processors, enabling the implementation of MPC with a high PWM frequency of up to 200 MHz. This processor features dual 32-bit CPUs and a 16-bit ADC, allowing for high-resolution readings from sensors. Leveraging digital signal processing technologies and advanced electronic circuits, this study advances the development of high-performance boost converters, achieving power outputs of up to 48 watts and output voltages of 24 volts. Electronic circuits (PCB boards) have been devised, implemented, and evaluated to showcase their significance in advancing efficient V2G integration. [ABSTRACT FROM AUTHOR]

In recent years, headphones have become increasingly popular worldwide. There are numerous models on the market today, varying in technical characteristics and offering different listening experiences. This article presents an application for simulating the sound response of specific headphone models by physically wearing others. In the future, for example, this application could help to guide people who already own a pair of headphones during the decision-making process of purchasing a new headphone model. However, the potential fields of application are much broader. An in-depth study of digital signal processing was carried out with the implementation of a computational model. Prior to this, an analysis was performed on impulse response measurements of specific headphones, which allowed for a better understanding of the behavior of each set of headphones. Finally, an evaluation of the entire system was conducted through a listening test. The analysis of the results showed that the software works reasonably well in replicating the target headphones. We hope that this work will stimulate further efforts in the same direction. [ABSTRACT FROM AUTHOR]

The (p, fc)-parametrization technique introduced by Alaca provides an alternative approach for formulating several new Eisenstein series identities involving Borwein's theta functions. As a practical example, we have computed the convolution sum of divisor functions, which exhibit a connection with Eisenstein series. [ABSTRACT FROM AUTHOR]

Enhanced Loran (eLoran) is the most important backup system for Global Navigation Satellite System (GNSS). However, most current eLoran demodulation methods are based on digital signal processing, which may produce large errors under the influence of strong interference or noise. The authors propose an eLoran signal message prediction algorithm based on deep learning. Using time‐frequency (TF) analysis convert one‐dimensional signal into two‐dimensional high‐resolution image. It improves Alexnet by adjusting the convolutional layer structure, adding an attention module, and reducing the pooling layer window to construct the Alexnet‐ECA network. The network is used to identify TF image features and predict signal message. The experimental results show that novel method for eLoran signal message prediction based on Alexnet‐ECA can achieve high accuracy and robustness in various SNR scenarios. The accuracy is more than 90% at SNR greater than 10db and not less than 80% even in the complex environments. Compared with Resnet34 and VGG16 networks, Alexnet‐ECA demonstrates its efficiency and effectiveness using real measurement data. This method can enhance the performance and reliability of eLoran receivers and applications. [ABSTRACT FROM AUTHOR]

This study investigates the biomechanical impact of a passive Arm-Support Exoskeleton (ASE) on workers in wool textile processing. Eight workers, equipped with surface electrodes for electromyography (EMG) recording, performed three industrial tasks, with and without the exoskeleton. All tasks were performed in an upright stance involving repetitive upper limbs actions and overhead work, each presenting different physical demands in terms of cycle duration, load handling and percentage of cycle time with shoulder flexion over 80°. The use of ASE consistently lowered muscle activity in the anterior and medial deltoid compared to the free condition (reduction in signal Root Mean Square (RMS) − 21.6 % and − 13.6 % , respectively), while no difference was found for the Erector Spinae Longissimus (ESL) muscle. All workers reported complete satisfaction with the ASE effectiveness as rated on Quebec User Evaluation of Satisfaction with Assistive Technology (QUEST), and 62% of the subjects rated the usability score as very high (>80 System Usability Scale (SUS)). The reduction in shoulder flexor muscle activity during the performance of industrial tasks is not correlated to the level of ergonomic risk involved. This preliminary study affirms the potential adoption of ASE as support for repetitive activities in wool textile processing, emphasizing its efficacy in reducing shoulder muscle activity. Positive worker acceptance and intention to use ASE supports its broader adoption as a preventive tool in the occupational sector. [ABSTRACT FROM AUTHOR]

Passive location based on TDOA (time difference of arrival) and FDOA (frequency difference of arrival) is the mainstream method for target localization. This paper proposes a fast time–frequency difference positioning method to address issues such as low accuracy, large computational resource utilization, and limited suitability for real-time signal processing in the conventional CAF (cross-ambiguity function)-based approach, aiming to complete the processing of the target radiation source to obtain the target parameters within a short timeframe. In the mixing product operation step of the CAF, a frequency-domain approach replaces the time-domain convolution operation in PW-ZFFT (pre-weighted Zoom-FFT) to reduce the computational load of the CAF. Additionally, a quadratic surface fitting method is used to enhance the accuracy of TDOA and FDOA. The localization solution is obtained using Newton's method, which can provide more accurate results compared to analytical methods. Next, a signal processing platform is designed with FPGA (field-programmable gate array) and multi-core DSP (digital signal processor), and works by dividing and mapping the algorithm functional modules according to the hardware's characteristics. We analyze the architectural advantages of multi-core DSP and design methods to improve program performance, such as EDMA transfer optimization, inline function optimization, and cache optimization. Finally, this paper constructs simulation tests in typical positioning scenarios and compares them to hardware measurement results, thus confirming the correctness and real-time capability of the program. [ABSTRACT FROM AUTHOR]

Permanent magnet (PM) motors are gaining prominence in subsea applications such as drilling, pumping, and boosting for oil and natural gas extraction. These motors are gradually replacing traditional induction motors. However, starting and operating PM motors at low speeds under heavy loads poses significant challenges. This is because of unknown initial rotor positions and resistive voltage drops due to the presence of a sinewave filter, transformer, and long cable. An unknown rotor position may result in temporary reverse speed, which may cause a loss of synchronism; therefore, initial rotor position estimation is preferable. Additionally, addressing the voltage drop issue requires careful voltage compensation to avoid transformer core saturation. In this paper, an enhanced V / H z starting of a PM motor is proposed with initial position detection (IPD) and voltage compensation to start the motor reliably with a heavy load. The proposed control method is verified with controller hardware in the loop (C-HIL) real-time simulation using a Typhoon HIL-604 emulator and a Texas Instruments TMS320F28335 digital signal processor (DSP) control card. [ABSTRACT FROM AUTHOR]

In electrified transportation systems, power system failures can lead to greater disasters. Therefore, the reliability of converters in transportation systems has been a concern. Fault-tolerant techniques are widely applied to ensure that converters can continue to supply loads under fault conditions. Fault diagnosis as a prerequisite for fault tolerance has also become a research hotspot. This paper proposes a fast method for fault diagnosis of high-frequency LLC converters. The proposed fault diagnosis method is based on the observation of the voltage across the resonant capacitor to determine and locate the faulty power switch, providing a basis for fault tolerance. This diagnosis method requires a voltage sensor, which is also necessary for some control methods. When applying these control methods, the proposed fault diagnosis method can be used without additional sensors, beneficial for cost reduction. A full-bridge LLC converter controlled by a digital signal processor was used as an experimental platform to verify the effectiveness and speed of the proposed diagnostic method. The results show that the proposed fault diagnosis method can achieve the fast diagnosis of high-frequency LLC converters in a short time and with only minimal computational resources. [ABSTRACT FROM AUTHOR]

Modern electrical power systems are characterized by a high rate of transient processes, the use of digital monitoring and control systems, and the accumulation of a large amount of technological information. The active integration of renewable energy sources contributes to reducing the inertia of power systems and changing the nature of transient processes. As a result, the effectiveness of emergency control systems decreases. Traditional emergency control systems operate based on the numerical analysis of power system dynamic models. This allows for finding the optimal set of preventive commands (solutions) in the form of disconnections of generating units, consumers, transmission lines, and other primary grid equipment. Thus, the steady-state or transient stability of a power system is provided. After the active integration of renewable sources into power systems, traditional emergency control algorithms became ineffective due to the time delay in finding the optimal set of control actions. Currently, machine learning algorithms are being developed that provide high performance and adaptability. This paper contains a meta-analysis of modern emergency control algorithms for power systems based on machine learning and synchronized phasor measurement data. It describes algorithms for determining disturbances in the power system, selecting control actions to maintain transient and steady-state stability, stability in voltage level, and limiting frequency. This study examines 53 studies piled on the development of a methodology for analyzing the stability of power systems based on ML algorithms. The analysis of the research is carried out in terms of accuracy, computational latency, and data used in training and testing. The most frequently used textual mathematical models of power systems are determined, and the most suitable ML algorithms for use in the operational control circuit of power systems in real time are determined. This paper also provides an analysis of the advantages and disadvantages of existing algorithms, as well as identifies areas for further research. [ABSTRACT FROM AUTHOR]

We describe a method for reducing the cost of optical frequency domain reflectometer (OFDR) hardware by replacing two reference channels, including an auxiliary interferometer and a gas cell, with a single channel. To extract useful information, digital signal processing methods were used: digital frequency filtering, as well as empirical mode decomposition. It is shown that the presented method helps to avoid the use of an unnecessary analog-to-digital converter and photodetector, while the OFDR trace is restored by the equal frequency resampling (EFR) algorithm without loss of high resolution and with good measurement repeatability. [ABSTRACT FROM AUTHOR]

Quantum key distribution (QKD) is one quantum technology that can provide secure encryption keys for data transmission. The secret key rate (SKR) is a core performance indicator in QKD, which directly determines the transmission rate of enciphered data. Here, for the first time, we demonstrate a high-key-rate Gaussian-modulated continuous-variable QKD (CV-QKD) using telecom optical components. The framework of CV-QKD over these components is constructed. Specifically, the high-rate low-noise Gaussian modulation of coherent states is realized by a classical optical IQ modulator. High-baud low-intensity quantum signals are received by an integrated coherent receiver under the shot-noise limit. A series of digital signal processing algorithms are proposed to achieve accurate signal recovery and key distillation. The system can yield a high asymptotic SKR of 10.37 Mbps within 20 km standard telecom fiber, and the secure distance can exceed 100 km. This result confirms the feasibility of CV-QKD with state-of-the-art performance using telecom optical components. Besides, due to the ease of integrating these discrete components, it provides a high-performance and miniaturized QKD solution for the metropolitan quantum network. [ABSTRACT FROM AUTHOR]

Solid-state transformers (SSTs) are expected to become one of the most powerful and adaptable devices that allow controllable voltage, power factor correction, fault isolation, compact size as compared to their low-frequency (50 Hz/60 Hz) counterparts. The high-frequency isolation of single-phase modified quasi-Z-source AC–AC converter (SPM-qZAC) employing bidirectional switches to create the single-stage SPM-qZAC-based SST is proposed in this paper. The proposed topology offers all the benefits of conventional impedance source topologies, including single-stage power conversion with a small footprint, buck–boost operation and retaining or reversing the phase angle. Moreover, the presented converter topology allows to share the same ground between input and output voltage, continuous input current, no input–output LC filters and performs AC–AC power conversion without the use of DC storage, making it suitable for AC voltage regulation. This study introduces two modulation schemes for SPM-qZAC-based SST. Finite control set model predictive control (FCS-MPC) which is a current control technique at variable switching frequency is employed owing to the capabilities of modern digital signal processing. Further, an adaptive hysteresis band-based delta sigma modulation (DSM) technique that offers the benefit of constant switching frequency (CSF) is proposed as an alternative voltage control-based modulation of the same topology. Various performance indices including steady-state response, total harmonic distortion of source current and dynamic response are assessed through simulation studies using MATLAB/Simulink software and real-time simulation environment using RT-Lab with OPAL-RT OP4510. It is observed that SPM-qZAC exhibits good performance when modulated using either modulation techniques; however, CSF-DSM technique offers an additional benefit of constant switching frequency. [ABSTRACT FROM AUTHOR]

A frequency/phase/amplitude estimator is arguably one of the most crucial components in the control and synchronization of grid-connected equipment. Such an estimator may also be useful for monitoring and protection purposes in power systems. In this paper, an open-loop (and therefore unconditionally stable) estimator for the accurate and rapid extraction of the grid voltage phase, frequency, and amplitude is presented. In designing the proposed technique, special focus is given to applications operating at a low sampling rate. Examples of such applications include high-power converters, where both switching and sampling frequencies are very low. The study concludes with a comprehensive evaluation of the proposed estimator, demonstrating its effectiveness in accurately and swiftly estimating the fundamental parameters of grid voltage under low sampling rates. It highlights the estimator's enhanced performance in scenarios of distorted grid conditions and its superiority in filtering capabilities compared to traditional methods. These findings underline the estimator's potential for broad applicability in power system monitoring, protection, and control. [ABSTRACT FROM AUTHOR]

The ability to sense propagating electromagnetic plane waves based on their directions of arrival (DOAs) is fundamental to a range of radio frequency (RF) sensing, communications, and imaging applications. This paper introduces an algorithm for the wideband true time delay digital delay Vandermonde matrix (DVM), utilizing Thiran fractional delays that are useful for realizing RF sensors having multiple look DOA support. The digital DVM algorithm leverages sparse matrix factorization to yield multiple simultaneous RF beams for low-complexity sensing applications. Consequently, the proposed algorithm offers a reduction in circuit complexity for multi-beam digital wideband beamforming systems employing Thiran fractional delays. Unlike finite impulse response filter-based approaches which are wideband but of a high filter order, the Thiran filters trade usable bandwidth in favor of low-complexity circuits. The phase and group delay responses of Thiran filters with delays of a fractional sampling period will be demonstrated. Thiran filters show favorable results for sample delay blocks with a temporal oversampling factor of three. Thiran fractional delays of orders three and four are mapped to Xilinx FPGA RF-SoC technologies for evaluation. The preliminary results of the APF-based Thiran fractional delays on FPGA can potentially be used to realize DVM factorizations using application-specific integrated circuit (ASIC) technology. [ABSTRACT FROM AUTHOR]

We are completely aware of the fact that ternary algebraic structures in some way naturally occur in diverse fields of theoretical and mathematical physics, computer science, especially in ternary operators in Java and Python, ternary logic applied for digital signal processing, and musical systems for song composition. The primary aim of this research is to examine ternary semigroups in the context of hybrid quasi-ideals and hybrid A-ideals. Different features of hybrid quasi-ideals and hybrid A-ideals in the ternary semigroup are discussed. In addition, the idea of minimal hybrid A-ideals of ternary semigroups is defined. [ABSTRACT FROM AUTHOR]

The arithmetic and logic unit (ALU) is a key element of complex circuits and an intrinsic part of the most widely recognized complex circuits in digital signal processing. Also, recent attention has been brought to reversible logic and quantum-dot cellular automata (QCA) because of their intrinsic capacity to decrease energy dissipation, which is a crucial need for low-power digital circuits. QCA will be the preferred technology for developing the subsequent generation of digital systems. These technologies played a substantial role in the design of the ALU for operations such as multiplication, subtraction, and division. In developing reversible logic and QCA technologies, the ALU is frequently studied as a central unit. Implementing an efficient ALU with low quantum cost and a small number of cells based on an efficient reversible block can solve all previous issues. Therefore, this research constructs a Feynman gate, a Fredkin gate, and full adder circuits using reversible logic and QCA technology. Using all of the specified circuits, a 20-operation ALU is constructed. The power consumption of the proposed ALU under various energy ranges demonstrated significant improvements over earlier designs. [ABSTRACT FROM AUTHOR]

The combination of wet-lab experimental data on multi-site combinatorial mutations and machine learning is an innovative method in protein engineering. In this study, we used an innovative sequence-activity relationship (innov'SAR) methodology based on novel descriptors and digital signal processing (DSP) to construct a predictive model. In this paper, 21 experimental (R)-selective amine transaminases from Aspergillus terreus (AT-ATA) were used as an input to predict higher thermostability mutants than those predicted using the existing data. We successfully improved the coefficient of determination (R2) of the model from 0.66 to 0.92. In addition, root-mean-squared deviation (RMSD), root-mean-squared fluctuation (RMSF), solvent accessible surface area (SASA), hydrogen bonds, and the radius of gyration were estimated based on molecular dynamics simulations, and the differences between the predicted mutants and the wild-type (WT) were analyzed. The successful application of the innov'SAR algorithm in improving the thermostability of AT-ATA may help in directed evolutionary screening and open up new avenues for protein engineering. [ABSTRACT FROM AUTHOR]

The electroencephalogram (EEG) examination provides information on the brain's electricity, especially in cases of epilepsy. Since the characteristics of EEG signals are nonlinear and nonstationary, visual inspection becomes very difficult. To overcome this problem, digital EEG signal processing was developed. Automatic epileptic EEG recognition is an area of interest on which much research focuses. The complexity approach to EEG signal analysis is interesting to be used as feature extraction, referring to the nonlinear characteristics of the signal. This study proposed an automatic epileptic EEG classification method based on the multiscale Hjorth descriptor measurement. EEG signals consisting of normal, interictal, and seizure (ictal) were simulated. The signal is scaled into new signals using the coarse-grained procedure on a scale of 1–20. Then, the Hjorth parameter which consists of activity, mobility, and complexity is calculated on the new signal. This process produces a feature vector that is used in the classification stage. Support vector machine (SVM) is used to evaluate the proposed feature extraction method. Simulation results showed that the Hjorth parameter on a scale of 1–15 yields 99.5% accuracy. The proposed method is expected to be applied to digital EEG for seizure detection and prediction. [ABSTRACT FROM AUTHOR]

Due to the complex range migration characteristics of large squint angle synthetic aperture radar (SAR), it is difficult for traditional SAR deceptive jamming algorithms to balance focusing ability and computational efficiency. There is an urgent demand for proposing a deceptive jamming algorithm against large squint angle SAR in the field of SAR jamming. This article proposes a deceptive jamming algorithm against SAR with large squint angles based on non-linear chirp scaling and low azimuth sampling reconstruction (NLCSR). The NLCSR algorithm uses a high-order approximation of a high-precision model to accurately construct the jammer's frequency response (JFR) function. In line with the notion of low azimuth sampling processing of the transformation domain, the construction of the space-variant azimuth modulation phase item is completed using the non-linear chirp scaling method. Compared with the traditional deceptive jamming algorithms against the large squint angle SAR, the NLCSR algorithm only needs Fourier transform and complex multiplication while ensuring the focusing ability, which is easier to implement on an efficient parallel digital signal processor based on fast Fourier transform (FFT). Simulation results prove the superior property of the NLCSR algorithm in focusing ability and computational efficiency. Compared to the existing large squint angle SAR deceptive jamming algorithm, the focusing ability of the NLCSR algorithm is almost the same, and the calculation efficiency is improved by at least 52.1%. [ABSTRACT FROM AUTHOR]

The advancement in technology and the availability of specialized digital signal processing chips have made digital filter design and implementation more feasible in a variety of fields, including biomedical engineering. This paper makes two key contributions. First, it uses a genetic algorithm to optimize the coefficients of finite impulse response (FIR) filters. Second, it conducts a case study on using genetic algorithms to optimize FIR filters for electrocardiogram (ECG) biomedical signal noise removal. The goal of the proposed filter design approach is to achieve the desired signal bandwidth while minimizing the side lobe level and eliminating unwanted signals using a genetic algorithm. The results of a comprehensive analysis show that the genetic algorithm-based filter is more effective than conventional filter designs in terms of noise removal efficiency. [ABSTRACT FROM AUTHOR]

The Number Theoretic Transform (NTT) has been widely used to speed up polynomial multiplication in lattice-based post-quantum algorithms. All NTT operands use modular arithmetic, especially modular multiplication, which significantly influences NTT hardware implementation efficiency. Until now, most hardware implementations used Digital Signal Processing (DSP) to multiply two integers and optimally perform modulo computations from the multiplication product. This paper presents a customized Lattice-DSP (L-DSP) for modular multiplication based on the Karatsuba algorithm, Vedic multiplier, and modular reduction methods. The proposed L-DSP performs both integer multiplication and modular reduction simultaneously for lattice-based cryptography. As a result, the speed and area efficiency of the L-DSPs are 283 MHz for 77 SLICEs, 272 MHz for 87 SLICEs, and 256 MHz for 101 SLICEs with the parameters q of 3329, 7681, and 12,289, respectively. In addition, the N − 1 multiplier in the Inverse-NTT (INTT) calculation is also eliminated, reducing the size of the Butterfly Unit (BU) in CRYSTAL-Kyber to about 104 SLICEs, equivalent to a conventional multiplication in the other studies. Based on the proposed DSP, a Point-Wise Matrix Multiplication (PWMM) architecture for CRYSTAL-Kyber is designed on a hardware footprint equivalent to 386 SLICEs. Furthermore, this research is the first DSP designed for lattice-based Post-quantum Cryptography (PQC) modular multiplication. [ABSTRACT FROM AUTHOR]

Few new Eisenstein series identities involving Borwein’s theta functions are formulated using (p, k)- parametrization technique which is introduced by Alaca. As an application, we have evaluated the convolution sum of divisor functions which are related to Eisenstein series. [ABSTRACT FROM AUTHOR]

Flexoelectricity is a nanoscale phenomenon in dielectric crystals, where the mechanical loads resulting from the first strain gradient shares producing electricity. In this work, we present a numerical investigation for the plane strain problem of the dynamical flexoelectric effect in isotropic dielectrics. A surface loading based on the Sinc function, that is, sincπ(x), with a temporal exponentially decay, is applied to the upper surface of a semi-infinite dielectric crystal. Two cases for the electric potential are considered: (1) Open circuit, in which there is zero charge on the terminals; and (2) Short-circuit, where there is a given value for the potential of the terminals. This type of surface loading is often used in applications such as seismic analysis and electrical engineering, especially signal processing and digital signal processing. Also, it can be used to model other types of dynamic loads, such as wind or wave loads. Furthermore, this setting generates a two-dimensional formulation, known as the plane strain problem. Laplace and Fourier transform techniques are employed for solving the field equations. Suitable numerical techniques are implemented to present the solution to the physical domain. We choose the Strontium Titanate material (SrTiO3) for the two-dimensional simulation. Discussion for the behavior of the dynamical polarization, electric field, electric potential, and stresses is provided in the two-dimensional setting. Effects of the model parameters on electricity generation and behavior are studied. [ABSTRACT FROM AUTHOR]

In practice, inverter dead time and digital signal processing delay are influential factors in classic predictive control performance. In this paper, delay compensation in finite-set model predictive current control (FS-MPCC) and inverter dead-time compensation in deadbeat predictive control are considered to improve permanent magnet synchronous machine control steady-state error, current and torque ripples, reduce the computational burden, correct inverter dead time-induced deviation, and reduce the sensitivity of parameter uncertainties. Deadbeat control uses a space vector modulation (SWM) block and converts the controller output voltage into duty cycles imposed on the inverter ensuring a fixed inverter switching frequency as opposed to FS-MPCC, which uses a finite set of switching states with a variable switching frequency (without modulation). The second approach looks at how a Takagi–Sugeno fuzzy logic speed controller (TS-FLC) can be applied to operate an intelligent system, offering a great current reference, which is crucial for the design of the FS-MPCC cost function and the deadbeat inner-loop control. A speed estimation observer based on a model reference adaptive system (MRAS) is suggested. By eliminating the encoder or speed sensor, the observer improves system reliability, boosts control performance, and reduces costs. The chosen FS-MPCC and deadbeat controller will be built and used in the laboratory utilizing DSpace.1104. The experimental results comparison shows that both FS-MPCC and deadbeat can be well applied to the PMSM driving system with good speed tracking performance. However, the FS-MPCC can achieve less harmonics in the stator currents and shows advantages in smaller ripples in the mechanical torque. [ABSTRACT FROM AUTHOR]

To achieve low power consumption and high performance, an approximate multiplier is a commonly used operation. A new approximate computation method has been used for Error Tolerant Image Processing applications. This operation is popular in error tolerance applications. Inexact computing is applied to error-tolerant digital signal processing applications where error can be tolerated. Multiplier is the basic unit of arithmetic logic unit of any computer computational unit. In this paper, a new approximate compressor computation method is proposed for error-tolerant image processing applications. An approximate compressor has been designed for better output power with an improved figure of merit. A comparison of the proposed compressor with the previous 4:2 compressor design has been investigated and a reduction in area, delay and power consumption has been achieved. A similar algorithm has been applied to 8-bit multiplier applications which have considerable error performance. With the newly designed multiplier using a compressor, the simulation results compared the best power utilization. The results of designing the multiplier indicate that the proposed design of a multiplier using an approximate compressor achieves a reduction in power by 129 mw. [ABSTRACT FROM AUTHOR]

Square-root unscented Kalman filter (SRUKF) is a widely used state estimator for several state of-the-art, highly nonlinear, and critical applications. It improves the stability and numerical accuracy of the system compared to the non-square root formulation, the unscented Kalman filter (UKF). At the same time, SRUKF is less computationally intensive compared to UKF, making it suitable for portable and battery-powered applications. This paper proposes a low-complexity and power-efficient architecture design methodology for SRUKF presented with a use case of the simultaneous localization and mapping (SLAM) problem. Implementation results show that the proposed SRUKF methodology is highly stable and achieves higher accuracy than the extensively used extended Kalman filter and UKF when developed for highly critical nonlinear applications such as SLAM. The design is synthesized and implemented on resource constraint Zynq-7000 XC7Z020 FPGA-based Zedboard development kit and compared with the state-of-the-art Kalman filter-based FPGA designs. Synthesis results show that the architecture is highly stable and has significant computation savings in DSP cores and clock cycles. The power consumption was reduced by 64 % compared to the state-of-the-art UKF design methodology. ASIC design was synthesized using UMC 90-nm technology, and the results for on-chip area and power consumption results have been discussed. [ABSTRACT FROM AUTHOR]

This article compares two methods of algorithmically processing bandlimited time-continuous signals in light of the general problem of finding "suitable" representations of analog information on digital hardware. Albeit abstract, we argue that this problem is fundamental in digital twinning, a signal-processing paradigm the upcoming 6G communication-technology standard relies on heavily. Using computable analysis, we formalize a general framework of machine-readable descriptions for representing analytic objects on Turing machines. Subsequently, we apply this framework to sampling and interpolation theory, providing a thoroughly formalized method for digitally processing the information carried by bandlimited analog signals. We investigate discrete-time descriptions, which form the implicit quasi-standard in digital signal processing, and establish continuous-time descriptions that take the signal's continuous-time behavior into account. Motivated by an exemplary application of digital twinning, we analyze a textbook model of digital communication systems accordingly. We show that technologically fundamental properties, such as a signal's (Banach-space) norm, can be computed from continuous-time, but not from discrete-time descriptions of the signal. Given the high trustworthiness requirements within 6G, e.g., employed software must satisfy assessment criteria in a provable manner, we conclude that the problem of "trustworthy" digital representations of analog information is indeed essential to near-future information technology. [ABSTRACT FROM AUTHOR]

An alternating representation of integers in binary form is proposed, in which the numbers -1 and +1 are used instead of zeros and ones. It is shown that such a representation creates considerable convenience for multiplication numbers modulo p = 2n+1. For such numbers, it is possible to implement a multiplication algorithm modulo p, similar to the multiplication algorithm modulo the Mersenne number. It is shown that for such numbers a simple algorithm for digital logarithm calculations may be proposed. This algorithm allows, among other things, to reduce the multiplication operation modulo a prime number p = 2n+1 to an addition operation. [ABSTRACT FROM AUTHOR]

Addition is a fundamental computer arithmetic operation that is widely performed in microprocessors, digital signal processors, and application-specific processors. The design of a high-speed and energy-efficient adder is thus useful and important for practical applications. In this context, this paper presents the designs of novel asynchronous carry look-ahead adders (CLAs) viz. a standard CLA (SCLA) and a block CLA (BCLA). The proposed CLAs are monotonic, dual-rail encoded, and are realized according to return-to-zero handshake (RZH) and return-to-one handshake (ROH) protocols using a 28-nm CMOS process technology. The proposed BCLA has a slight edge over the proposed SCLA, and the proposed BCLA reports the following optimizations in design metrics such as cycle time (delay), area, and power compared to a recently presented state-of-the-art asynchronous CLA for a 32-bit addition: (i) 32.6% reduction in cycle time, 29% reduction in area, 4.3% reduction in power, and 35.5% reduction in energy for RZH, and (ii) 31.4% reduction in cycle time, 28.9% reduction in area, 4.4% reduction in power, and 34.4% reduction in energy for ROH. Also, the proposed BCLA reports reductions in cycle time and power/energy compared to many other asynchronous adders. [ABSTRACT FROM AUTHOR]

The FMCW (Frequency Modulated Continuous Wave) laser interferometer can achieve high-precision displacement measurement by calculating the phase of the interference signal. Due to the need for continuous superposition of signal phases, the optical path and power supply cannot be interrupted during the measurement process. To solve this problem, this article proposes a new absolute ranging method—the decimal comparison method. Two distributed feedback lasers with different central wavelengths are used to measure the same target. The digital signal processing technology is used to solve the sampled interference signals, and the initial phase value corresponding to the decimal of interference is taken. Combined with the central wavelength of the two laser sources, the length variation of the F–P cavity corresponding to the number of interference periods is calculated. Finally, the optical path difference of the target is calculated by the established mathematical model. The experimental results show that this method can realize the absolute measurement of laser interferometry and can expand the application range of FMCW interferometry. [ABSTRACT FROM AUTHOR]

This study addresses the challenge of motion control in autonomousvehicles through the introduction of a novel profile generation design. Specifically,autonomous vehicles often contend with uncertain factors and physicallimitations within their operational environments, such as abrupt changes inacceleration or intricate parametric motion profiles. To tackle this problem, afiltering technique for motion profile generation is proposed, leveraging ahardware programming language as its foundation. The investigation begins byanalyzing the specific structure of the mobile platform, which includes twoactive side wheels, two passive rear wheels, a high load capacity, and adifferential drive mode. Building upon this theoretical basis, the proposedfiltering technique is introduced to attain smooth motion profiles and optimizetiming. Furthermore, the study suggests the use of FPGA (Field ProgrammableGate Array) acceleration to expedite these computations for swift motionprocessing. To validate the efficacy of the proposed method, both the mobilevehicle and the load are simulated as a one‐axis linear ball‐screw system withan aluminum ruler. The experimental results unequivocally demonstrate theeffectiveness, feasibility, and applicability of the proposed approach across avariety of industrial solutions. [ABSTRACT FROM AUTHOR]

At present, a medium-level microcontroller is capable of performing edge computing and can handle the computation of neural network kernel functions. This makes it possible to implement a complete end-to-end solution incorporating signal acquisition, digital signal processing, and machine learning for the classification of cardiac arrhythmias on a small wearable device. In this work, we describe the design and implementation of several classifiers for atrial fibrillation detection on a general-purpose ARM Cortex-M4 microcontroller. We used the CMSIS-DSP library, which supports Naïve Bayes and Support Vector Machine classifiers, with different kernel functions. We also developed Python scripts to automatically transfer the Python model (trained in Scikit-learn) to the C environment. To train and evaluate the models, we used part of the data from the PhysioNet/Computing in Cardiology Challenge 2020 and performed simple classification of atrial fibrillation based on heart-rate irregularity. The performance of the classifiers was tested on a general-purpose ARM Cortex-M4 microcontroller (STM32WB55RG). Our study reveals that among the tested classifiers, the SVM classifier with RBF kernel function achieves the highest accuracy of 96.9%, sensitivity of 98.4%, and specificity of 95.8%. The execution time of this classifier was 720 μ s per recording. We also discuss the advantages of moving computing tasks to edge devices, including increased power efficiency of the system, improved patient data privacy and security, and reduced overall system operation costs. In addition, we highlight a problem with false-positive detection and unclear significance of device-detected atrial fibrillation. [ABSTRACT FROM AUTHOR]

For the application of a digital array signal processing system with a high sampling rate and large bandwidth, and considering the constraints of limited resources (performance, volume, power consumption, weight, etc.), this paper proposes a design and implementation method of broadband digital array signal processing system based on radio frequency system on a chip. The system focuses on multi-channel synchronization under a high sampling rate and multi-channel amplitude and phase calibration under large bandwidth to form an all-digital, low-power, multi-channel, high-speed, large bandwidth hardware platform suitable for broadband digital array signal processing. Through the implementation of the Multiple-Input Multiple-Output phased-array digital beamforming algorithm, the test conducted verifies that the system has superior signal processing performance of the broadband digital array. [ABSTRACT FROM AUTHOR]

This article proposes a Distributed-control Architecture (D-CA) and an operation sequence with start-up strategies for a Digital Signal Processor (DSP)-based Solid-State Transformer (SST). Although various control techniques for SSTs have been reported in earlier studies, there is still a lack of research covering comprehensive content, including hierarchical control architectures and operation sequences with start-ups considering the implementation of DSPs. Therefore, this article addresses the following factors of SST. First, the D-CA is described for the design of the hierarchy between control boards. With the D-CA, because sub-boards are in charge of their corresponding DC-link voltage balancing control individually, the computational burden on the master board can be reduced. Second, the operation sequence of the SST system is explained based on the SST with D-CA. The step of DC-link voltage balance is considered throughout the entire operation sequence for safe driving. Furthermore, the PWM start-up strategies for a Cascade H-bridge Multilevel (CHM) converter and Dual Active Bridge (DAB) converter are proposed to prevent switching pulse errors caused by DSP operating characteristics. These start-up strategies reduce the current surges. The validity of the proposed D-CA and operation sequence with start-up strategies are verified by experimental results. [ABSTRACT FROM AUTHOR]

A new fractional-order cellular neural network (CNN) system is solved using the Adomian decomposition method (ADM) with the hyperbolic tangent activation function in this paper. The equilibrium point is analyzed in this CNN system. The dynamical behaviors are studied as well, using a phase diagram, bifurcation diagram, Lyapunov Exponent spectrum (LEs), and spectral entropy (SE) complexity algorithm. Changing the template parameters and the order values has an impact on the dynamical behaviors. The results indicate that rich dynamical properties exist in the system, such as hyperchaotic attractors, chaotic attractors, asymptotic periodic loops, complex coexisting attractors, and interesting state transition phenomena. In addition, the digital circuit implementation of this fractional-order CNN system is completed on a digital signal processing (DSP) platform, which proves the accuracy of ADM and the physical feasibility of the CNN system. The study in this paper offers a fundamental theory for the fractional-order CNN system as it applies to secure communication and image encryption. [ABSTRACT FROM AUTHOR]

Complex natural resonances (CNRs) extraction methods such as matrix pencil method (MPM), Cauchy, vector-fitting Cauchy method (VCM), or Prony's method decompose a signal in terms of frequency components and damping factors based on Baum's singularity expansion method (SEM) either in the time or frequency domain. The validation of these CNRs is accomplished through a reconstruction of the signal based on these complex poles and residues and a comparison with the input signal. Here, we perform quantitative performance metrics in order to have an evaluation of each method's hardware suitability factor before selecting a hardware platform using benchmark signals, simulations of backscattering scenarios, and experiments. [ABSTRACT FROM AUTHOR]

In this study, an FPGA(Field Programmable Gate Array)-based borehole strain measurement system was designed that makes extensive use of digital signal processing operations to replace analog circuits. Through the formidable operational capability of FPGA, the sampled data were filtered and denoised to improve the signal-to-noise ratios. Then, with the goal of not reducing observational accuracy, the signal amplification circuit was removed, the excitation voltage was reduced, and the dynamic range of the primary adjustments was expanded to 130 dB. The system's online compilation function made it more flexible to changes in measurement parameters, allowing it to adapt to various needs. In addition, the efficiency of the equipment use was enhanced. The actual observational results showed that this study's FPGA-based borehole strain measurement system had a voltage resolution higher than 1 μV. Clear solid tides were successfully recorded in low-frequency bands, and seismic wave strain was accurately recorded in high-frequency bands. The arrival times and seismic phases of the seismic waves S and P were clearly recorded, which met the requirements for geophysical field deformation observations. Therefore, the system proposed in this study is of major significance for future analyses of geophysical and crust deformation observations. [ABSTRACT FROM AUTHOR]

This paper describes the work for the radar signal processor, the core of the Cheia space surveillance radar. It presents the basic operation, the requirements and the achieved processing performance together with a description of optimizations both in terms of signal-to-noise ratio and in terms of software processing. The Cheia Radar is financed by the European Space Agency and will be used for the tracking of low Earth orbit objects and for refining the international catalogs of space objects. [ABSTRACT FROM AUTHOR]

Wideband beamforming and interference cancellation for phased array antennas requires advances in signal processing algorithms, software, and specialized hardware platforms. A high-throughput array receiver has been developed that enables communication in radio frequency interference-rich environments with field programmable gate array (FPGA)-based frequency channelization and packetization. In this study, a real-time interference mitigation algorithm was implemented on graphics processing units (GPUs) contained in the data pipeline. The key contribution is a hardware and software pipeline for subchannelized wideband array signal processing with 150 MHz instantaneous bandwidth and interference cancellation with a heterogeneous, distributed, and scaleable digital signal processing (DSP) architecture that achieves 30 dB interferer cancellation null depth in real time with a moving interference source. [ABSTRACT FROM AUTHOR]