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This work demonstrates a RISC-V vector microprocessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching switched-capacitor DC-DC (SC DC-DC) converters and adaptive clocking that generates four on-chip voltages between 0.45 and 1 V using only 1.0 V core and 1.8 V IO voltage inputs. The converters achieve high efficiency at the system level by switching simultaneously to avoid charge-sharing losses and by using an adaptive clock to maximize performance for the resulting voltage ripple. Details about the implementation of the DC-DC switches, DC-DC controller, and adaptive clock are provided, and the sources of conversion loss are analyzed based on measured results. This system pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20 ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80%-86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices.

Integrating multiple power converters on-chip improves energy efficiency of manycore architectures. Switched-capacitor (SC) dc-dc converters are compatible with conventional CMOS processes, but traditional implementations suffer from limited conversion efficiency. We propose a dynamic voltage and frequency scaling scheme with SC converters that achieves high converter efficiency by allowing the output voltage to ripple and having the processor core frequency track the ripple. Minimum core energy is achieved by hopping between different converter modes and tuning body-bias voltages. A multicore processor model based on a 28-nm technology shows conversion efficiencies of 90% along with over 25% improvement in the overall chip energy efficiency.

Emerging applications in brain-machine interface systems require high-resolution, chronic multisite cortical recordings, which cannot be obtained with existing technologies due to high power consumption, high invasiveness, or inability to transmit data wirelessly. In this paper, we describe a microsystem based on electrocorticography (ECoG) that overcomes these difficulties, enabling chronic recording and wireless transmission of neural signals from the surface of the cerebral cortex. The device is comprised of a highly flexible, high-density, polymer-based 64-channel electrode array and a flexible antenna, bonded to 2.4 mm × 2.4 mm CMOS integrated circuit (IC) that performs 64-channel acquisition, wireless power and data transmission. The IC digitizes the signal from each electrode at 1 kS/s with 1.2 μV input referred noise, and transmits the serialized data using a 1 Mb/s backscattering modulator. A dual-mode power-receiving rectifier reduces data-dependent supply ripple, enabling the integration of small decoupling capacitors on chip and eliminating the need for external components. Design techniques in the wireless and baseband circuits result in over 16× reduction in die area with a simultaneous 3× improvement in power efficiency over the state of the art. The IC consumes 225 μW and can be powered by an external reader transmitting 12 mW at 300 MHz, which is over 3× lower than IEEE and FCC regulations.

This paper provides a perspective on progress toward realization of efficient, fully integrated dc-dc conversion and regulation functionality in CMOS platforms. In providing a comparative assessment between the inductor-based and switched-capacitor approaches, the presentation reviews the salient features in effectiveness in utilization of switch technology and in use and implementation of passives. The analytical conclusions point toward the strong advantages of the switched-capacitor (SC) approach with respect to both switch utilization and much higher energy densities of capacitors versus inductors. The analysis is substantiated with a review of recently developed and published integrated dc-dc converters of both the inductor-based and SC types. © 2012 IEEE.

This brief discusses the limitation of previously published statistical decision feedback equalizer (DFE) models when residual inter-symbol interference (ISI) is present and proposes a method that overcomes this limitation. The paper presents an accurate closed-form expression for the DFE with residual ISI and additive white Gaussian noise (AWGN). The analysis is extended to 4-level pulse amplitude modulation (PAM-4) to cover serial links of current interest. The results verify that the proposed model estimates an accurate bit error rate (BER). [ABSTRACT FROM AUTHOR]

A single-output, band selecting interposer is designed to combine three identical all-digital CMOS transmitter (Tx) chips. The open-drain CMOS Txs are flip-chip connected to the primary windings of three frequency selecting transformers realized on a single PCB interposer. The secondary windings of the three transformers are connected in series and they share a single output. Across 0.4 to 4 GHz, a peak power higher than 22.9 dBm is achieved collectively by the three sub-Txs with a drain efficiency (DE) better than 25%. The peak powers/DE of the three sub-Txs are 28.6 dBm/50%, 27.4 dBm/49%, and 24.7 dBm/34%, at 0.85, 2.1, and 3 GHz, respectively. This paper further demonstrates that the band selection can be achieved via reconfiguring the CMOS inverse Class-D switching power amplifiers. As demonstrated via continuous wave and 64-quadratic-amplitude modulation, WLAN, and LTE modulation tests, the reconfigurable Tx package exhibits high power and efficiency across all supported bands. [ABSTRACT FROM AUTHOR]

This paper demonstrates a wideband CMOS all-digital polar transmitter with flip-chip connection to three high-density-interconnection PCB interposers. The interposers are designed to extract power from a CMOS open-drain inverse Class-D power amplifier core. For a wide frequency range from 0.7 to 3.5 GHz, continuous-wave output power higher than 25.5 dBm and drain efficiency (DE) above 40% are demonstrated. The low-band package achieves a peak power of 29.2 dBm at 1.1 GHz with DE of 60%, the mid-band package outputs 28.8 dBm at 1.5 GHz with DE of 56%, and the high-band package generates 26 dBm at 3 GHz with DE of 49%. The amplitude modulation (AM) is achieved by digitally modulating the switch conductance of the inverse Class-D core, and the on-chip phase modulation is achieved by digitally weighing the in-phase and quadrature bias currents in the IQ mixer. Detailed modulation tests, involving 64 quadrature amplitude modulation (QAM) and 20-MHz WLAN and LTE signals, exhibit excellent power and efficiency at 0.6, 1.2, 1.8, 2.4, 3, and 3.6 GHz. The associated specifications on spectral masks and error vector magnitudes are satisfied. [ABSTRACT FROM AUTHOR]

Various logic functions can be implemented by appropriately biasing a single seesaw relay. The seesaw relay can also be configured as a bistable latch so that a memory cell can be implemented with one relay and one access transistor. Measurements of seesaw relay switching speed are well matched to lumped-parameter modeling results. [ABSTRACT FROM AUTHOR]

Using low parasitic microsolder bumping, we hybrid integrated efficient photonic devices from different platforms with advanced 40 nm CMOS VLSI circuits to build ultra-low power silicon photonic transmitters and receivers for potential applications in high performance inter/intra-chip interconnects. We used a depletion racetrack ring modulator with improved electro-optic efficiency to allow stepper optical photo lithography for reduced fabrication complexity. Integrated with a low power cascode 2 V CMOS driver, the hybrid silicon photonic transmitter achieved better than 7 dB extinction ratio for 10 Gbps operation with a record low power consumption of 1.35 mW. A received power penalty of about 1 dB was measured for a BER of 10(-12) compared to an off-the-shelf lightwave LiNOb3 transmitter, which comes mostly from the non-perfect extinction ratio. Similarly, a Ge waveguide detector fabricated using 130 nm SOI CMOS process was integrated with low power VLSI circuits using hybrid bonding. The all CMOS hybrid silicon photonic receiver achieved sensitivity of -17 dBm for a BER of 10(-12) at 10 Gbps, consuming an ultra-low power of 3.95 mW (or 395 fJ/bit in energy efficiency). The scalable hybrid integration enables continued photonic device improvements by leveraging advanced CMOS technologies with maximum flexibility, which is critical for developing ultra-low power high performance photonic interconnects for future computing systems.

We report ultra-low-power (690fJ/bit) operation of an optical receiver consisting of a germanium-silicon waveguide detector intimately integrated with a receiver circuit and embedded in a clocked digital receiver. We show a wall-plug power efficiency of 690microW/Gbps for the photonic receiver made of a 130nm SOI CMOS Ge waveguide detector integrated to a 90nm Si CMOS receiver circuit. The hybrid CMOS photonic receiver achieved a sensitivity of -18.9dBm at 5Gbps for BER of 10(-12). Enabled by a unique low-overhead bias refresh scheme, the receiver operates without the need for DC balanced transmission. Small signal measurements of the CMOS Ge waveguide detector showed a 3dB bandwidth of 10GHz at 1V of reverse bias, indicating that further increases in transmission rate and reductions of energy-per-bit will be possible.