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Electronic system and device are vulnerable under intensive electromagnetic pulse (EMP) environment, where low noise amplifer (LNA) is a typical sensitive instance for electromagnetic energy. This work focuses on the EMP-induced damage effect of GaAs pseudomorphic high electron mobility transistor (PHEMT), which is the core part of LNA. Using the simulation softeware Sentaurus TCAD, an EMP-induced damage model of the GaAs PHEMT is established in this paper, and verified through the experimental result. It is shown that the damage position of the device under the injection EMP exists in the center area under gate terminal. Based on this model and aiming at EMP parameters and external resistances, the influence of the external conditions on the damage effect of the device is investigated. The results indicate that the damage time is related to EMP parameters obviously:1) the damage time is inversely proportional to EMP amplitude since higher power density is absorbed under a stronger EMP; 2) the damage time is in direct proportion to signal rising time since the breakdown time is postponed under EMP with a slower rising edge. Furthermore, it is found that a load resistor is able to weaken current channel which is effective in delaying the damage process, and this effect is more obvious, with load resistor connected with source terminal. It should be noted that the results are beneficial to and valuable in hardening method against EMP of semiconductor devices. It is feasible to design external circuit protection units, aiming at attenuating signal amplitude and increasing the rising time of injected pulse. Another effectual approach is to enlarge the source series resistance under the premise of the performance meeting the requirements.

As electromagnetic environment of semiconductor device and integrated circuit deteriorates increasingly, electromagnetic pulse (EMP) of device and damage phenomenon have received more and more attention. In this paper, the damage effect and mechanism of the GaN high electron mobility field effect transistor(HEMT) under EMP are investigated. A two-dimensional electro-thermal theoretical model of GaN HEMT under EMP is proposed, which includes GaN polarization effect, mobility degradation in large electric field, avalanche generation effect, and self-heating effect. The internal transient response of AlGaN/ GaN HEMT is analyzed under the EMP injected into the gate electrode, and the damage mechanism is studied. The results show that the temperature of device keeps increasing, and the rate is divided into three stages, which present a tendency of rapid-slow-sharp till burn-out. The first rapid increasing of temperature is caused by the avalanche breakdown, and then rate becomes smaller due to the decrease of electric field. As the temperature is more than 2000 K, a positive feedback is formed between the hot electron emission and temperature of device, which causes temperature to sharply increase till burn-out. The maximum values of electric field and current density are located at the cylinder surface beneath the gate around the source, which is damage prone because of heat accumulation. Finally, the dependences of the EMP damage power, P, and the absorbed energy, E, on pulse width are obtained in a nanosecond range by adopting the data analysis software. It is demonstrated that the damage power threshold decreases but the energy threshold increases slightly with the increasing of pulse-width. The proposed formulas P = 38-0.052 and E = 1.1 0.062 can estimate the HPM pulse-width dependent damage power threshold and energy threshold of AlGaN/GaN HEMT, which can provide a good prediction of device damage and a guiding significance for electromagnetic pulse resistance destruction.

The current controlled voltage source model of substrate parasitic resistance of deep sub-micron electrostatic discharge protection device is optimized by considering the effect of conductance modulation. A compact macro-model of substrate resistance is presented according to the characteristics of lightly doped bulk substrate and heavily doped substrate with a lightly doped epitaxial layer, which is scalable with the layout dimension. The experimental model parameters of devices with various spaces between source and substrate diffusion can be extracted by device simulation. The breakdown behavior of gate grounded negative-channel metal oxide semiconductor shows the effectiveness of this method. In the meantime, the simulation time-consuming of the compact model is only 7% that of the device simulation software.

A two-dimensional electrothermal model of the bipolar transistor (BJT) is established, and the transient behaviors of the BJT originally in the forward-active region are simulated with the injection of electromagnetic pulse from the base. The results show that the damage location of the BJT shifts with the amplitude of the pulse. With a low pulse amplitude, the burnout of the BJT is caused by the avalanche breakdown of the emitter-base junction, and the damage location lies in the cylindrical region of this junction. With a high pulse amplitude, the damage first occurs at the edge of the base closer to the emitter due to the second breakdown of the p-n-n+ structure composed of the base, the epitaxial layer and the substrate. The burnout time increases with pulse amplitude increasing, while the damage energy changes in a decrease-increase-decrease order with it, thus generating both a minimum value and a maximum value of the damage energy. A comparison between simulation results and experimental ones shows that the transistor model presented in the paper can not only predict the damage location in the BJT under intense electromagnetic pulses, but also obtain the damage energy.

Based on the device operation mechanism and physical model, effects of the improved hetero-material-gate (HMG) approach on deep sub-micron silicon carbide (SiC) metal-semiconductor field-effect transistor (MESFET) are analyzed. By comparing with the conventional MESFET, it is shown that the improved HMG approach induces a multi-stepped distribution of the potential in the channel, leading to an enhanced electric field at the source. Meanwhile, the position of the maximum of the channel potential is changed to the drain side compared with the dual-material-gate (DMG) device, thus the carriers in the channel are accelerated more efficiently and the variation of potential caused by drain voltage is eliminated to a certain degree, resulting in a better restraint in short-channel effect. Also, different technological parameters are designed to study the dependence of the device performance and an optimization plan is obtained, leading to a decreased sub-threshold swing. In addition, asymmetric gate structures are designed for high power application, achieving an improved distribution of the electric field at the gate edge and an enhanced breakdown voltage of the small scale device.

Combining self-heating effect, mobility degradation in high electric field and avalanche generation effect, a two-dimensional electro-thermal model of the typical silicon-based n+-p-n-n+ structure bipolar transistor induced by high power microwave is established in this paper. By analyzing the variations of device internal distributions of the electric field, the current density and the temperature with time, a detailed investigation of the damage effect and the mechanism of the bipolar transistor under the injection of 1GHz equivalent voltage signals from the base and collector is performed. The results show that temperature elevation occurs in the negative half-period and the maximum temperature falls slightly in the positive half-period when the signals are injected from the collector. Compared with the former, device damage occurs easily with the signals injected from the base. Specifically, the base-emitter junction is susceptible to damage. The damage results caused by two large-amplitude signals with initial phases of 0 and respectively indicate that the injected signal with an initial phase of is liable to cause device damage. Meanwhile, the emitter series resistance can enhance the capability of the device to withstand microwave damage effectively.

A resistometric model based on microscopic analysis of electromigration failure mechanism is built. An extraction method for failure parameters of electromigration in copper interconnects is proposed from resistometric characteristics including the slope and step height. The results show that the failure time can be considered as the time to deplete grains at the cathode line end under a given stressing current. Two dominant failure modes with resuling slit and trench voids are observed in electromigration induced failures. The resistance curve for the trench-voiding failure mode consists of two characteristic regions,i.e., a step jump and an oblique line. The grain size and the extracted critical void length are lognormally distributed with close parameters. The variation in the slop of the oblique line in resistance curve with temperature obeys an exponential law. Activation energy of approximately 0.9 eV obtained from the resisometric model is consistent with that from Black equation.

A study of the internal damage process and mechanism of the typical n+-p-n-n+ structure bipolar transistor induced by the intense electromagnetic pulse (EMP) is carried out in this paper from the variation analysis of the distribution of the electric field,the current density and the temperature. Research shows that the damage position of the bipolar transistor is different with the different magnitude of the injecting voltage,when the magnitude of the injecting voltage is low the damage will appear firstly near the collector region under the center of the emitter region,and when the magnitude of the injecting voltage is sufficiently high the damage will appear firstly at the edge of the base near the emitter due to the breakdown of the PIN structure composed of the base-epitaxial layer-collector. Adopting the data analysis software,the relation equation between the device damage power P and the pulse width T under different injecting voltage is obtained. Owing to the variety of the device damage energy,it is demonstrated that the empirical formulas of the intense electromagnetic pulse P=AT-1 (A is a constant) is modified to P=AT-1.4 for the bipolar transistor.

In this paper,based on the research of the features about high voltage and high current under electrostatic discharge(ESD),the new 3D model of 0.6 μm gate-grounded NMOS(ggNMOS) ESD protection circuit with CSMC 6S06DPDM-CT02 CMOS technology have been derived from the optimization of lattice self-heating drift/diffusion model and its thermal model; systematic study about the effect of drain contact to gate spacing(DCGS)and the source contact to gate spacing(SCGS)on the relative protection circuit robustness index(turn-on voltage,breakdown voltage,self-heating peak,etc)have been done based on this model. The simulation results show that turn-on voltage and thermal balance are not influenced by the change of DCGS and SCGS,and compared to SCGS,DCGS is more sensitive to the breakdown voltage and the self-heating peak value of protection circuit. To improve the robustness of ESD protection circuit,it is not appropriate to monotonic increase the DCGS and SCGS for the reason that the breakdown voltage cannot be increased and the self-heating peak value of devices cannot be reduced by increasing DCGS and SCGS continuously. Compared to the TLP test results of 0.5 μm and 0.6 μm CMOS,a better reflection about the trend of electrical and heating features is derived from the simulation results,and the conclusions and test results are fully consistent. The reference for sub-micrometer ggNMOS ESD protection circuit layout parameter can be provided by the study.

A stressinduced voiding model based on the NabarroHerring mechanism has been proposed. The stressinduced voiding phenomena in Cu interconnects have been studied by the FIB crosssection technique and stress modeling. The driving force for the formation of stressinduced voids has been investigated. The relationship between stressinduced voiding, temperature, stress gradient and the dominant diffusion path are discussed. The results show that stress and stress gradient reach their peak values at the top surfaces of Cu M1 lines underneath the corner of the vials where voids are observed. Stress gradient shows crucial effect on the failure spot and the voiding rate. Stress migration is basically a diffusion and nucleation process of vacancies through the main diffusion path under the force of the stress gradient. The stress gradient and the diffusion terms vary oppositely with temperature and the maximum voiding rate is reached at a medium temperature.

The Raman scattering spectra of the nitrogen doped n-SiC is studied. The theoretical line shape analysis indicates that, compared with 4H-SiC, the shift of the LO phonon-plasma coupled mode in 6H-SiC with free carrier concentration is smaller. From the electronic Raman spectra, which were obtained with laser excitation at 5145nm, there are four spectral lines in 6H-SiC and two lines in 4H-SiC, which correspond to the 1s(A1) to 1s(E) valley orbit transitions at the inequivalent k site. The explanation of the high-frequency signals of 6303 and 635 cm-1 is that they are velated with transitions at active deep level of defect. Finally, the second-order Raman features of 6H- and 4H-SiC are identified using the selection rules for second-order scattering in wurtzite structure.

Accelerated stress-migration testing under 200℃ of Cu (M1/M2) interconnects has been done for 700h. Finite element analysis and focused-ion beam techniques have been used to study the stress-induced voiding in the Cu interconnects with vias of 500 and 350nm in diameter. The voiding mechanism and the effect of via size on the stress migration have been studied. The results show that peak values of stress and stress gradient in M1 lines are reached underneath the edge of vias. The stress gradient shows crucial effect on the voiding process. The vacancies introduced by thermo-mechanical stress diffuse along Cu M1/SiN interfaces under the force of stress gradient and nucleate at the peak values of the stress gradient. The void grows faster along the length direction because the stress in M1 lines changes faster horizontally. The stress and stress gradient increase with increasing via diameter, leading to a faster voiding rate.