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Artificial Intelligence algorithms have shown performance advantages in a wide range of application domains. However, the increasing demand for hardware resources raises challenges for AI accelerator design. To alleviate this issue, the academic community has presented much research. Among these, evaluating the performance of AI algorithms on accelerators is a hot topic. However, such work usually requires a miscellaneous experimental setup configuration, and may involve repetitive tests. Instead of conducting redundant experiments with prior research, in this paper, we present a comprehensive evaluation of AI operators rather than AI algorithms in an easy-to-operate manner. We first explore common AI operators in a variety of AI algorithms with an in-depth analysis. We identify six representative operator categories. Then, we analyze their performance using roofline model. To verify our analysis, we conduct simple evaluation experiments, where several AI operators are evaluated on two NVIDIA GPUs. We observe from the evaluation results that AI operators benefit from low-precision, large-size on-chip cache and high-bandwidth off-chip memory, and sparsity processing. Based on the observations, we propose three optimization opportunities for AI accelerator design, including multiple-precision support, an efficient memory system, and sparsity processing.

Activation function is an important part of neural network. Many artificial intelligence accelerators specially design hardware component supporting for activation function. In this article, we analyze normal activation functions, study kinds of activation function hardware implementation methods, and propose a parallel look-up table based piecewise linear fitting method. In many-core AI processor, we determine the table precision by memory size, and propose the basic algorithm and detailed structural design scheme. After the design is completed, we verify its correctness and evaluate its performance. The result shows that proposed method meets the need of correctness, and can finish the parallel computation of sixteen activation function fitting results within thirteen cycles. It greatly improves the efficiency of activation function hardware design.