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This paper presents a novel structure and design of a full custom digital chip that generates the three-phase sinusoidal pulse width modulation (SPWM) waveform with variable voltage and variable frequency (VVVF) control. The voltage and frequency are simultaneously controlled with constant v/f ratio. The frequency range is from 5Hz up to 75Hz and the voltage also changes proportionally. In this way, three modes including fix, manual setting and closed loop control have been defined that provide simple implementation and high flexibility for the IC. The synchronous modulation is used (p=63) in which there are 63 pulses for every complete sinusoidal cycle. Considering the dead time between the complementary signals that reach the switches on an inverter’s leg, the result of the simulation shows the elimination of low order harmonics with value of 40 dB for each of the SPWM outputs. The method used for generating sinusoidal waveform and variable frequency generator circuit and also the approach taken for controlling amplitude and frequency simultaneously are completely novel. The chip has been designed using 0.35µm CMOS standard technology with approximately 15000 transistors on chip. The complete circuit consumes 680µm × 570µm of chip area and 48mW of power dissipation.

The conversion error of a pipelined A/D converter using inaccurate comparators is analyzed. Error bounds are established, and it is shown that the error can be compensated using simple analog circuitry combined with some digital logic. The resulting system is especially useful for fast converters in which accurate comparators would require a large chip area and large de power. Simulations are presented to verify the efficiency of the proposed error correction scheme., An analysis of the conversion errors caused by defective comparators in a pipeline analog-to-digital converter is presented. Error bounds are derived and, together with a knowledge of the pipeline converter's inherent features, used to develop error correcting algorithms that minimized hardware requirements while reducing the complexity of digital error compensation in such comparators. Computer simulation results are given to showthe efficacy of the proposed scheme.

This study presents a spread spectrum clock generator (SSCG) circuit for high‐speed applications. The proposed SSCG adopts a phased locked loop with two dual voltage‐controlled oscillators and a frequency modulation loop implemented with a novel control unit to achieve the desired spectrum‐spreading profile. The control unit consists of an analogue charge pump‐based frequency comparator that can determine the deviation of spread spectrum clock frequency from the reference frequency. Using this analogue frequency comparator simplifies the SSCG control unit and mitigates the design constraints, particularly the speed requirements of SSCG control unit. Hence, the structure becomes a suitable solution for high‐speed applications. The proposed SSCG is tailored for USB3.1 standard with −4000 to −5000 ppm down spreading at 5 GHz clock frequency and 30–33 kHz modulation frequencies. The circuit is designed in TSMC 0.18 μm 1P6M CMOS process that occupies 0.13 mm2 active area. Based on simulation results, with a 1.8 V supply, it consumes 53.46 mW. The RMS value of absolute jitter at 5 GHz output of non‐spread spectrum is 1.1 ps rms, and the EMI reduction is 22.7 dB with −5000 ppm down spread. The simulation results of the proposed system are compared with recent works. [ABSTRACT FROM AUTHOR]