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Monolithic three‐dimensional (M3D) integration advances integrated circuits by enhancing density and energy efficiency. Ferroelectric thin‐film transistors (Fe‐TFTs) attract attention for neuromorphic computing and back‐end‐of‐the‐line (BEOL) compatibility. However, M3D faces challenges like increased runtime temperatures due to limited heat dissipation, impacting system reliability. This work demonstrates the effect of temperature impact on single‐gate (SG) Fe‐TFT reliability. SG Fe‐TFTs have limitations such as read‐disturbance and small memory windows, constraining their use. To mitigate these, dual‐gate (DG) Fe‐TFTs are modeled using technology computer‐aided design, comparing their performance. Compute‐in‐memory (CIM) architectures with SG and DG Fe‐TFTs are investigated for deep neural networks (DNN) accelerators, revealing heat's detrimental effect on reliability and inference accuracy. DG Fe‐TFTs exhibit about 4.6x higher throughput than SG Fe‐TFTs. Additionally, thermal effects within the simulated M3D architecture are analyzed, noting reduced DNN accuracy to 81.11% and 67.85% for SG and DG Fe‐TFTs, respectively. Furthermore, various cooling methods and their impact on CIM system temperature are demonstrated, offering insights for efficient thermal management strategies.

Circuits possess an irregular representation. Hence, their data structure (e.g., gate-level netlists) necessitate the encoding into fixed formats like vectors. For machine learning-based tasks, such vectors are the expected format. In contrast, brain-inspired hyperdimensional computing (HDC) can process irregular data structures with its unique encoding algebra. This work is the first to propose HDC for optimized circuit encoding and learning. One advantage of HDC over conventional deep learning algorithms is that it does not require extensive training to encode a gate-level netlist into a hypervector. Furthermore, with HDC-based circuit encoding, the similarity between circuits is efficiently computed as the similarity between their hypervectors, enabling a wide range of applications, such as circuit recognition, verification, and optimization. We introduce CircuitHD, a versatile HDC-based framework for circuit encoding and learning, featuring three encoding methods, each with specific advantages. We demonstrate its effectiveness in two applications: circuit recognition and the detection of hardware intellectual property (IP) piracy, using ITC-99 and ISCAS-85 benchmarks. In circuit recognition, CircuitHD maintains a 97% accuracy, even when the designs are obfuscated using logic locking. It detects IP piracy across diverse scenarios, achieving a 97.8% precision, outperforming a state-of-the-art graph neural network approach, with a precision of merely 81%.

Abstract Advancements in AI led to the emergence of in-memory-computing architectures as a promising solution for the associated computing and memory challenges. This study introduces a novel in-memory-computing (IMC) crossbar macro utilizing a multi-level ferroelectric field-effect transistor (FeFET) cell for multi-bit multiply and accumulate (MAC) operations. The proposed 1FeFET-1R cell design stores multi-bit information while minimizing device variability effects on accuracy. Experimental validation was performed using 28 nm HKMG technology-based FeFET devices. Unlike traditional resistive memory-based analog computing, our approach leverages the electrical characteristics of stored data within the memory cell to derive MAC operation results encoded in activation time and accumulated current. Remarkably, our design achieves 96.6% accuracy for handwriting recognition and 91.5% accuracy for image classification without extra training. Furthermore, it demonstrates exceptional performance, achieving 885.4 TOPS/W–nearly double that of existing designs. This study represents the first successful implementation of an in-memory macro using a multi-state FeFET cell for complete MAC operations, preserving crossbar density without additional structural overhead.

In this article, we propose a nontraditional design of dynamic logic circuits using fully-depleted silicon-on-insulator (FDSOI) FETs. FDSOI FET allows the threshold voltage ( $V_{\text {t}}$ ) to be adjustable (i.e., low- $V_{\text {t}}$ and high- $V_{\text {t}}$ states) by using the back gate (BG) bias. Our design utilizes the front gate (FG) and BG of an FDSOI FET as the input terminals and proposes the dynamic logic gates (like NAND, NOR, AND, OR, XOR, and XNOR) and circuits (like a half-adder and full-adder). It requires fewer transistors to build dynamic logic gates and achieves high performance with low power dissipation compared to conventional dynamic logic designs. The compact industrial model of FDSOI FET (BSIM-IMG) has been used to simulate dynamic logic gates and is fully calibrated to reproduce the 14 nm FDSOI FET technology node data. Calibration is performed for both electrical characteristics and process variations. The simulation results show an average improvement in transistor count, propagation delay, power, and power-delay product (PDP) of 23.43%, 57.16%, 47.05%, and 77.29%, respectively, compared to the conventional designs. Further, our design reduces the charge-sharing effect, which affects the drivability of the dynamic logic gates. In addition, we have analyzed the impact of the process, supply voltage, and load capacitance variations on the propagation delay of the dynamic logic family in detail. The results show that these variations have a minor impact on the propagation delay of the proposed FDSOI-based dynamic logic gates compared to the conventional dynamic logic gates.

Cryogenic CMOS circuits that efficiently connect the classical domain with the quantum world are the cornerstone in bringing large-scale quantum processors to reality. The major challenges are, however, the tight power budget (in the order of milliwatts) and small latency (in the order of microseconds) requirements that such circuits inevitably must fulfill when operating at cryogenic temperatures. In-memory computing (IMC) is rapidly emerging as an attractive paradigm that holds the promise of performing computations efficiently where the data does not need to move back and forth between the CPU and the memory. Hence, it overcomes the fundamental bottleneck in classical von Neumann architectures, which provides considerable savings in power and latency. In this work, for the first time, we propose and implement an end-to-end approach that investigates SRAM-based IMC for cryogenic CMOS. To achieve that, we first characterize commercial 5 nm FinFETs from 300 K down to 10 K. Then, we employ the first cryogenic-aware industry-standard compact model for the FinFET technology (BSIM-CMG) to empower SPICE to accurately capture how cryogenic temperatures alter the electrical characteristics of transistors (e.g., threshold voltage, carrier mobility, sub-threshold slope, etc.). Our key contributions span from (1) carefully calibrating the cryogenic-aware BSIM-CMG against commercial 5 nm FinFET measurements in which SPICE simulations come with an excellent agreement with the experimental data, (2) exploring how the robustness of SRAM cells against noise (during the hold, read, and write operations) changes at extremely low temperatures, (3) investigating how the behavior of SRAM-based IMC circuits changes at 10 K compared to 300 K, and (4) modeling the error probabilities of IMC circuits that are used to calculate the Hamming distance, which is one of the essential similarity calculations to perform classifications.

This article presents a novel, simulation-based study of the long-term impact of X-ray irradiation on the ferroelectric field effect transistor (FeFET). The analysis is conducted through accurate multiphysics technology CAD (TCAD) simulations and radiation impact on the two FeFET memory states—high-voltage threshold (HVT) and low-voltage threshold (LVT)—is studied. For both the states, we investigate the deterioration of device characteristics, such as threshold voltage shift ( $\Delta V_{\text {th}}$ ) and memory window (MW) degradation, resulting from total ionizing dose (TID) exposure between 10 krad/s and 3 Mrad/s. At a dose rate of 10 krad/s, the FeFET is adequately radiation hardened for both HVT and LVT due to negligible change in MW from the baseline, unradiated case. At a dose rate of 3 Mad/s, an MW degradation of 40% is observed, and the greatest contributor is identified as the HVT state, which shows a 0.5-V increase in $\Delta V_{\text {th}}$ , compared with 0.08 V $\Delta V_{\text {th}}$ for LVT at the same dose rate. The difference in radiation responses for HVT and LVT at the same TID is investigated and attributed to the impact of the depolarization electric field ( $E_{\text {dep}}$ ) on the transport of electrons and holes. Consequently, holes form oxide traps that occupy deeper energy levels for HVT compared with LVT, which underlies the $V_{\text {th}}$ shift and MW degradation. The resultant $I_{d}$ – $V_{g}$ characteristics are in good agreement with the experimental data. Our analysis highlights that the HVT state is sensitive to TID relative to LVT.

Quantum computing can enable novel algorithms infeasible for classical computers. For example, new material synthesis and drug optimization could benefit if quantum computers offered more quantum bits (qubits). One obstacle for scaling up quantum computers is the connection between their cryogenic qubits at temperatures between a few millikelvin and a few kelvin (depending on qubit type) and the classical processing system on chip (SoC) at room temperature ($300 \,\mathrm{K}$). Through this connection, outside heat leaks to the qubits and can disrupt their state. Hence, moving the SoC into the cryogenic part eliminates this heat leakage. However, the cooling capacity is limited, requiring a low-power SoC, which, at the same time, has to classify qubit measurements under a tight time constraint. In this work, we explore for the first time if an off-the-shelf SoC is a plausible option for such a task. Our analysis starts with measurements of state-of-the-art 5-nm fin-shaped field-effect transistors (FinFETs) at 10 and $300 \,\mathrm{K}$. Then, we calibrate a transistor compact model and create two standard cell libraries, one for each temperature. We perform synthesis and physical layout of a RISC-V SoC at $300 \,\mathrm{K}$ and analyze its performance at $10 \,\mathrm{K}$. Our simulations show that the SoC at $10 \,\mathrm{K}$ is plausible but lacks the performance to process more than a few thousand qubits under the time constraint.

Abstract Fully-printed temperature sensor arrays—based on a flexible substrate and featuring a high spatial-temperature resolution—are immensely advantageous across a host of disciplines. These range from healthcare, quality and environmental monitoring to emerging technologies, such as artificial skins in soft robotics. Other noteworthy applications extend to the fields of power electronics and microelectronics, particularly thermal management for multi-core processor chips. However, the scope of temperature sensors is currently hindered by costly and complex manufacturing processes. Meanwhile, printed versions are rife with challenges pertaining to array size and sensor density. In this paper, we present a passive matrix sensor design consisting of two separate silver electrodes that sandwich one layer of sensing material, composed of poly(3,4-ethylenedioxythiophene):polystyrene sulfonate (PEDOT:PSS). This results in appreciably high sensor densities of 100 sensor pixels per cm $$^2$$ 2 for spatial-temperature readings, while a small array size is maintained. Thus, a major impediment to the expansive application of these sensors is efficiently resolved. To realize fast and accurate interpretation of the sensor data, a neural network (NN) is trained and employed for temperature predictions. This successfully accounts for potential crosstalk between adjacent sensors. The spatial-temperature resolution is investigated with a specially-printed silver micro-heater structure. Ultimately, a fairly high spatial temperature prediction accuracy of 1.22 °C is attained.

The recent renaissance in machine learning is requesting computing power at an ever-increasing rate. In order to meet this demand, tensor processing units (TPU) are becoming popular because they hold the promise to be more efficient in terms of power usage as well as throughput compared to GPUs. This is achieved by integrating a huge number of matrix-multiply units (MMU) to perform a massive amount of parallel multiply-accumulate operations. However, this causes excessive localized hot-spots. Elevated on-chip temperatures jeopardize reliability and significantly reduce the lifetime of semiconductor devices by accelerating aging defects. Therefore, it is vital to obtain accurate thermal maps of the TPU die at the design time to ensure reliability requirements during the run-time. Due to the high power density, traditional forced air convection cooling is often insufficient. Hence, liquid cooling may seem promising, but it requires substantial maintenance effort. To overcome this challenge, novel cooling concepts need to be explored. Recent advances in thermoelectric coolers (TEC), more specifically ultra thin-film superlattice thermoelectric (TE) devices, have opened new doors to combat this obstacle. To this end, finite-element (FEM) simulations enable designers to find tradeoffs between temperature and cooling cost. However, such multi-physics simulations are extremely time-consuming, which prevents designers from exploring the available design-space. In this work, we demonstrate a neural network (NN) model that captures the effects of a superlattice TEC device mounted on top of a TPU die. The additional required cooling cost is also estimated. The commercial multi-physics tool ANSYS is employed in order to obtain high resolution data towards training the NN model. Our NN model allows to speed up the design-space exploration considerably, reducing the time required to generate a single thermal map from, on average, 45 min in ANSYS to merely 70 ms with an average prediction error of 0.26°C. Our model covers a wide range of design parameters, such as convection film coefficient, power density and superlattice TEC cooling intensity. Open Source: https://github.com/ML-CAD/TPU-Thermal-Map-Prediction.git Our framework including the generated thermal image dataset and the trained neural network models are publicly available under the above link.

With the emergence of the Internet of Things (IoT), deep neural networks (DNNs) are widely used in different domains, such as computer vision, healthcare, social media, and defense. The hardware-level architecture of a DNN can be built using an in-memory computing-based design, which is loaded with the weights of a well-trained DNN model. However, such hardware-based DNN systems are vulnerable to model stealing attacks where an attacker reverse-engineers (REs) and extracts the weights of the DNN model. In this work, we propose an energy-efficient defense technique that combines a ferroelectric field effect transistor (FeFET)-based reconfigurable physically unclonable function (PUF) with an in-memory FeFET XNOR to thwart model stealing attacks. We leverage the inherent stochasticity in the FE domains to build a PUF that helps to corrupt the neural network’s (NN) weights when an adversarial attack is detected. We showcase the efficacy of the proposed defense scheme by performing experiments on graph-NNs (GNNs), a particular type of DNN. The proposed defense scheme is a first of its kind that evaluates the security of GNNs. We investigate the effect of corrupting the weights on different layers of the GNN on the accuracy degradation of the graph classification application for two specific error models of corrupting the FeFET-based PUFs and five different bioinformatics datasets. We demonstrate that our approach successfully degrades the inference accuracy of the graph classification by corrupting any layer of the GNN after a small rewrite pulse.

Self-Heating Effects (SHE) is known as one of the key reliability challenges in FinFET and beyond. Large timing guard bands are necessary, which we try to reduce. In this work, we propose operating (biasing) processors at Zero-Temperature Coefficient (ZTC) to contain (mitigate) SHE-induced delay. Operating at ZTC allows near-zero timing guard band to protect circuits against SHE. However, a trade-off is found between thermal timing guard band and performance loss from lowering the voltage.

This paper demonstrates the critical role that Ferroelectric (FE) layer thickness ( $t_{FE}$ ) plays in Negative Capacitance (NC) transistors connecting device and circuit levels together. The study is done through fully-calibrated TCAD simulations for a $14nm$ FDSOI technology node, exploring the impact of $t_{FE}$ on the figures of merit of n-type and p-type devices, voltage transfer characteristic (VTC) and noise margin of inverter as well as the speed of buffer circuits. First, we analyze the device electrical parameters (e.g., $I_{ON}$ , $SS$ , $I_{ON}/I_{OFF}$ and $C_{gg}$ ) by varying $t_{FE}$ up to the maximum level at which hysteresis in the I-V characteristic starts. Then, we analyze the deleterious impact of Negative Differential Resistance (NDR), due to the drain to gate coupling, demonstrating how it imposes an additional constraint limiting the maximum $t_{FE}$ . We show the consequences of NDR effects on the VTC and noise margin of inverter, which are essential components for constructing robust clock trees in any chip. We demonstrate how the considerable increase in the gate’s capacitance due to FE seriously degrades the circuit’s performance imposing further constraints limiting the maximum $t_{FE}$ . Further, we analyze the impact of $t_{FE}$ on the SRAM cell static performance metrics such hold noise margin (HNM), read noise margin (RNM) and write noise margin (WNM) at supply voltages of 0.7V and 0.4V. We demonstrate that the HNM and RNM in a NC-FDSOI FET based SRAM cell are higher then those of the baseline FDSOI FET based SRAM cell noise margin and further increase with $t_{FE}$ . However, the WNM in general follows a non monotonic trend w.r.t $t_{FE}$ , and the trend also depends on the supply voltage. Finally, we optimize the design of the SRAM cell considering overall performance metrics. All in all, our analysis provides guidance for device and circuit designers to select the optimal FE thickness for NCFETs in which hysteresis-free operations, reliability, and performance are optimized.

This is the first work to investigate the impact that Negative Capacitance Field-Effect Transistor (NCFET) brings on the efficiency and accuracy of future Neural Networks (NN). NCFET is at the forefront of emerging technologies, especially after it has become compatible with the existing fabrication process of CMOS. Neural Network inference accelerators are becoming ubiquitous in modern SoCs and there is an ever-increasing demand for tighter and tighter throughput constraints and lower energy consumption. To explore the benefits that NCFET brings to NN inference regarding frequency, energy, and accuracy, we investigate different configurations of the multiply-add (MADD) circuit, which is the core computational unit in any NN accelerator. We demonstrate that, compared to the baseline 7nm FinFET technology, its negative capacitance counterpart reduces the energy by 55%, without any frequency reduction. In addition, it enables leveraging higher computational precision, which results to a considerable improvement in the inference accuracy. Importantly, the achieved accuracy improvement comes also together with a significant energy reduction and without any loss in frequency.

Monolithic 3D (M3D) integration reduces the wire length, which eventually improves energy efficiency and performance compared to 2D integration. However, 3D integration inevitably causes higher on-chip temperature compared to 2D integration due to the increased power density as well as worse heat dissipation. The high on-chip temperature may offset the benefits of the M3D microprocessors due to the following reasons: 1) high on-chip temperature increases leakage power, which degrades energy efficiency. 2) the actual clock frequency is limited at run-time by frequent dynamic thermal management (DTM) invocations. In this paper, for the first time, we explore the thermal feasibility (whether it is possible to achieve high energy efficiency and performance without exceeding threshold temperature) of the M3D microprocessors depending on cooling solutions. For the thermal feasibility study, we construct an integrated framework to investigate the thermal behaviors and thermal feasibility of different types of microprocessors (M3D, 2D, and through-silicon-via based 3D (TSV-3D)) with different cooling solutions. Our thermal-aware evaluation results show that the best configuration of the M3D microprocessors reduces average energy consumption by 27.6% compared to the 2D microprocessor at an iso-frequency (4.0GHz). In addition, at the highest clock frequencies satisfying both design and thermal constraints, the best configuration of the M3D microprocessors improves average system performance by 25.1% and 26.0% compared to the 2D and TSV-3D microprocessors, respectively.

Today, more and more commodity hardware devices are used in safety-critical applications, such as advanced driver assistance systems in automotive. These applications demand very high reliability of electronic components even in adverse environmental conditions, such as high temperatures. Ensuring the reliability of microelectronic components is a major challenge at these high temperatures. The computing systems of these applications rely on DRAMs as working memory, which are built upon bit cells that store charges in capacitors. These commodity DRAMs are optimized for cost per bit and not for high reliability. Thus, very high temperatures impose an enormous challenge for commodity DRAMs as the data retention time and reliability decrease largely, affecting the data correctness. Data correctness can be ensured up to certain temperatures by increasing the refresh rate to counterbalance the retention time reduction. However, this severely degrades the access latencies and the usable DRAM bandwidth. To overcome these limitations, we present for the first time a Thermoelectric Cooling (TEC) solution for commodity DRAMs in harsh-environments, such as automotive. Our TEC solution enables the use of commodity off-the-shelf DRAMs in safety-critical applications by reducing the temperature conditions to a range where they can operate reliably. This TEC solution is applied a posteriori to the DRAM chips without using high-cost package solutions. Thus, it maintains the low-cost targets of such devices, improves the reliability, and at the same time, counterbalances the adverse effects of increasing the refresh rate. To quantitatively evaluate the benefits of TEC on commodity DRAMs in harsh-environments, we performed system-level evaluations with several applications backed up by the measured data on commodity DRAMs. Our experimental results, using accurate multi-physics simulations that employ finite element method, demonstrate that the TEC-based cooling ensures that the maximum temperature of all DRAM chips is always below 85°C despite that the original on-chip temperature (i.e., in the absence of our TEC based cooling) goes beyond 120°C.

The separation of computing units and memory in the computer architecture mandates energy-intensive data transfers creating the von Neumann bottleneck. This bottleneck is exposed at the application level by the steady growth of IoT and data-centric deep learning algorithms demanding extraordinary throughput. On the hardware level, analog Processing-in-Memory (PiM) schemes are used to build platforms that eliminate the compute-memory gap to overcome the von Neumann bottleneck. PiM can be efficiently implemented with ferroelectric transistors (FeFET), an emerging non-volatile memory technology. However, PiM and FeFET are heavily impacted by process variation, especially in sub 14 nm technology nodes, reducing the reliability and thus inducing errors. Brain-inspired Hyperdimensional Computing (HDC) is robust against such errors. Further, it is able to learn from very little data cutting energy-intensive transfers. Hence, HDC, in combination with PiM, tackles the von Neumann bottleneck at both levels. Nevertheless, the analog nature of PiM schemes necessitates the conversion of results to digital, which is often not considered. Yet, the conversion introduces large overheads and diminishes the PiM efficiency. In this paper, we propose an all-in-memory scheme performing computation and conversion at once, utilizing programmable FeFET synapses to build the comparator used for the conversion. Our experimental setup is first calibrated against Intel 14 nm FinFET technology for both transistor electrical characteristics and variability. Then, a physics-based model of ferroelectric is included to realize the Fe-FinFETs. Using this setup, we analyze the circuit’s susceptibility to process variation, derive a comprehensive error probability model, and inject it into the inference algorithm of HDC. The robustness of HDC against noise and errors is able to withstand the high error probabilities with a loss of merely 0.3% inference accuracy.

In this work, we investigate the impact of Si-SiO2 interface traps on the performance of negative capacitance transistor, which is a promising emerging technology that aims at achieving a steep sub-threshold slope. Interface traps induced degradation is well known to be one of the major concerns when it comes to reliability. We focus on investigating the impact of different interface trap concentrations on the figures of merit of both the devices and circuits. Our investigation is performed using TCAD models, which are well calibrated against 14nm production quality FinFETs. This allows accurate analysis and modeling of the impact of NC on the electric field across the SiO2 layer. Then, the industry compact model of FinFET (BSIM-CMG) is fully calibrated to reproduce TCAD data. In addition, a physics-based NC model is integrated and solved self-consistently within the BSIM-CMG model in which TCAD data of NC-pFinFETs and NC-nFinFETs are also well matched. This allows studying how interface traps induced degradation can impact circuits. Our results demonstrate that the amplified electric field across the SiO2 layer within NC-pFinFET due to NC effect leads to a higher interface trap concentration. This, in turn, results in a larger degradation in the NC-pFinFET compared to its pFinFET counterpart - when both of these devices are operated at the same nominal supply voltage of the 14nm node. However, at the same interface trap concentration, the NC-pFinFET always exhibits less degradation than the baseline pFinFET due to the former's better electrostatic integrity on account of voltage amplification effect. With respect to circuits, we study both Ring Oscillator (RO) and 6-T SRAM cell circuits. We show how the frequency of RO in the case of NC-FinFET is always less impacted by interface trap induced degradations compared to its counterpart FinFET-based RO. For 6-T SRAM cell, we demonstrate how the key reliability metrics such as hold noise margin, read noise margin, and write noise margin are also less impacted by the induced degradations in NC-FinFET SRAMs compared to the baseline FinFET SRAMs. This is because of the much better electrostatic integrity that NC provides.

Leveraging the inherent error tolerance of a vast number of application domains that are rapidly growing, approximate computing arises as a design alternative to improve the efficiency of our computing systems by trading accuracy for energy savings. However, the requirement for computational accuracy is not fixed. Controlling the applied level of approximation dynamically at runtime is a key to effectively optimize energy, while still containing and bounding the induced errors at runtime. In this paper, we propose and implement an automatic and circuit independent design framework that generates approximate circuits with dynamically reconfigurable accuracy at runtime. The generated circuits feature varying accuracy levels, supporting also accurate execution. Extensive experimental evaluation, using industry strength flow and circuits, demonstrates that our generated approximate circuits improve the energy by up to 41% for 2% error bound and by 17.5% on average under a pessimistic scenario that assumes full accuracy requirement in the 33% of the runtime. To demonstrate further the efficiency of our framework, we considered two state-of-the-art technology libraries which are a 7nm conventional FinFET and an emerging technology that boosts performance at a high cost of increased dynamic power.

This paper reports a novel approach that uses transistor aging in an integrated circuit (IC) to detect hardware Trojans. When a transistor is aged, it results in delays along several paths of the IC. This increase in delay results in timing violations that reveal as timing errors at the output of the IC during its operation. We present experiments using aging-aware standard cell libraries to illustrate the usefulness of the technique in detecting hardware Trojans. Combining IC aging with over-clocking produces a pattern of bit errors at the IC output by the induced timing violations. We use machine learning to learn the bit error distribution at the output of a clean IC. We differentiate the divergence in the pattern of bit errors because of a Trojan in the IC from this baseline distribution. We simulate the golden IC and show robustness to IC-to-IC manufacturing variations. The approach is effective and can detect a Trojan even if we place it far off the critical paths. Results on benchmarks from the Trust-hub show a detection accuracy of ≥ 99%.

Negative capacitance field-effect transistor (NCFET) addresses one of the key fundamental limits in technology scaling, akin to the non-scalable Boltzmann factor, by offering a sub-threshold swing below 60 mV/decade. In this paper, we investigate how the NCFET technology can open the doors not only for the continuation of Moore's law, which is approaching its end, but also for reviving Dennard's scaling, which stopped more than a decade ago. We study NCFET for the 7-nm FinFET technology node, from physics to processors and demonstrate that prior trends in processor design with respect to voltage and frequency can be revived with the NCFET technology. Our work focuses on answering the following three questions towards drawing the impact of NCFET technology on computing efficiency: In how far NCFET technology will enable processors: 1) to operate at higher frequencies without increasing voltage; 2) to operate at higher frequencies without increasing power density, which is substantial, because maintaining on-chip power densities under tight constraints due to limited cooling capabilities is inevitable; and 3) to operate at lower voltages, while still fulfilling performance requirements, which is substantial for the emerging Internet of Things, in which available power budgets for such devices are typically very restricted.