Search

Nowadays, two groundbreaking factors are emerging in neural networks. Firstly, there is the RISC-V open instruction set architecture (ISA) that allows a seamless implementation of custom instruction sets. Secondly, there are several novel formats for real number arithmetic. In this work, we combined these two key aspects using the very promising posit format, developing a light Posit Processing Unit. We present an extension of the base RISC-V ISA that allows the conversion between 8 or 16-bit posits and 32-bit IEEE Floats or fixed point formats in order to offer a compressed representation of real numbers with little-to-none accuracy degradation. Then we elaborate on the hardware and software toolchain integration of our PPU inside the Ariane RISC-V core and its toolchain, showing how little it impacts in terms of circuit complexity and power consumption. Indeed, only 0.36% of the circuit is devoted to the PPU while the full RISC-V core occupies the 33% of the overall circuit complexity. Finally we present the impact of our PPU-light on a deep neural network task, reporting speedups up to 10 on sample inference processing time.

Subgraph enumeration is important for many applications such as network motif discovery, community detection, and frequent subgraph mining. To accelerate the execution, recent works utilize graphics processing units (GPUs) to parallelize subgraph enumeration. The performances of these parallel schemes are dominated by the set intersection operations which account for up to $95\%$ of the total processing time. (Un)surprisingly, a significant portion (as high as $99\%$) of these operations is actually redundant, i.e., the same set of vertices is repeatedly encountered and evaluated. Therefore, in this paper, we seek to salvage and recycle the results of such operations to avoid repeated computation. Our solution consists of two phases. In the first phase, we generate a reusable plan that determines the opportunity for reuse. The plan is based on a novel reuse discovery mechanism that can identify available results to prevent redundant computation. In the second phase, the plan is executed to produce the subgraph enumeration results. This processing is based on a newly designed reusable parallel search strategy that can efficiently maintain and retrieve the results of set intersection operations. Our implementation on GPUs shows that our approach can achieve up to $5$ times speedups compared with the state-of-the-art GPU solutions.

With the development of computer architecture, even for embedded systems, GPU devices can be integrated, providing outstanding performance and energy efficiency to meet the requirements of different industries, applications, and deployment environments. Data analytics is an important application scenario for embedded systems. Unfortunately, due to the limitation of the capacity of the embedded device, the scale of problems handled by the embedded system is limited. In this paper, we propose a novel data analytics method, called G-TADOC, for efficient text analytics directly on compression on embedded GPU systems. A large amount of data can be compressed and stored in embedded systems, and can be processed directly in the compressed state, which greatly enhances the processing capabilities of the systems. Particularly, G-TADOC has three innovations. First, a novel fine-grained thread-level workload scheduling strategy for GPU threads has been developed, which partitions heavily-dependent loads adaptively in a fine-grained manner. Second, a GPU thread-safe memory pool has been developed to handle inconsistency with low synchronization overheads. Third, a sequence-support strategy is provided to maintain high GPU parallelism while ensuring sequence information for lossless compression. Moreover, G-TADOC involves special optimizations for embedded GPUs, such as utilizing the CPU-GPU shared unified memory. Experiments show that G-TADOC provides 13.2× average speedup compared to the state-of-the-art TADOC. G-TADOC also improves performance-per-cost by 2.6× and energy efficiency by 32.5× over TADOC.

As the reduced instruction set computing (RISC) processors are widely used nowadays, to meet the requirement that no secret instructions be included in the processor ISA or implemented in the processor micro-architecture, a consistency testing approach capable of revealing any possible dark instructions (i.e., executable instructions without clear definitions) in RISC processors has been proposed and comes in three phases. During the generation phase, based on the instruction set encoding rules, all the undefined instructions are generated. Even with a smaller test space, this step guarantees the test coverage needed to reveal all possible dark instructions that exist. In the next phase, all the undefined instructions obtained from the previous phase are executed on the processor under test, following some persistence strategies; any instruction exhibiting usual execution result will be deemed suspicious and recorded so. During the last analysis phase, each of those recorded suspicious instructions will be checked and analyzed to decide whether it truly constitutes a dark instruction. We have applied the proposed testing model and strategy to several RISC processors and found that all of them have a few dark instructions previously unknown. The potential vulnerabilities introduced by these dark instructions have thus been evaluated and exposed.

In a shared-memory multicore system, the intrinsic irregular data structure of graphs leads to poor cache utilization, and therefore deteriorates the performance of graph analytics. To address the problem, prior works have proposed a variety of lightweight reordering methods with focus on the optimization of cache locality. However, there is a compromise between cache locality and workload balance. Little insight has been devoted into the issue of workload imbalance for the underlying multicore system, which degrades the effectiveness of parallel graph processing. In this work, a measurement approach is proposed to quantify the imbalance incurred by the concentration of vertices. Inspired by it, we present Cache-aware Reorder (Corder) , a lightweight reordering method exploiting the cache hierarchy of multicore systems. At the shared-memory level, Corder promotes even distribution of computation loads amongst multicores. At the private-cache level, Corder facilitates cache efficiency by applying further refinement to local vertex order. Comprehensive performance evaluation of Corder is conducted on various graph applications and datasets. Experimental results show that Corder yields speedup of up to $2.59\times$ 2 . 59 × and on average $1.45\times$ 1 . 45 × , which significantly outperforms existing lightweight reordering methods. To identify the root causes of performance boost delivered by Corder, multicore activities are investigated in terms of thread behavior, cache efficiency, and memory utilization. Statistical analysis demonstrates that the issue of imbalanced thread execution time dominates other factors in determining the overall graph processing time. Moreover, Corder achieves remarkable advantages in cross-platform scalability and reordering overhead.

Moving toward exascale computing, the size of data stored and accessed by applications is ever increasing. However, traditional disk-based storage has not seen improvements that keep up with the explosion of data volume or the speed of processors. Multiple levels of non-volatile storage devices are being added to handle bursty I/O, however, moving data across the storage hierarchy can take longer than the data generation or analysis. Asynchronous I/O can reduce the impact of I/O latency as it allows applications to schedule I/O early and to check their status later. I/O is thus overlapped with application communication or computation or both, effectively hiding some or all of the I/O latency. POSIX and MPI-I/O provide asynchronous read and write operations, but lack the support for non-data operations such as file open and close. Users also have to manually manage data dependencies and use low-level byte offsets, which requires significant effort and expertise to adopt. In this article, we present an asynchronous I/O framework that supports all types of I/O operations, manages data dependencies transparently and automatically, provides implicit and explicit modes for application flexibility, and error information retrieval. We implemented these techniques in HDF5. Our evaluation of several benchmarks and application workloads demonstrates it effectiveness on hiding the I/O cost from the application.

Post-quantum cryptography was proposed in the past years due to the foreseeable emergence of quantum computers that are able to break the conventional public key cryptosystems at acceptable costs. However, post-quantum schemes are usually less efficient than conventional ones, which makes them less practical in scenarios with limited resources or high concurrency. Server-side applications always feature multiple users, therefore requiring efficient execution of batch tasks. GPU is intrinsically well-suited to batch tasks owing to its SIMD/SIMT execution fashion, so it naturally helps to achieve high performance. However, a naive GPU-based implementation cannot make the best use of hardware resources of the GPU regardless of task loads. In this article, we propose SIMD parallelization paradigms for fine-grained GPU implementations and then apply them to a post-quantum key encapsulation algorithm called NewHope, where we carefully design every module, especially NTT and inverse NTT, to fit into the SIMD parallelization paradigms. In addition, we employ multi-streaming to improve performance in user's perspective. Finally, our evaluations are made on two testbeds with GPU accelerators NVIDIA GeForce MX150 and GeForce GTX 1650, respectively. The experimental results show that the fine-grained implementations save up to 98 percent latency at low task loads, and their throughputs increase by up to 86 percent at high task loads, when compared with the naive ones in kernel's perspective, and the multi-streaming implementations greatly reduce the latency overhead percentage at high task loads by up to 86 percent, when compared with the fine-grained implementation in user's perspective. Moreover, our fine-grained implementation and multi-streaming implementation are respectively 51.5 and 45.5 percent faster than Gupta et al. 's implementations when compared with it under reasonable assumptions. Furthermore, as lattice-based post-quantum schemes have similar operations, our proposal also easily applies to other lattice-based post-quantum schemes.

The RISC-V instruction set architecture open licensing policy has spawned a hive of development activity, making a range of implementations publicly available. The environments in which RISC-V operates have expanded correspondingly, driving the need for a generalized approach to evaluating the reliability of RISC-V implementations under adverse operating conditions or after normal wear-out periods. Fault injection (FI) refers to the process of changing the state of registers or wires, either permanently or momentarily, and then observing execution behavior. The analysis provides insight into the development of countermeasures that protect against the leakage or corruption of sensitive information which might occur because of unexpected execution behavior. In this paper, we develop a hardware-software co-design architecture that enables fast, configurable fault emulation and utilize it for information leakage and data corruption analysis. Modern System-on-chip FPGAs enable building an evaluation platform where control elements run on a processor(s) (PS) simultaneously with the target design running in the programmable logic (PL). Software components of the FI system introduce faults and report execution behavior. A pair of RISC-V FI-instrumented implementations are created and configured to execute the Advanced Encryption Standard and Twister algorithms. Key and plaintext information leakage and degraded pseudo-random sequences are both observed in the output for a subset of the emulated faults.

The depthwise separable convolution is commonly seen in convolutional neural networks (CNNs), and is widely used to reduce the computation overhead of a standard multi-channel 2D convolution. Existing implementations of depthwise separable convolutions target accelerating model training with large batch sizes with a large number of samples to be processed at once. Such approaches are inadequate for small-batch-sized model training and the typical scenario of model inference where the model takes in a few samples at once. This article aims to bridge the gap of optimizing depthwise separable convolutions by targeting the GPU architecture. We achieve this by designing two novel algorithms to improve the column and row reuse of the convolution operation to reduce the number of memory operations performed on the width and the height dimensions of the 2D convolution. Our approach employs a dynamic tile size scheme to adaptively distribute the computational data across GPU threads to improve GPU utilization and to hide the memory access latency. We apply our approach on two GPU platforms: an NVIDIA RTX 2080Ti GPU and an embedded NVIDIA Jetson AGX Xavier GPU, and two data types: 32-bit floating point (FP32) and 8-bit integer (INT8). We compared our approach against cuDNN that is heavily tuned for the NVIDIA GPU architecture. Experimental results show that our approach delivers over $2\times$ 2 × (up to $3\times$ 3 × ) performance improvement over cuDNN. We show that, when using a moderate batch size, our approach averagely reduces the end-to-end training time of MobileNet and EfficientNet by 9.7 and 7.3 percent respectively, and reduces the end-to-end inference time of MobileNet and EfficientNet by 12.2 and 11.6 percent respectively.

Recently, FPGA has been utilized to accelerate the Random Forest prediction process to meet the speed requirements of real-time tasks. However, the existing accelerators impose restrictions on the parameters of the accelerated model. The accelerators have to be reconfigured to adapt to a model whose parameters exceed the predefined restrictions. When these accelerators are applied in the scenarios where the model updates or switches frequently, non-trivial time overhead and maintenance costs may be introduced. To solve the above problem, a flexible accelerator RF-RISA, Random Forest Reduced Instruction Set Accelerator, is presented in this paper. Compared with the existing accelerators, RF-RISA eliminates all the restrictions by decoupling the model parameters from its hardware implementation. Specifically, RF-RISA encodes the information of the model into a group of instructions, then the instructions are stored in the memory rather than are hardcoded in the hardware. Meanwhile, a mapping scheme is proposed to map the instructions into the memory dynamically. Finally, a new hardware architecture is designed to support the pipelined computing. The theoretical analysis and experimental results show that the proposed RF-RISA can accelerate a wide range of RF models without reconfiguration. At the same time, it can achieve the same throughput as the state-of-the-art.

Large scale quantum computers will break classical public-key cryptography protocols by quantum algorithms such as Shor’s algorithm. Hence, designing quantum-safe cryptosystems to replace current classical algorithms is crucial. Luckily there are some post-quantum candidates that are assumed to be resistant against future attacks from quantum computers, and NIST is considering standardizing them. Among these candidates, lattice-based cryptography sounds more interesting than others due to the performance results as well as confidence in the security. There are few works in the literature evaluating the performance of lattice-based cryptography in hardware. In this paper, we focus on Cryptographic Suite for Algebraic Lattices (CRYSTALS) key exchange mechanisms known as Kyber and provide an instruction-set hardware architecture and implement on Xilinx Artix-7 FPGA for performance evaluation and testing. Our proposed architecture provides an efficient and high-performance set of components to perform polynomial sampling, number-theoretic transform (NTT), and point-wise multiplication to speed up lattice-based post-quantum cryptography (PQC). This architecture implemented on ASIC outperforms state-of-the-art implementations.

Data-parallel applications, such as data analytics, machine learning, and scientific computing, are placing an ever-growing demand on floating-point operations per second on emerging systems. With increasing integration density, the quest for energy efficiency becomes the number one design concern. While dedicated accelerators provide high energy efficiency, they are over-specialized and hard to adjust to algorithmic changes. We propose an architectural concept that tackles the issues of achieving extreme energy efficiency while still maintaining high flexibility as a general-purpose compute engine. The key idea is to pair a tiny 10kGE (kilo gate equivalent) control core, called Snitch, with a double-precision floating-point unit (FPU) to adjust the compute to control ratio. While traditionally minimizing non-floating-point unit (FPU) area and achieving high floating-point utilization has been a trade-off, with Snitch, we achieve them both, by enhancing the ISA with two minimally intrusive extensions: stream semantic registers (SSR) and a floating-point repetition instruction (FREP). SSRs allow the core to implicitly encode load/store instructions as register reads/writes, eliding many explicit memory instructions. The FREP extension decouples the floating-point and integer pipeline by sequencing instructions from a micro-loop buffer. These ISA extensions significantly reduce the pressure on the core and free it up for other tasks, making Snitch and FPU effectively dual-issue at a minimal incremental cost of 3.2 percent. The two low overhead ISA extensions make Snitch more flexible than a contemporary vector processor lane, achieving a $2\times$ 2 × energy-efficiency improvement. We have evaluated the proposed core and ISA extensions on an octa-core cluster in 22 nm technology. We achieve more than $6\times$ 6 × multi-core speed-up and a $3.5\times$ 3 . 5 × gain in energy efficiency on several parallel microkernels.

In their 2018 Turing Award lecture and 2019 paper, John Hennessy and David Patterson reviewed computer architecture progress since the 1960s. They projected a second golden age akin to the first, approximately 1986–1996, when new instruction set architectures, almost all reduced instruction set computers (RISCs), revolutionized the industry, eliminated most minicomputer vendors, rivaled mainframes, and began a takeover of supercomputing. The C language and derivatives came to pervade systems programming, whereas Unix derivatives came to run many servers, desktops, and smartphones. Such outcomes were not inevitable but depended on evolutionary interactions of computer architecture and languages, industry dynamics, and sometimes random coincidences.

It was a different computing world in the late 1980s. Many if not most researchers in the computer architecture area had become convinced that complex instruction sets such as the Intel x86 were doomed in light of the many advantages promised by reduced instruction set architecture publications. There were many voices within Intel urging upper management to abandon x86 and get started on some alternative. Even engineers who had worked on Intel's then-flagship 486 were expressing serious reservations about whether the x86 architecture could be “dragged further up the hill” to be, if not directly competitive with emerging RISC designs, at least close enough for x86 to remain profitable.

Improving the latency hiding ability is important for GPU performance. Although existing works, which mainly target on either improving thread level parallelism or optimizing memory hierarchy, are effective at improving GPUs’ latency hiding ability, warps are still blocked after executing long latency operations, reducing the number of schedulable warps. This article revisits the recently proposed non-blocking execution for GPUs to improve the latency hiding ability of GPUs. With non-blocking execution, instructions from warps blocked by long latency operations can be pre-executed to make full use of GPU resources. However, we find that the state-of-the-art non-blocking GPU architecture gains limited performance improvement. Through in-depth analysis, we observe that the poor performance is largely due to inefficient pre-execution state management, duplicate instruction extraction, frequent early eviction and severe resource congestion. To make non-blocking execution actually useful for GPUs and minimize hardware overheads, we carefully redesign the non-blocking architecture for GPUs based on our analysis and propose MIPSGPU . Our evaluations show that MIPSGPU , relative to the state-of-the-art non-blocking GPU architecture, improves performance of memory intensive applications by 19.05 percent, and reduces memory to SM traffics by 14 percent.

In the 70s of the last century, during the active development of electronic computing technology, the development of computing systems went in two ways: high-performance computing systems (OS); narrow-profile computing systems. In fact, high-performance systems are universal operating systems whose task is to maximize the high speed of computing per unit of time. Narrow-profile operating systems aimed at performing certain types of tasks, where just the speed of calculations did not matter so much, and other technical characteristics were obtained for the first roles: energy efficiency, product ergonomics, the need to perform only certain types of tasks, and so on. Specifically, the type of tasks has become decisive in terms of the architectural implementation of the OS. Let's consider the RISC-V architecture to assess the prospects of its introduction into the mass segment. В 70-х роках минулого сторіччя, під час активного розвитку електронно-обчислювальної техніки, розвиток обчислювальних систем пішов двома шляхами: високопродуктивні обчислювальні системи (ОС); вузькопрофільні обчислювальні системи. Фактично, високопродуктивні системи – це універсальні ОС завданням яких є максимальна висока швидкість обчислень за одиницю часу. Вузькопрофільні ОС ставили за мету виконання певних типів завдань, де якраз швидкість обчислень не мала такого значення, а на перші ролі виходили інші технічні характеристики: енергоефективність, ергономіка виробу, необхідність виконання тільки певного роду завдань та інше. Саме вид завдань став вирішальним з точки зору архітектурної реалізації ОС. Розглянемо архітектуру RISC-V з метою оцінки перспективності впровадження її до масового сегменту.

OpenMP has become a reference standard for the design of parallel applications. This standard is evolving very fast, thus offering ever new opportunities to the application programmers. However, OpenMP runtime environments are often not fully aligned to the actual requirements imposed by the evolution of such standard. Among the main lacks, we find: (a) a limited capability to effectively cope with task priorities, and (b) the inadequacy in guaranteeing core properties while processing tasks such as the so called extit{work-conservativeness}---the ability of the OpenMP runtime environment to fully exploit the underlying multi-processor/multi-core machine through the avoidance of thread-blocking phases. In this article we present the design of extensions to the GNU OpenMP ({ t GOMP}) implementation, integrated into { t gcc}, which allow the effective management of tasks and their priorities. Our proposal is based on a user-space library---modularly combined with the one already offered by { t GOMP}---and an external kernel-level Linux module---offering the opportunity to exploit raising hardware facilities for the purpose of task/priority management. We also provide experimental results showing the effectiveness of our proposal, achieved by running either OpenMP common benchmarks or a new benchmark application (named {sc Hashtag-Text}) that we explicitly devised in order to stress the OpenMP runtime environment in relation to the above-mentioned task/priority management aspects.

For most Internet-of-Things (IoT) applications, embedded processors typically execute lightweight tasks such as sensing and communication. The typical IoT program senses some information and sends them via a channel, usually a wireless channel with an RF circuit. These IoT nodes often require a system with networking capabilities and a low-power harvester implementation. This brief presents a sub- $\mu \text{W}$ 8-bit processor which is suitable for such IoT applications. The processor implements the Open8 Instruction Set Architecture (ISA) with an 8-bit datapath and 16-bit bus addressing. The chip contains the processor and a 4-KB of Static Random-Access-Memory (SRAM), and is fabricated by the 65-nm Silicon-On-Thin-Box (SOTB) process. The SOTB process is one of the Fully-Depleted Silicon-On-Insulator (FD-SOI) technology. Hence, the ability to control biasing voltages is one of its key advantages to achieve low-power. The experimental results show that the power consumption at the reverse-body bias can reach down to 50-nW with 0.5-V supply voltage and 32-KHz operating clock frequency. The completed microcontroller consists of the Open8 processor, 32-KB of Read-Only-Memory (ROM), 4-KB of SRAM, Serial Peripheral Interface (SPI), SPI programmer, debug module, General-Purpose In-Outs (GPIOs), and UART. The system was tested using an XC7A100T Xilinx Field-Programmable Gate Array (FPGA); it yielded 1.8% of the total FPGA utilization.

Worst-case dI/dt voltage noise is typically characterized post-silicon using direct voltage measurements through either on-package measurement points or on-chip dedicated circuitry. These approaches consume expensive pad resources or suffer from design-time and run-time overheads. This work proposes an alternative non-intrusive, zero-overhead approach for post-silicon dI/dt voltage noise characterization based on sensing CPU electromagnetic emanations using an antenna and a spectrum analyzer. This approach is based on the observation that high amplitude electromagnetic emanations are correlated with high resonance-induced voltage-noise. This approach enables essential Power-Delivery Network characterization tasks such as: a) obtaining the first-order resonance-frequency of the Power-Delivery LC-tank network, and b) automatically generating voltage noise (dI/dt) stress tests with a genetic-algorithm that is driven by the electromagnetic signal amplitude. The generality of the approach is established by successfully applying it to four different CPUs: two ARM multi-core mobile CPU clusters hosted on a big.LITTLE configuration, one x86-64 AMD desktop CPU and one ARM 64bit 8-core clustered architecture server CPU. The efficacy of the proposed methodology is validated through VMIN and direct voltage-noise measurements. Furthermore, the effectiveness of the EM approach to generate dI/dt viruses that have higher VMIN that conventional workloads is demonstrated with a dynamic-voltage-scaling (DVS) governor that scales the voltage according to the VMIN of the EM generated dI/dt viruses for various core-allocations scenarios. For a 62-hour test with a varying workload mix and core allocations, this governor provides safe below nominal-voltage operation.

This article presents approaches for performance improvements into two large and well-known open source projects, Git and GNU Compiler Collection, using parallel programming. We share the difficulties faced and the strategies used, concluding with a set of lessons learned that are useful to similar parallelization processes.

Sparse triangular solves (SpTRSVs) are widely used in linear algebra domains, and several GPU-based SpTRSV algorithms have been developed. Synchronization-free SpTRSVs, due to their short preprocessing time and high performance, are currently the most popular SpTRSV algorithms. However, we observe that the performance of those SpTRSV algorithms on different matrices can vary greatly by 845 times. Our further studies show that when the average number of components per level is high and the average number of nonzero elements per row is low, those SpTRSVs exhibit extremely low performance. The reason is that, they use a warp on the GPU to process a row in sparse matrices, and such warp-level designs have severe underutilization of the GPU. To solve this problem, we propose YuenyeungSpTRSV, a thread-level and wrap-level fusion synchronization-free SpTRSV algorithm, which handles the rows with a large number of nonzero elements at warp-level while the rows with a low number of nonzero elements at thread-level. Particularly, YuenyeungSpTRSV has three novel features. First, unlike the previous studies, YuenyeungSpTRSV does not need long preprocessing time to calculate levels. Second, YuenyeungSpTRSV exhibits high performance on matrices that previous SpTRSVs cannot handle efficiently. Third, YuenyeungSpTRSV's optimization does not rely on the specific sparse matrix storage format. Instead, it can achieve very good performance on the most popular sparse matrix storage, compressed sparse row (CSR) format, and thus users do not need to conduct format conversion. We evaluate YuenyeungSpTRSV with 245 matrices from the Florida Sparse Matrix Collection on four GPU platforms, and experiments show that our YuenyeungSpTRSV exhibits 7.14 GFLOPS/s, which is 5.98x speedup over the state-of-the-art synchronization-free SpTRSV algorithm, and 4.83x speedup over the SpTRSV in cuSPARSE.

The increasingly complex AC/DC network as a result of the massive integration of wind farms manifests the significance of a comprehensive transient study. In this work, the wind turbine (WT) and the DC grid are modeled in detail for the electromagnetic transient (EMT) simulation to maximize its fidelity, whilst the AC grid transient stability is analyzed by dynamic simulation (DS). An interactive EMT-DS interface is thus introduced to enable their concurrency and subsequently form a co-simulation. The CPU which is dominant in system study faces a tremendous challenge in handling a great number of components albeit they exhibit homogeneity. The many-core graphics processing unit (GPU) featuring massive parallelism is therefore exploited and following the definition of an adaptive computing boundary, a flexible heterogeneous sequential-parallel processing architecture is proposed for efficient analysis of the wind farm-integrated AC/DC grid. Topological reconfiguration of WTs is specifically carried out to reduce the numerical order whilst enhancing system homogeneity that enables the GPU to thoroughly utilize its peculiar property of single-instruction multiple-thread (SIMT) compute paradigm. Consequently, significant speedups can be attained by the proposed computing framework over pure CPU computation, while its accuracy is validated by the commercial EMT and dynamic security analysis tools PSCAD/EMTDC and DSATools, respectively.

Radio resource management (RRM) is critical in 5G mobile communications due to its ubiquity on every radio device and its low latency constraints. The rapidly evolving RRM algorithms with low latency requirements combined with the dense and massive 5G base station deployment ask for an on-the-edge RRM acceleration system with a tradeoff between flexibility, efficiency, and cost-making application-specific instruction-set processors (ASIPs) an optimal choice. In this work, we start from a baseline, simple RISC-V core and introduce instruction extensions coupled with software optimizations for maximizing the throughput of a selected set of recently proposed RRM algorithms based on models using multilayer perceptrons (MLPs) and recurrent neural networks (RNNs). Furthermore, we scale from a single-ASIP to a multi-ASIP acceleration system to further improve RRM throughput. For the single-ASIP system, we demonstrate an energy efficiency of 218 GMAC/s/W and a throughput of 566 MMAC/s corresponding to an improvement of $10\times $ and $10.6\times $ , respectively, over the single-core system with a baseline RV32IMC core. For the multi-ASIP system, we analyze the parallel speedup dependency on the input and output feature map (FM) size for fully connected and LSTM layers, achieving up to $10.2\times $ speedup with 16 cores over a single extended RI5CY core for single LSTM layers and a speedup of $13.8\times $ for a single fully connected layer. On the full RRM benchmark suite, we achieve an average overall speedup of $16.4\times $ , $25.2\times $ , $31.9\times $ , and $38.8\times $ on two, four, eight, and 16 cores, respectively, compared to our single-core RV32IMC baseline implementation.

Graph analytics elicits insights from large graphs to inform critical decisions for business, safety and security. Several large-scale graph processing frameworks feature efficient runtime systems; however, they often provide programming models that are low-level and subtly different from each other. Therefore, end users can find implementation and specially optimization of graph analytics error-prone and time-consuming. This paper regards the abstract interface of the graph processing frameworks as the instruction set for graph analytics, and presents Grafs, a high-level declarative specification language for graph analytics and a synthesizer that automatically generates efficient code for five high-performance graph processing frameworks. It features novel semantics-preserving fusion transformations that optimize the specifications and reduce them to three primitives: reduction over paths, mapping over vertices and reduction over vertices. Reductions over paths are commonly calculated based on push or pull models that iteratively apply kernel functions at the vertices. This paper presents conditions, parametric in terms of the kernel functions, for the correctness and termination of the iterative models, and uses these conditions as specifications to automatically synthesize the kernel functions. Experimental results show that the generated code matches or outperforms handwritten code, and that fusion accelerates execution.

Low latency stream processing on large clusters consisting of hundreds to thousands of servers is an increasingly important challenge. A crucial barrier to tackling this challenge is stragglers , i.e., tasks that are significantly straggling behind others in processing the stream data. However, prior straggler mitigation solutions have significant limitations. They balance streaming workloads among tasks but may incur imbalanced backlogs when the workloads exhibit variance, causing stragglers as well. Fortunately, we observe that carefully scheduling the outgoing tuples of different tasks can yield benefits for balancing backlogs, and thus avoids stragglers. To this end, we present Hone , a tuple scheduler that aims to minimize the maximum queue backlog of all tasks over time. Hone leverages an online Largest-Backlog-First ( LBF ) algorithm with a provable good competitive ratio to perform efficient tuple scheduling. We have implemented Hone based on Apache Storm and evaluated it extensively via both simulations and testbed experiments. Our results show that under the same workload balancing strategy– shuffle grouping , Hone outperforms the original Storm significantly, with the end-to-end tuple processing latency reduced by 78.7 percent on average.

A reversible Turing machine (RTM) is a standard model of reversible computing that reflects physical reversibility. So far, to describe an RTM the quadruple formulation and the quintuple formulation have been used. In this paper, we propose the program form as a new formulation for RTMs. There, an RTM is described by a sequence of only five kinds of instructions. It is shown that any RTM in the quintuple form is converted to an RTM in the program form, and vice versa. We also show each instruction is implemented by a particular reversible logic element with memory called a rotary element (RE) very simply. Hence, a circuit that simulates a given RTM is easily and systematically constructed out of REs.

This paper provides a survey of methods and tools for automated code-reuse exploit generation. Such exploits use code that is already contained in a vulnerable program. The code-reuse approach allows one to exploit vulnerabilities in the presence of operating system protection that prohibits data memory execution. This paper contains a description of various code-reuse methods: return-to-libc attack, return-oriented programming, jump-oriented programming, and others. We define fundamental terms: gadget, gadget frame, gadget catalog. Moreover, we show that, in fact, a gadget is an instruction, and a set of gadgets defines a virtual machine. We can reduce an exploit creation problem to code generation for this virtual machine. Each particular executable file defines a virtual machine instruction set. We provide a survey of methods for gadgets searching and determining their semantics (creating a gadget catalog). These methods allow one to get the virtual machine instruction set. If a set of gadgets is Turing-complete, then a compiler can use a gadget catalog as a target architecture. However, some instructions can be absent. Hence we discuss several approaches to replace missing instructions with multiple gadgets. An exploit generation tool can chain gadgets by pattern searching (regular expressions) or considering gadgets semantics. Furthermore, some chaining methods use genetic algorithms, while others use SMT-solvers. We compare existing open-source tools and propose a testing system rop-benchmark that can be used to verify whether a generated chain successfully opens a shell.

Modern data-intensive applications demand high computation capabilities with strict power constraints. Unfortunately, such applications suffer from a significant waste of both execution cycles and energy in current computing systems due to the costly data movement between the computation units and the memory units. Genome analysis and weather prediction are two examples of such applications. Recent FPGAs couple a reconfigurable fabric with high-bandwidth memory (HBM) to enable more efficient data movement and improve overall performance and energy efficiency. This trend is an example of a paradigm shift to near-memory computing. We leverage such an FPGA with high-bandwidth memory (HBM) for improving the pre-alignment filtering step of genome analysis and representative kernels from a weather prediction model. Our evaluation demonstrates large speedups and energy savings over a high-end IBM POWER9 system and a conventional FPGA board with DDR4 memory. We conclude that FPGA-based near-memory computing has the potential to alleviate the data movement bottleneck for modern data-intensive applications., Comment: This is an extended and updated version of a paper published in IEEE Micro, vol. 41, no. 4, pp. 39-48, 1 July-Aug. 2021

In this article, we'll learn about the concepts of instruction organized in computer organization. On the premise of accessibility of ALU operands sorts of CPU organization is moreover endorsed in this article. When the constructing agent forms an Instruction it changes over the instruction from its memory helpers shape to standard machine language format called the "Instruction organize". Within the preparation of change, the constructing agent must decide the sort of instruction, change over typical names and express documentation to a base/displacement organize, decide the lengths of certain operands, and parse any strict and constants. An instruction arrangement characterizes the format of bits of instruction, in terms of its constituent parts. An instruction arrangement must incorporate an opcode and verifiably or unequivocally, zero or more operands. Each unequivocal operand is referenced utilizing one of tending to modes. Arrange must, certainly or unequivocally, show tending to the mode for each operand. For most instruction sets, more than on instruction used.

In the modern world, we use microprocessors which are either based on ARM or x86 architecture which are the most common processor architectures. ARM originally stood for ‘Acorn RISC Machines’ but over the years changed to ‘Advanced RISC Machines’. It was started as just an experiment but showed promising results and now it is omnipresent in our modern devices. Unlike x86 which is designed for high performance, ARM focuses on low power consumption with considerable performance. Because of the advancements in the ARM technology, they are becoming more powerful than their x86 counterparts. In this analysis we will collate the two architectures briefly and conclude which microprocessor will dominate the microprocessor industry. The processor which will perform better in different tests will be more suitable for the reader to use in their application. The shift in the industry towards ARM processors can change how we write softwares which in turn will affect the whole software development environment.

Design of high-performance processors with very low power requirement is the primary goal of many contemporary and futuristic applications. This brief presents a novel processor micro-architecture which is capable of achieving these requirements. The micro-architecture is based on RISC-V Instruction Set Architecture (ISA). The core is implemented and verified on Xilinx Virtex-7 FPGA board with a resource requirement of 7617 LUTs and 2319 FFs. This core could achieve a Dhrystone benchmark score of 1.71 DMIPS per MHz which is higher than ARM Cortex-M3 (1.50 DMIPS per MHz) and ARM Cortex-M4 (1.52 DMIPS per MHz). The Coremark benchmark is also tested on this core and it gives 4.13 Coremark per MHz. The physical design result of the core using commercial tools shows that it can achieve a maximum frequency of 198.02 MHz with 0.036 mm2 area and $17.36~\mu \text{W}$ /MHz power requirement at UMC 40 nm technology node. The core consumes a dynamic power of $19.75~\mu \text{W}$ /MHz at UMC 90nm which is 36% and 40% better than ARM Cortex-M3 and Cortex-M4 respectively and also lower than many others cores. The results show that this core can outperform many existing commercial and open-source cores.

Rich thread-level parallelism of GPU has motivated co-running GPU kernels on a single GPU. However, when GPU kernels co-run, it is possible that one kernel can leverage buffer overflow to attack another kernel running on the same GPU. There is very limited work aiming to detect buffer overflow for GPU. Existing work has either large performance overhead or limited capability in detecting buffer overflow. In this article, we introduce GMODx, a runtime software system that can detect GPU buffer overflow. GMODx performs always-on monitoring on allocated memory based on a canary-based design. First , for the fine-grained memory management, GMODx introduces a set of byte arrays to store buffer information for overflow detection. Techniques, such as lock-free accesses to the byte arrays, delayed memory free, efficient memory reallocation, and garbage collection for the byte arrays, are proposed to achieve high performance. Second , for the coarse-grained memory management, GMODx utilizes unified memory to delegate the always-on monitoring to the CPU. To reduce performance overhead, we propose several techniques, including customized list data structure and specific optimizations against the unified memory. For micro-benchmarking, our experiments show that GMODx is capable of detecting buffer overflow for the fine-grained memory management without performance loss, and that it incurs small runtime overhead (4.2 percent on average and up to 9.7 percent) for the coarse-grained memory management. For real workloads, we deploy GMODx on the TensorFlow framework, it only causes 0.8 percent overhead on average (up to 1.8 percent).

Owing to the failure of Dennard’s scaling, the past decade has seen a steep growth of prominent new paradigms leveraging opportunities in computer architecture. Two technologies of interest are Posit and RISC-V. Posit was introduced in mid-2017 as a viable alternative to IEEE-754, and RISC-V provides a commercial-grade open source Instruction Set Architecture (ISA). In this article, we bring these two technologies together and propose a Configurable Posit Enabled RISC-V Core called PERI. The article provides insights on how the Single-Precision Floating Point (“F”) extension of RISC-V can be leveraged to support posit arithmetic. We also present the implementation details of a parameterized and feature-complete posit Floating Point Unit (FPU). The configurability and the parameterization features of this unit generate optimal hardware, which caters to the accuracy and energy/area tradeoffs imposed by the applications, a feature not possible with IEEE-754 implementation. The posit FPU has been integrated with the RISC-V compliant SHAKTI C-class core as an execution unit. To further leverage the potential of posit , we enhance our posit FPU to support two different exponent sizes (with posit-size being 32-bits), thereby enabling multiple-precision at runtime. To enable the compilation and execution of C programs on PERI, we have made minimal modifications to the GNU C Compiler (GCC), targeting the “F” extension of the RISC-V. We compare posit with IEEE-754 in terms of hardware area, application accuracy, and runtime. We also present an alternate methodology of integrating the posit FPU with the RISC-V core as an accelerator using the custom opcode space of RISC-V.

The technology advances of CPU (Central Processing Unit) architecture alternate between generalization and specialization. In the past decade, the general performance has been enhanced while addressing the new brick walls that include power, memory, and ILP (Instruction-Level Parallelism). Thus, it will enter into the era of specialization called adaptable ISA (Instruction Set Architecture) for target applications. Reconfigurable devices such as FPGAs (Field Programmable Gate Array) can offer a solution if the two following issues are addressed. One is the FPGA design is not easy for non-hardware experts, and the other is the process is iterative and lengthy. The most apparent solution to those problems is an overlay that can abstract hardware details while providing a software-like interface. This article presents DRAGON (Dynamically Re-programmable Architecture of Gather-scatter Overlay Nodes), demonstrates its general aspects as well as the way it can be seamlessly integrated into any heterogeneous computing platform. The experimental evaluation of DRAGON reports more than four times better computational efficiency when compared to an Intel Core i9 CPU, in two stencil-based benchmarks.

The microprocessor revolution, of which this issue marks the 50th anniversary, drove remarkable innovations in instruction set architecture, microarchitecture, and system design, some of which continue to evolve in current research and commercial products. Many of these features were indeed new, but others have their roots in a line of processor architectures that predates this revolution and that, alone among those ancient species, continues to thrive in modern information technology (IT) world: the IBM mainframe, launched in 1964 as S/360 and now continuing as IBM Z. This article will briefly describe some of the “modern” features that were pioneered there, then recount how the mainframe made the transition into the complementary metal–oxide–semiconductor (CMOS) microprocessor world.

Thumb-2 is the most recent instruction set architecture for ARM processors which are one of the most widely used embedded processors. In this paper, two extensions are proposed to improve the performance of the Thumb-2 instruction set architecture, which are addressing mode extensions and sign/zero extensions combined with data processing instructions. To speed up access to an element of an aggregated data, the proposed approach first introduces three new addressing modes for load and store instructions. They are register-plus-immediate offset addressing mode, negative register offset addressing mode, and post-increment register offset addressing mode. Register-plus-immediate offset addressing mode permits two offsets and negative register offset allows offset to be a negative value of a register content. Post-increment register offset mode automatically modifies the offset address after the memory operation. The second is the sign/zero extension combined with a data processing instruction which allows the result of a data processing operation to be sign/zero extended to accelerate a type conversion. Several least frequently used instructions are reduced to provide the encoding space for the new extensions. Experiments show that the proposed approach improves performance by an average of 8.6% when compared to the Thumb-2 instruction set architecture.

Marvell ThunderX3 is the third-generation Arm-based server processor from Marvell. This article describes the architecture of ThunderX3, going into details of core microarchitecture. ThunderX3 is distinctive among mainstream processors in supporting four SMT threads. The article describes the threading microarchitecture of ThunderX3 and highlights threading benefits. The article also touches on the on-chip interconnect and L3-cache and the power management subsystem. Initial benchmark results from silicon show 30%+ single thread and up to 3X socket level performance gains over the prior generation resulting in industry-leading single thread and socket level performance.

Neural network (NN) accelerators based on resistive random access memory (ReRAM) have been widely investigated as a promising solution to address the memory wall challenge, due to its capability of processing-in-memory with extremely high density. However, the performance of these accelerators is bounded by the peripheral circuits and the interconnection. And they also suffer from accuracy issue and flexibility issue caused by the device-variation and the in-situ computation mode respectively. Solving these issues with hardware will further offset the performance. Enlightened by the design principle of conventional reduced instruction set computer (RISC), this article proposes a new software/hardware system for ReRAM-based NN acceleration, which achieves complex functions with sophisticated software tools while making the hardware much more compact and efficient, in order to fully utilize ReRAM potential. The hardware architecture, Field Programmable Synapse Array (FPSA), provides high-density reconfigurable logic, wires, and computational resources based on ReRAM-crossbar. Accordingly, the software can convert various types of NNs, including dynamic NNs, into equivalent networks that meet hardware constraints with negligible accuracy loss and optimize the scheduling and mapping of the latter onto FPSA. Further evaluations show that compared to one state-of-the-art ReRAM-based NN accelerator, PRIME, our approach achieves up to $1000\times$ 1000 × speedup.

In this article, we design and implement a full-packet capture and network measurement (FPC-NM) system in a 20 Gbit/s network. The system has multiple functions, such as packet receiving, nanosecond timestamp, load balancing, data packet preprocessing, application layer protocol analysis, data packet storage, and log management. We design a timestamp module in field programmable gate array (FPGA) that can add a timestamp to each captured packet, and the retrospective packet analysis can be done with 4 ns accuracy. As far as we know, this is the first time that nanosecond timestamp has been applied to FPC-NM system, which greatly improves the accuracy of security incident retrospective analysis. The experimental results show that the FPC-NM system can achieve 17 Gbit/s throughput and 160 000 connections per second under the premise of zero packet loss. Using LZ4 compression, the performance of our system for real-time compression and storage of traffic can achieve 10 Gbit/s. The system performance is improved by about 40% after software optimization including direct memory access buffer size adjustment and single instruction, multiple data (SIMD) instruction set, which validates the practicability and effectiveness of our optimization method.

Represented by application-specific instruction set processors (ASIPs) and array processors, existing cryptographic processors face challenges in application to mobile terminals with sensitive security requirements. Typically, ASIPs have limited computational efficiency and algorithmic adaptability. An array processor requires massive circuits to perform fully expansive computations for ciphers, and such processors are unaffordable for terminals. To overcome these issues, we propose a highly area-efficient parallel reconfigurable symmetric cipher stream processor combining the characteristics of symmetric cryptograph stream-state processing and the advantages of stream architectures. This processor has a hierarchical stream architecture with multi-dimensional parallelism. It decouples cipher computation from data transmission, facilitating parallelism between algorithm operation and data scheduling. Furthermore, the processor fully excavates vertical pipeline parallelism and horizontal block parallelism in its operation processes. Additionally, it takes multi-granular cipher units and reconfigures computation circuits to map different algorithms efficiently. These mechanisms significantly improve its area efficiency and security intensity. The processor's prototype was verified and synthesised in a 65 nm CMOS process. Many typical ciphers were mapped onto the processor. Experimental results demonstrate excellent performance in feedback/no-feedback modes with a small area (1.26 mm2). Therefore, its area efficiency is clearly higher than other cipher processors, and it has better prospects for future applications.

This work presents a simple integer-only instruction set architecture and microarchitecture derived from One Instruction Set Computers (OISCs) and embedding multiple execution modes ( ${m}$ OISC), capable of running at a reasonable performance level to enable basic usability in microcontroller applications. The purpose of ${m}$ OISC is to enable simple data transfer tasks and run small programs while maintaining ultimate simplicity. We present the internal organization for a computer architecture including an 8bit I/O register, and 64kB central Random Access Memory (RAM), organized in two-bytes words. The processor can run code generated assuming an OISC or a Complex Instruction Set Computer (CISC) scheme (op-code based), depending on the programmer’s demands and based on the initial setting of a register during start-up. To enable practical applications and demonstrate successful exploitation of ${m}$ OISC in view of integration in a compiler back-end, we designed a custom Proof-of-Concept (PoC) software design toolchain based on LLVM and clang. Although not targeting all the features of commercial ISA, the toolchain is capable of compiling C code from LLVM intermediate representation or generating ${m}$ OISC code translated from ARM, x86, RISC-V, and MIPS assembly. The toolchain also enables practical Value Change Dump (VCD) simulations output with graphical plots of the CPU state and associated symbols. A PoC microcontroller system has been synthesized in a low power Field Programmable Gate Array (FPGA) and verified in a basic wireless telemetry application including a Synchronous Peripheral Interface (SPI) RFM9x Long RAnge (LoRA) transceiver and a MAX30205 Inter Integrated Circuit (I2C) temperature sensor, using its 8bit I/O port, with software bus interface implementation. ${m}$ OISC occupies ~6% of resources on a Cyclone 10LP FPGA, for 1397 Adaptive Look-Up Tables (ALUTs) and 461 dedicated logic registers. The measured dynamic current consumption of the complete FPGA board with synthesized ${m}$ OISC is 12mA at 100MHz clock.

This study discusses the quality analysis of a new tapping machine. By measuring the torque and speed of the tapping machine, the correlation between the quality of the nut and the tapping process is analyzed. Using various regression trees and learning methods, the results show that the magnitude of the tapping torque is an essential indicator of the quality of the thread. In addition, through such methods, the appropriate operation boundary of the tapper torque and tapper speed can be determined. Thread, processed in the two boundaries, can have a high probability of being a Class 1 thread. Furthermore, the tapping torque is also used for quality classification by a one-dimensional convolutional neural network (1-D CNN). The 1-D CNN model performs high classification accuracy and has the ability to localize the important area of the signal. The experimental results show that the regression tree can effectively find the operation boundary, providing information for users to adjust their machine settings, and improve the thread quality. In addition, the off-line classification of thread done by humans can be replaced by the high-accuracy 1-D CNN model predicting the thread quality in real-time. The detection speed can be accelerated, and labor costs can be reduced.

Heterogeneous multi-core processors (HMP) with the same instruction set architecture (ISA) integrate complex high performance big cores with power efficient small cores on the same chip. In comparison with homogeneous architectures, HMPs have been shown to significantly increase energy efficiency. However, current techniques to exploit the energy efficiency of HMPs do not consider fair usage of resources that leads to reduced performance predictability, a longer makespan, starvation, and QoS degradation. The effect of different cluster voltage and frequency levels on fairness is another issue neglected by previous task scheduling algorithms. The present study investigates both the fairness problem and energy efficiency in HMPs. This article proposes a heterogeneous fairness-aware energy efficient framework (HFEE) that employs DVFS to meet fairness constraints and provide energy efficient scheduling. The proposed framework is implemented and evaluated on a real heterogeneous multi-core processor. The experimental results indicate that the introduced technique can significantly improve energy efficiency and fairness when compared to Linux standard scheduler and two energy efficient and fairness-aware schedulers.

As semiconductor technology scales, modern microprocessors are more vulnerable to transient faults. Software-level fault tolerance schemes are promising because they can improve reliability effectively without extra hardware. Redundant Multi-threading (RMT) uses off-the-shelf cores as redundancy to achieve error resilience. Latest software RMT fault-tolerance models do not effectively cope with transient faults occurring on multiple components during the application execution, resulting in a large number of silent data corruptions (SDC). To address this challenge, we propose FERNANDO, a software-level RMT runtime fault tolerance scheme which provides enhanced error detection and comprehensive error recovery by Triple-Modular Redundancy (TMR). On an ARM Cortex-A57 like simulated microprocessor, we performed probability model transient fault injection experiments in different components of all cores. The results demonstrate that, compared to the state-of-the-art technique, FERNANDO can reduce the SDC rate by about 86.67 percent and optimize the execution time overhead by about 19.64 percent.