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1. Physics-Based and Closed-Form Model for Cryo-CMOS Subthreshold Swing

Author

Beckers, Arnout, Michl, Jakob, Grill, Alexander, Kaczer, Ben, Bardon, Marie Garcia, Parvais, Bertrand, Govoreanu, Bogdan, De Greve, Kristiaan, Hiblot, Gaspard, and Hellings, Geert

Subjects
Condensed Matter - Mesoscale and Nanoscale Physics
Abstract

Cryogenic semiconductor device models are essential in designing control systems for quantum devices and in benchmarking the benefits of cryogenic cooling for high-performance computing. In particular, the saturation of subthreshold swing due to band tails is an important phenomenon to include in low-temperature analytical MOSFET models as it predicts theoretical lower bounds on the leakage power and supply voltage in tailored cryogenic CMOS technologies with tuned threshold voltages. Previous physics-based modeling required to evaluate functions with no closed-form solutions, defeating the purpose of fast and efficient model evaluation. Thus far, only the empirically proposed expressions are in closed form. This article bridges this gap by deriving a physics-based and closed-form model for the full saturating trend of the subthreshold swing from room down to low temperature. The proposed model is compared against experimental data taken on some long and short devices from a commercial 28-nm bulk CMOS technology down to 4.2 K., Comment: Accepted for publication in IEEE Transactions on Nanotechnology

Published
2022
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2. Comphy v3.0 -- A Compact-Physics Framework for Modeling Charge Trapping Related Reliability Phenomena in MOS Devices

Author

Waldhoer, Dominic, Schleich, Christian, Michl, Jakob, Grill, Alexander, Claes, Dieter, Karl, Alexander, Knobloch, Theresia, Rzepa, Gerhard, Franco, Jacopo, Kaczer, Ben, Waltl, Michael, and Grasser, Tibor

Subjects
Physics - Applied Physics
Abstract

Charge trapping plays an important role for the reliability of electronic devices and manifests itself in various phenomena like bias temperature instability (BTI), random telegraph noise (RTN), hysteresis or trap-assisted tunneling (TAT). In this work we present Comphy v3.0, an open source physical framework for modeling these effects in a unified fashion using nonradiative multiphonon theory on a one-dimensional device geometry. Here we give an overview about the underlying theory, discuss newly introduced features compared to the original Comphy framework and also review recent advances in reliability physics enabled by these new features. The usefulness of Comphy v3.0 for the reliability community is highlighted by several practical examples including automatic extraction of defect distributions, modeling of TAT in high-k capacitors and BTI/RTN modeling at cryogenic temperatures.

Published
2022
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5. Evidence of contact-induced variability in industrially-fabricated highly-scaled MoS2 FETs.

Author

Panarella, Luca, Kaczer, Ben, Smets, Quentin, Tyaginov, Stanislav, Saraza Canflanca, Pablo, Vici, Andrea, Verreck, Devin, Schram, Tom, Lin, Dennis, Knobloch, Theresia, Grasser, Tibor, Lockhart de la Rosa, César, Kar, Gouri S., and Afanas'ev, Valeri

Subjects
SCHOTTKY barrier, CONTACT dermatitis, FIELD-effect transistors, RANDOM noise theory, MODULATION-doped field-effect transistors
Abstract

Evidence of microscopic inhomogeneities of the side source/drain contacts in 300 mm wafer integrated MoS2 field-effect transistors is presented. In particular, the presence of a limited number of low Schottky barrier spots through which channel carriers are predominantly injected is demonstrated by the dramatic current changes induced by individual charge traps located near the source contact. Two distinct types of "contact-impacting traps" are identified. Type-1 trap is adjacent to the contact interface and exchanges carriers with the metal. Its impact is only observable when the adjacent contact is the reverse-biased FET source and limits the channel current. Type-2 trap is located in the AlOx gate oxide interlayer, near the source contact, and exchanges carriers with the channel. Its capture/emission time constants exhibit both a gate and drain bias dependence due to the high sensitivity of the contact regions to the applied lateral and vertical fields. Unlike typical channel-impacting oxide traps, both types of reported defects affect the Schottky barrier height and width rather than the threshold voltage and result in giant random telegraph noise (RTN). These observations indicate that the contact quality and geometry play a fundamental role in the ultimate scaling of 2D FETs. [ABSTRACT FROM AUTHOR]

Published
2024
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7. NBTI in Nanoscale MOSFETs - The Ultimate Modeling Benchmark

Author

Grasser, Tibor, Rott, Karina, Reisinger, Hans, Waltl, Michael, Schanovsky, Franz, and Kaczer, Ben

Subjects
Condensed Matter - Mesoscale and Nanoscale Physics, Condensed Matter - Materials Science
Abstract

After nearly half a century of research into the bias temperature instability (BTI), two classes of models have emerged as the strongest contenders: one class of models, the reaction-diffusion models, is built around the idea that hydrogen is released from the interface and that it is the diffusion of some form of hydrogen that controls both degradation and recovery. While many different variants of the reaction-diffusion idea have been published over the years, the most commonly used recent models are based on non-dispersive reaction rates and non- dispersive diffusion. The other class of models is based on the idea that degradation is controlled by first-order reactions with widely distributed (dispersive) reaction rates. We demonstrate that these two classes give fundamentally different predictions for the stochastic degradation and recovery of nanoscale devices, therefore providing the ultimate modeling benchmark. Using de- tailed experimental time-dependent defect spectroscopy (TDDS) data obtained on such nanoscale devices, we investigate the compatibility of these models with experiment. Our results show that the diffusion of hydrogen (or any other species) is unlikely to be the limiting aspect that determines degradation. On the other hand, the data are fully consistent with reaction-limited models. We finally argue that only the correct understanding of the physical mechanisms leading to the significant device-to-device variation observed in the degradation in nanoscale devices will enable accurate reliability projections and device optimization.

Published
2014
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8. Compact Physics Hot-Carrier Degradation Model Valid over a Wide Bias Range

Author

Tyaginov, Stanislav, primary, Bury, Erik, additional, Grill, Alexander, additional, Yu, Zhuoqing, additional, Makarov, Alexander, additional, De Keersgieter, An, additional, Vexler, Mikhail, additional, Vandemaele, Michiel, additional, Wang, Runsheng, additional, Spessot, Alessio, additional, Chasin, Adrian, additional, and Kaczer, Ben, additional

Published
2023
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9. Impact of Nitridation on Bias Temperature Instability and Hard Breakdown Characteristics of SiON MOSFETs

Author

Tyaginov, Stanislav, primary, O’Sullivan, Barry, additional, Chasin, Adrian, additional, Rawal, Yaksh, additional, Chiarella, Thomas, additional, de Carvalho Cavalcante, Camila Toledo, additional, Kimura, Yosuke, additional, Vandemaele, Michiel, additional, Ritzenthaler, Romain, additional, Mitard, Jerome, additional, Palayam, Senthil Vadakupudhu, additional, Reifsnider, Jason, additional, and Kaczer, Ben, additional

Published
2023
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12. A Pragmatic Model to Predict Future Device Aging

Author

Brown, James, primary, Tok, Kean Hong, additional, Gao, Rui, additional, Ji, Zhigang, additional, Zhang, Weidong, additional, Marsland, John S., additional, Chiarella, Thomas, additional, Franco, Jacopo, additional, Kaczer, Ben, additional, Linten, Dimitri, additional, and Zhang, Jian Fu, additional

Published
2023
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15. On Superior Hot Carrier Robustness of Dynamically-Doped Field-Effect-Transistors

Author

Tyaginov, Stanislav, Afzalian, Aryan, Makarov, Alexander, Grill, Alexander, Vandemaele, Michiel, Cherenev, Maksim, Vexler, Mikhail, Hellings, Geert, and Kaczer, Ben

Subjects
interface traps, Technology, Science & Technology, carrier transport, Physics, Hot-carrier degradation, PASSIVATION, Engineering, Multidisciplinary, Engineering, Electrical & Electronic, dynamically doped field-effect-transistor, non-equilibrium Green functions, DEGRADATION, HYDROGEN, Physics, Applied, Engineering, Physical Sciences, INTERFACE DEFECTS, SCATTERING, KINETICS
Abstract

ispartof: 2022 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) ispartof: IEEE International Reliability Physics Symposium (IRPS) location:TX, Dallas date:27 Mar - 31 Mar 2022 status: published

Published
2022

16. Simulation Comparison of Hot-Carrier Degradation in Nanowire, Nanosheet and Forksheet FETs

Author

Vandemaele, Michiel, Kaczer, Ben, Tyaginov, Stanislav, Bury, Erik, Chasin, Adrian, Franco, Jacopo, Makarov, Alexander, Mertens, Hans, Hellings, Geert, and Groeseneken, Guido

Subjects
Technology, Science & Technology, TCAD, STRESS, gate-all-around FETs, Physics, Engineering, Multidisciplinary, Engineering, Electrical & Electronic, trapping, interface defects, Physics, Applied, MODEL, Engineering, Border traps, hot-carrier degradation, nanosheet FETs, forksheet FETs, Physical Sciences, oxide defects, nanowire FETs, simulations
Abstract

ispartof: 2022 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) ispartof: IEEE International Reliability Physics Symposium (IRPS) location:TX, Dallas date:27 Mar - 31 Mar 2022 status: published

Published
2022

22. Understanding the Origin of Metal Gate Work Function Shift and Its Impact on Erase Performance in 3D NAND Flash Memories

Author

Ramesh, Sivaramakrishnan, primary, Ajaykumar, Arjun, additional, Ragnarsson, Lars-Åke, additional, Breuil, Laurent, additional, El Hajjam, Gabriel, additional, Kaczer, Ben, additional, Belmonte, Attilio, additional, Nyns, Laura, additional, Soulié, Jean-Philippe, additional, Van den bosch, Geert, additional, and Rosmeulen, Maarten, additional

Published
2021
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23. Toward reliability-aware physics-based FET compact models

Author

Kaczer, Ben

Subjects
reliability, FET, compact models
Abstract

Outline Introduction Degradation mechanisms basics Bias Temperature Instability (BTI) and Compact Physical (Comphy) model for trapping Hot Carrier Degradation (HCD) Self-Heating (SH) Time-Dependent Dielectrics Breakdown (TDDB) Measuring degradation using on-chip circuits Approaches to reliability compact modeling Comphy > CM Comphy + HCD sEKV-based CM BSIM-based CM TCAD >CM Conclusions

Published
2021
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26. Physical Modeling the Impact of Self-Heating on Hot-Carrier Degradation in pNWFETs

Author

Tyaginov, Stanislav, Makarov, Alexander, Bury, Erik, Vandemaele, Michiel, Jech, Markus, Grill, Alexander, Keersgieter, An De, Linten, Dimitri, and Kaczer, Ben

Subjects
Hot-carrier degradation, self-heating, transport, interface states, NWFET, modeling
Abstract

We develop and validate a physics-based modeling framework for coupled hot-carrier degradation (HCD) and self-heating (SH). Within this framework, we obtain the lattice temperature distribution throughout the device by solving the lattice heat flow equation coupled with the drift-diffusion approach. Then, the evaluated temperature spatial profile in the transistor is taken into account while solving the Boltzmann transport equation for carriers to obtain the carrier energy distribution functions, which are needed to compute the rates of the single and multiple-carrier mechanisms of bond dissociation. The effect of SH on HCD is threefold: (i) it results in a significant distortion of the carrier distribution function, (ii) device heating decreases vibrational lifetime of the Si-H bond, thereby suppressing the multiple-carrier mechanism, and (iii) the rate of thermal bond breakage becomes higher due to SH. The model is capable of accurately reproducing relative changes in the saturation drain current with stress time measured in p-channel nanowire field-effect transistors subjected to HCD under different stress conditions. We show that neglecting SH leads to substantial underestimation of HCD.

Published
2020
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27. A new TDDB reliability prediction methodology accounting for multiple SBD and wear out

Author

Sahhaf, Sahar, Degraeve, Robin, Roussel, Philippe J., Kaczer, Ben, Kauerauf, Thomas, and Groeseneken, Guido

Subjects
Breakdown (Electricity) -- Analysis, Gates (Electronics) -- Evaluation, Reliability (Engineering) -- Analysis, Business, Electronics, Electronics and electrical industries
Abstract

The time-dependent dielectric breakdown in thin gate oxides is studied and a new methodology is proposed that is applicable to a wide range of gate stacks for extracting soft breakdown (SBD) and post-SBD wear-out (WO) parameters from measuring the time to hard breakdown ([t.sub.HBD) only. A new complete reliability prediction model is proposed that has included SBD and WO.

Published
2009

28. An analysis of the NBTI-induced threshold voltage shift evaluated by different techniques

Author

Zhigang Ji, Jian Fu Zhang, Mo Huai Chang, Kaczer, Ben, and Groeseneken, Guido

Subjects
Voltage -- Evaluation, Gate arrays -- Analysis, Metal oxide semiconductor field effect transistors -- Thermal properties, Metal oxide semiconductor field effect transistors -- Evaluation, Field programmable gate array, Business, Electronics, Electronics and electrical industries
Abstract

The article presents various different techniques that can be employed for the evaluation of the threshold voltage shift induced by the negative bias temperature instability (NBTI). The effects of sensing and recovery are shown to be the major factors that need to be considered during the process of voltage evaluation.

Published
2009

29. Evidence that two tightly coupled mechanisms are responsible for negative bias temperature instability in oxynitride MOSFETs

Author

Grasser, Tibor and Kaczer, Ben

Subjects
Holes (Electron deficiencies) -- Analysis, Metal oxide semiconductor field effect transistors -- Thermal properties, Metal oxide semiconductor field effect transistors -- Electric properties, Silicon -- Electric properties, Silica -- Electric properties, Business, Electronics, Electronics and electrical industries
Abstract

Several stress and recovery experiments are conducted to explain the mechanisms that are shown to initiate the negative bias temperature instability (NBTI) in the pMOS transistors. Generation of defects near the silicon/silicon dioxide interface and hole trapping in the oxide are shown to be the two main mechanisms imvolved in the generation of NBTI.

Published
2009

30. LaSiO x - and Al 2 O 3 -Inserted Low-Temperature Gate-Stacks for Improved BTI Reliability in 3-D Sequential Integration.

Author

Wu, Zhicheng, Franco, Jacopo, Vandooren, Anne, Arimura, Hiroaki, Ragnarsson, Lars-Ake, Roussel, Philippe, Kaczer, Ben, Linten, Dimitri, Collaert, Nadine, and Groeseneken, Guido

Subjects
ALUMINUM oxide, COMPLEMENTARY metal oxide semiconductors, CHARGE carrier mobility, ELECTRON traps
Abstract

Sequential 3-D stacking of multiple CMOS device tiers in a single fabrication flow requires the development of reliable high- ${k}$ /metal gate (HKMG) stacks at a reduced thermal budget (<525 °C). The omission of the customary high-temperature gate-stack annealing results in excessive dielectric defect densities. We have recently demonstrated on MOS capacitors the insertion of “defect decoupling” layers–LaSiOx for nMOS and Al2O3 for pMOS–at the interface between SiO2 and HfO2 as a promising approach to engineer the high- ${k}$ band lineup and minimize charge trapping for improved bias-temperature-instability (BTI) reliability. In this article, we demonstrate this approach in planar transistors, which allows assessing the impact of defect decoupling on carrier mobility. First, a comparative study on the impact of LaSiOx and Al2O3 insertion is performed, highlighting the different strategies for improving positive BTI (PBTI) and negative BTI (NBTI) reliability. Second, a comprehensive investigation on the effects of LaSiOx and Al2O3 insertion is conducted with a focus on BTI reliability and channel carrier mobility: a lack of penalty (Al2O3) or even improved carrier mobility (LaSiOx) is reported for the dipole-inserted gate stacks. Furthermore, we explore the simplified dual gate-stack integration for CMOS flow. A severe PBTI reliability penalty is observed if an Al2O3 layer (for hole trap decoupling) is deposited in the nMOS gate-stack, even if on top of the beneficial LaSiOx (for electron trap decoupling). In contrast, the pMOS gate-stack is found to be more tolerant to the presence of a residual LaSiOx layer on top of the beneficial Al2O3 layer, suggesting a viable strategy for the simplified dual gate-stack integration. Finally, the reliability improvement is validated also on a FinFET test vehicle. [ABSTRACT FROM AUTHOR]

Published
2022
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32. Reliability of strained-Si devices with post-oxide-deposition strain introduction

Author

Shickova, Adelina, Verheyen, Peter, Eneman, Geert, Degraeve, Robin, Simoen, Eddy, Favia, Paola, Klenov, Dmitri O., Andres, Enrique San, Kaczer, Ben, Jurczak, Malgorzata, Absil, Philippe, Maes, Herman E., and Groeseneken, Guido

Subjects
Metal oxide semiconductor field effect transistors -- Electric properties, Metal oxide semiconductor field effect transistors -- Mechanical properties, Metal oxide semiconductor field effect transistors -- Structure, Polycrystalline semiconductors -- Mechanical properties, Business, Electronics, Electronics and electrical industries
Abstract

The impact of strain on negative bias temperature instability (NBTI) is assessed by studying devices with polycrystalline-Si/SiON as well as deposited metal gate/high-[kappa] and FUSI/high-[kappa] gate stacks. The studies have shown that there is no degradation of intrinsic NBTI behavior due to process-induced strain.

Published
2008

33. Theory of breakdown position determination by voltage- and current-ratio methods

Author

Alam, Muhammad Ashraful, Varghese, Dhanoop, and Kaczer, Ben

Subjects
Field-effect transistors -- Structure, Field-effect transistors -- Electric properties, Business, Electronics, Electronics and electrical industries
Abstract

The design and verification of a theory of the current-ratio (CR) technique in uniform semiconductors, which is widely used to locate gate oxide breakdown (BD) spots in one dimension, is reported. The newly developed technique could be used to interpret BD-spot distributions in 2-D to better predict gate oxide reliability.

Published
2008

34. Correlated Time-0 and Hot-Carrier Stress Induced FinFET Parameter Variabilities: Modeling Approach

Author

Makarov, Alexander, Roussel, Philippe, Bury, Erik, Vandemaele, Michiel, Spessot, Alessio, Linten, Dimitri, Kaczer, Ben, and Tyaginov, Stanislav

Subjects
interface traps, Technology, FinFETs, IMPACT, lcsh:Mechanical engineering and machinery, PASSIVATION, STATISTICAL VARIABILITY, physical modeling, Article, hot-carrier degradation, lcsh:TJ1-1570, Nanoscience & Nanotechnology, Instruments & Instrumentation, Science & Technology, carrier transport, variability, THRESHOLD VOLTAGE, random dopants, DISSOCIATION KINETICS, DEGRADATION, FLUCTUATIONS, random traps, INTERFACE DEFECTS, TRANSCONDUCTANCE, Science & Technology - Other Topics, GATE OXIDE
Abstract

We identify correlation between the drain currents in pristine n-channel FinFET transistors and changes in time-0 currents induced by hot-carrier stress. To achieve this goal, we employ our statistical simulation model for hot-carrier degradation (HCD), which considers the effect of random dopants (RDs) on HCD. For this analysis we generate a set of 200 device instantiations where each of them has its own unique configuration of RDs. For all &ldquo, samples&rdquo, in this ensemble we calculate time-0 currents (i.e. currents in undamaged FinFETs) and then degradation characteristics such as changes in the linear drain current and device lifetimes. The robust correlation analysis allows us to identify correlation between transistor lifetimes and drain currents in unstressed devices, which implies that FinFETs with initially higher currents degrade faster, i.e. have more prominent linear drain current changes and shorter lifetimes. Another important result is that although at stress conditions the distribution of drain currents becomes wider with stress time, in the operating regime drain current variability diminishes. Finally, we show that if random traps are also taken into account, all the obtained trends remain the same.

Published
2020

35. Impact of MOSFET gate oxide breakdown on digital circuit operation and reliability

Author

Kaczer, Ben, Degraeve, Robin, Rasras, Mahmoud, Koen Van de Mieroop, Roussel, Philippe J., and Groeseneken, Guido

Subjects
Digital integrated circuits -- Analysis, Reliability (Engineering) -- Analysis, Field-effect transistors -- Analysis, Field-effect transistors -- Properties, Business, Electronics, Electronics and electrical industries
Abstract

The influence of field-effect transistor (FET) gate oxide breakdown on the performance of a ring oscillator circuit is studied using statistical tools, emission microscopy and circuit analysis. It is further demonstrated that many hard breakdowns can occur in this circuit without affecting its overall function.

Published
2002

36. Consistent model for short-channel nMOSFET after hard gate oxide breakdown

Author

Kaczer, Ben, Degraeve, Robin, De Keersgieter, An, Van de Mieroop, Koen, Simons, Veerle, and Groeseneken, G.

Subjects
Breakdown (Electricity) -- Analysis, Field-effect transistors -- Analysis, Field-effect transistors -- Properties, Business, Electronics, Electronics and electrical industries
Abstract

A consistent picture for field-effect transistors (nFET) with hard gate oxide breakdown is proposed and supported by MEDICI and SPICE simulations. The circuit proposed could be used for determining how strongly gate oxide breakdown affects both digital and analog circuit operation.

Published
2002

40. Special Issue on Reliability

Author

Mahapatra, Souvik, primary, Chen, Kevin J., additional, Kaczer, Ben, additional, Pancheri, Lucio, additional, Rosenbaum, Elyse, additional, Mouli, Chandra, additional, Wong, Hei, additional, Kerber, Andreas, additional, Monzio Compagnoni, Christian, additional, Koval, Randy, additional, Meneghesso, Gaudenzio, additional, Sheridan, David, additional, Ramey, Stephen, additional, Wang, Runsheng, additional, and Stathis, Jim, additional

Published
2019
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41. Trigger-when-charged: a technique for directly measuring RTN and BTI-induced threshold voltage fluctuation under use-Vdd

Author

Manut, Azrif, Gao, Rui, Zhang, Jian Fu, Ji, Zhigang, Mehedi, Mehzabeen, Zhang, Wei Dong, Vigar, David, Asenov, Asen, and Kaczer, Ben

Abstract

—Low-power circuits are important for many\ud applications, such as Internet of Things. Device variations\ud and fluctuations are challenging their design. Random telegraph noise (RTN) is an important source of fluctuation.\ud To verify a design by simulation, one needs assessing\ud the impact of fluctuation in both driving current Id and\ud threshold voltage Vth. Many early works, however, only\ud measured RTN-inducedId. Vth was not directly measured\ud because of two difficulties: its average value is low and\ud it is highly dynamic. Early works often estimated Vth\ud from Id/gm(Vg = Vdd), where gm is the transconductance,\ud without giving its accuracy. The objective of this paper is to\ud develop a new Trigger-When-Charged (TWC) technique for\ud directly measuring the RTN-induced Vth. By triggering the\ud measurement only when a trap is charged, measurement\ud accuracy is substantially improved. It is found that there\ud is a poor correlation between Id/gm(Vg = Vdd) and the\ud directly measured Vth (Vg = Vth). The former is twice of the\ud latter on average. The origin for this difference is analyzed.\ud For the first time, the TWC is applied to evaluate deviceto-device variations of the directly measured RTN-induced\ud Vth without selecting devices.

Published
2019

42. Full (V-g, V-d) Bias Space Modeling of Hot-Carrier Degradation in Nanowire FETs

Author

Vandemaele, Michiel, Kaczer, Ben, Tyaginov, Stanislav, Stanojevic, Zlatan, Makarov, Alexander, Chasin, Adrian, Bury, Erik, Mertens, Hans, Linten, Dimitri, and Groeseneken, Guido

Subjects
Technology, Science & Technology, Engineering, TCAD, hot-carrier degradation, carrier energy distribution function, Engineering, Electrical & Electronic, nanowire FETs, impact ionization, interface defects
Abstract

© 2019 IEEE. Simulations of hot-carrier degradation of nanowire field-effect transistors are reported. The simulations rely on the carrier energy distribution function, obtained by solving the Boltzmann transport equation. To model the contribution of impact ionization, the hydrodynamic scheme is employed. A range of pertinent physical mechanisms is invoked and discussed to adequately reproduce HCD measurements in the full (V g, V d) bias space. Impact ionization is discussed as an important ingredient of HCD at low gate, high drain voltages. ispartof: 2019 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) vol:2019-March ispartof: IEEE International Reliability Physics Symposium (IRPS) location:CA, Monterey date:31 Mar - 4 Apr 2019 status: published

Published
2019

43. On the Apparent Non-Arrhenius Temperature Dependence of Charge Trapping in Iota Iota Iota V/High-k MOS Stack

Author

Putcha, Vamsi, Franco, Jacopo, Vais, Abhitosh, Sioncke, Sonja, Kaczer, Ben, Linten, Dimitri, and Groeseneken, Guido

Subjects
Technology, Science & Technology, InGaAs, reliability, Physics, Engineering, Electrical & Electronic, non-Arrhenius, TRAPS, Physics, Applied, ENERGY, capture-emission-time (CET) map, Engineering, Physical Sciences, Bias temperature instability, bivariate defect distributions
Abstract

© 1963-2012 IEEE. Operating temperature has a significant imp-act on the reliability of metal-oxide-semiconductor field effect transistors (MOSFETs). In Si-channel MOSFETs, the effective density of charged oxide defects ( Δ Neff) at operating condition typically shows an Arrhenius temperature dependence with EA 0.1 eV. In contrast, apparent non-Arrhenius temperature dependence is reported here for InGaAs devices subjected to BTI stress in a wide range of temperature (77-373 K). This apparent non-Arrhenius temperature dependence is explained here by the presence of three distinct populations of electron traps. Capture-emission-time maps are derived from the experimental data, and are modeled by three bivariate distributions of energy barriers for the capture and emission processes. The total ΔV th measured in biaserature-instability experiments reflects different contributions from the three defect populations, depending on the chosen temperature range, and on the measurement timing. We show that a correct description of the three defect distributions is crucial to properly assess their impact on the device performance. ispartof: IEEE TRANSACTIONS ON ELECTRON DEVICES vol:65 issue:9 pages:3689-3696 status: published

Published
2018

44. A Sensitivity Map-Based Approach to Profile Defects in MIM Capacitors From${I}$– ${V}$,${C}$– ${V}$, and${G}$– ${V}$Measurements

Author

Padovani, Andrea, primary, Kaczer, Ben, additional, Pesic, Milan, additional, Belmonte, Attilio, additional, Popovici, Mihaela, additional, Nyns, Laura, additional, Linten, Dimitri, additional, Afanas'ev, Valeri V., additional, Shlyakhov, Ilya, additional, Lee, Younggon, additional, Park, Hokyung, additional, and Larcher, Luca, additional

Published
2019
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48. Degradation and breakdown of plasma oxidized magnetic tunnel junctions: single trap creation in [Al.sub.2][O.sub.3] tunnel barriers

Author

Das, Jo, Degraeve, Robin, Kaczer, Ben, Boeve, Hans, Vanhelmont, Frederik, Groeseneken, Guido, Borghs, Gustaaf, and De Boeck, Jo

Subjects
Electromagnetism -- Research, Business, Electronics, Electronics and electrical industries
Abstract

We present an in-depth analysis of the reliability of plasma oxidized magnetic tunnel junctions, using constant voltage stress until breakdown. In the stress measurements, prebreakdown current jumps were also observed. We show that the prebreakdown jumps, as well as the final breakdown are caused by the generation of single trap conduction paths in the barrier. Finally, we demonstrate that applying stress can also cause gradual resistance changes, which can either be reversible or irreversible. Index Terms--Dielectric breakdown, magnetic tunnel junctions, reliability.

Published
2003

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