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This paper describes the theory, design, implementation, simulation, and testing of an ASIC capable of generating false target radar images for countering wideband synthetic aperture and inverse synthetic aperture imaging radars. The 5.5 6.1 mm IC has 81632 transistors, 132 I/O pins, and consumes 0.132 W at 70 MHz from a 3.3-V supply. An introduction to the application and operation of the ASIC in an electronic attack system is also presented. The false target image is fully programmable and the chip is capable of generating images of both small and large targets, even up to the size of an aircraft carrier. This is the first reported use of all-digital technology to generate false target radar images of large targets. Naval Research Laboratory Office of Naval Research

The subject of this thesis is a digital image synthesizer (DIS), which is especially useful as a counter-targeting signal repeater, i.e., for synthesizing the characteristic echo signature of a pre-selected target. The DIS has a digital radio frequency memory (DRFM) and associated circuitry, including digital tapped delay lines and a modulator in each delay line to impose both amplitude and frequency modulation in each line. A unique property of the digital image synthesizer is its ability to synthesize false targets using wideband chirp signals of any duration. The system-on-a-chip uses a scalable CMOS technology that increases the bandwidth and sensitivity of such a repeater over prior analog-based systems. The application-specific integrated-circuit reduces the noise of the repeated signal, reduces the size and cost of such a system and permits real-time alteration of operating parameters, permitting rapid and adaptive shifting among different types of targets to be synthesized http://archive.org/details/anlldigitalimage109457620 LTC, Swedish Army