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In this paper we suggest that further energy savings can be achieved by a new approach to synthesis of embedded processor cores, where the architecture is tailored to the algorithms that the core executes. In the context of embedded processor synthesis, both single-core and many-core, the types of algorithms and demands on the execution efficiency are usually known at the chip design time. This knowledge can be utilised at the design stage to synthesise architectures optimised for energy consumption. Firstly, we present an overview of both traditional energy saving techniques and new developments in architectural approaches to energy-efficient processing. Secondly, we propose a picoMIPS architecture that serves as an architectural template for energy-efficient synthesis. As a case study, we show how the picoMIPS architecture can be tailored to an energy efficient execution of the DCT algorithm.

This paper proposes a novel genetic-based high-level synthesis methodology for ΣΔ modulators. This approach is based on simulation-based optimisation where optimal topology of the ΣΔ modulator is automated explored using a genetic algorithm (GA) under various design constraints, such as SNR (Signal to-Noise Ratio) and hardware complexity. The proposed synthesis technique has been implemented in SystemC-A due to its advantages in terms of high simulation speed, flexibility and data manipulation. Experimental results validates the effectiveness of the synthesis approach.