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7. A 0.013 mm² 3.2-ns Input Range 10-Bit Cyclic Time-to-Digital Converter Using Gated Ring Oscillator With Phase Domain Reset in 65-nm CMOS

Author

Lu, Xin, Wu, Jiangchao, Wang, Zhao, Xiang, Yifei, Liu, Liyuan, Mak, Pui-In, Martins, Rui P., and Law, Man-Kay

Abstract

This brief presents a compact gated ring oscillator (GRO) based cyclic time-to-digital converter (TDC) for single-photon emission computed tomography, 3D cameras, and fluorescence lifetime imaging microscopy. With a single GRO serving as both the quantizer and residue generator, the GRO period can serve as the time reference to achieve intrinsic coarse-fine conversion. The proposed cyclic TDC also features a phase domain reset scheme which generates a compensation pulse for purging the GRO phase residue among consecutive conversion cycles. Fabricated in 65nm CMOS, this work occupied an area of 0.013mm2. The proposed TDC achieves a high resolution of 3.1ps together with an extended input range of 3.2ns. Consuming 1.41mW at 36MS/s from a 1-V supply, it also demonstrates a measured DNL and INL of +0.5/-0.6LSB and +3.3/-3.6LSB, respectively.

Published
2024
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10. One-Cycle-Startup Relaxation Oscillator Using Ratiometric Threshold-Referenced and Self-Synchronized Power Gating Techniques

Author

Zhao, Guangshu, Xiao, Zhiming, Mak, Pui-In, Martins, Rui P., and Law, Man-Kay

Abstract

This brief presents a one cycle startup relaxation oscillator (RO) suitable for resource-constrained wearable and implantable applications. For improving energy efficiency without relying on a low supply voltage, we propose a self-synchronized power gating technique to completely shut down almost all the analog building blocks except near the clock toggling moment. We further relax the system startup energy and size by introducing the ratiometric threshold-referenced technique and deadlock avoidance circuit to quickly pre-bias the internal RC network without using extra on-chip references. The proposed RO is designed and fabricated in standard 0.18- $\mu \text{m}$ CMOS, with four distinct implementations at 1kHz, 10kHz, 100kHz, and 1MHz. Measurement results show that all the ROs can achieve one-cycle startup operation. The 100kHz RO, which occupies an active area of only 0.041mm2, achieves a line sensitivity of ±1.14%/V from 1.7 to 1.9V while exhibiting an energy efficiency of 2.7nW/kHz. After trimming on-chip resistors with complementary temperature coefficients (TCs), the 1MHz RO attains a measured TC of 82ppm/°C from–25 to 100°C, as well as a noise-power figure-of-merit (FoM) of 149 dBc/Hz@100kHz.

Published
2024
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11. A 12/24 V-Input HV-LV-Separated Hybrid SC PoL Converter With 355 mW/mm3 Power Density at 3 A Load Current and 15.2 mm3 Power Passives

Author

Zhang, Xiongjie, Ma, Qiaobo, Zhao, Anyang, Jiang, Yang, Law, Man-Kay, Jiang, Junmin, Takamiya, Makoto, Martins, Rui P., and Mak, Pui-In

Abstract

This letter presents a high-power-density point-of-load dc–dc converter for 12/24 V input applications, using the proposed high voltage-low voltage separated hybrid switched-capacitor (SC) topology. By incorporating inductors between the SC networks in HV/LV domains, the design achieves reduced inductor dc current (IL,DC) at small voltage conversion ratios (VCRs), optimized switching and conduction losses, and extended duty ratio range, enabling the use of small-sized inductors with higher dc resistance and resulting in a compact system volume. LV switches handle most of the current conduction, reducing switching losses and silicon area for higher on-chip power density. The fabricated converter, using a 180-nm BCD process, generates 0.8–1.8 V output from 12/24 V inputs with a 3-A maximum load. Measured results show total IL,DC of 1.2 A at VCR 0.075 and 2 A load. The converter achieves a peak power density of 355 mW/mm3 with a power passive volume of 15.2 mm3. Peak efficiencies are 85% at 12 V input and 84.2% at 24 V input.

Published
2023
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12. A 10.5 W, 93% Efficient Dual-Path Hybrid (DPH)-Based DC–DC Converter Incorporating a Continuous-Current-Input Switched-Capacitor Stage and Enhanced IL Reduction for 12 V/24 V Inputs

Author

Ma, Qiaobo, Zhang, Xiongjie, Zhao, Anyang, Li, Huihua, Jiang, Yang, Law, Man-Kay, Takamiya, Makoto, Martins, Rui P., and Mak, Pui-In

Abstract

This work proposes a high-step-down switched-capacitor (SC) hybrid DC-DC converter that effectively addresses the conduction loss in the inductor and power switches. Specifically, an architecture combining a dual-path hybrid (DPH) converter at the input, and a continuous-current-input SC (CISC) stage at the output, achieves superior performance in reducing the inductor DC current ( $I_{\mathrm {L,DC}}$ ) compared to the existing single-inductor two-flying-capacitor ( $1L$ - $2C_{\mathrm {F}}$ ) converters. Also, the converter exploits low-voltage (LV) switches to handle a substantial portion of the current, diminishing the reliance on the inductor or high-voltage (HV) switches. Consequently, this approach enhances the efficiency and on-chip power/current density. The converter, implemented in 180-nm BCD, integrates monolithic power switches, drivers, and control circuitry. It is capable of regulating an output voltage within the range of 1.2 to 3.5 V, accommodating a 12 V/24 V-input. The peak efficiency is 93% and the on-chip current density is 0.638A/mm2. The load current delivery is up to 3 A, even using a compact inductor with a DC resistance (DCR) of 200 $\text{m}\Omega $ .

Published
2023
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25. A − °C–125 °C 0.4- μ A Low-Noise Bandgap Voltage Reference With 0.8-mA Load Driving Capability Using Shared Feedback Resistors.

Author

Zhang, Zhaobo, Zhan, Chenchang, Wang, Lidan, and Law, Man-Kay

Abstract

This brief presents a fully integrated low-power, low noise bandgap reference (BGR) with load driving capability. With the BGR core resistors functioning as the feedback network of the current sourcing power transistor, the proposed BGR saves chip area, reduces noise while supporting current load driving. The circuit is implemented in two different processes for performance comparison, namely the $0.18\mathbf {\mathrm {\mu }}\text{m}$ RF CMOS and the BCD mixed-signal CMOS processes. Measurement results from chip samples of the two processes show similar performances, with an average temperature coefficient (TC) of 27.1ppm/°C over $\mathbf {-} 40\mathbf {\mathrm {\sim }} 125\mathbf {^{\circ} }\text{C}$ at a 1.8-V supply. The corresponding measured coefficient of variation ($\mathbf {\mathrm {\sigma }}/\mathbf {\mathrm {\mu }}$) is around 0.3%, and the load driving capability can be up to $800\mathbf {\mathrm {\mu }}\text{A}$. By reusing the feedback resistors, the chip prototype achieved a low noise density of $1.92~\mathbf {\mathrm {\mu }}\text{V}/\surd $ Hz, 285nV/ $\surd $ Hz and 4nV/ $\surd $ Hz at 10 Hz, 10 kHz and 100 kHz, respectively, while consuming a quiescent current of 396nA. The measured power supply rejection (PSR) is −39dB at 5Hz and −45dB at 1MHz. The influence of load current on PSR has also been analyzed and verified. [ABSTRACT FROM AUTHOR]

Published
2022
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26. L<inline-formula><tex-math notation="LaTeX">${}_{\text{2}}$</tex-math></inline-formula>min<inline-formula><tex-math notation="LaTeX">${}^{\text{2/2s}}$</tex-math></inline-formula>: Efficient Linear Reconstruction Filter for Incremental Delta-Sigma ADCs

Author

Wang, Bo, Law, Man-Kay, and Schneider, Jens

Abstract

While it becomes more challenging to improve the energy efficiency of incremental delta-sigma data converters (IDCs) from the analog circuit design perspective, we propose two novel linear reconstruction filters for IDCs to enhance their performance in a digital way, including the L${}_{\mathbf{2}}$min${}^{\mathbf{2}}$ filter and its symmetric version, the L${}_{\mathbf{2}}$min${}^{\mathbf{2s}}$ filter. Compared to the classical linear reconstruction filters, such as the cascade-of-integrators (CoI) and cascaded integrator-comb (CIC) filter (an implementation of sinc filter), the proposed filters can achieve efficient quantization and thermal noise suppression, with the lowest thermal noise penalty factor of 1.2 among the high-order linear reconstruction filters. In this paper, we present analytical, numerical, and experimental results to demonstrate the superior performance of the filters for first-order and second-order IDC output reconstruction. The proposed filters are hardware-friendly and example digital implementations in a standard complementary metal-oxide-semiconductor (CMOS) and field-programmable gate array (FPGA) platforms are included in this paper.

Published
2023
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30. Introduction

Author

Lei, Ka-Meng, Mak, Pui-In, Law, Man-Kay, and Martins, Rui Paulo

Subjects
Article
Abstract

An essential part to evaluate the success of global health is the access to appropriate diagnostic tools [1]. A commendable diagnostic tool should be able to identify the disease occurred from the individuals rapidly. Especially for the infectious diseases, the turnaround time (TAT) for the diagnosis strongly affects their exacerbation level to the community. In vitro diagnostic (IVD) tool is aimed to offer a comfortable diagnosis for the patients, by taking only small specimens from the human body, e.g., blood, urine, or sputum, for analysis. Consequently, technologies enabling effective in vitro diagnosis become highly attractive for both developed and developing countries [2]. Tremendous efforts have been geared toward developing clinical-level IVD tools. Despite achieving high accuracy, the resulting TAT can be too long for diagnoses of contagious diseases like Ebola and SARS in the rural area, and the requisite of skillful operators and sophisticated equipment to perform the assays can dramatically raise the cost of the assay.

Published
2017

44. A 10.6 pJ $\cdot\text{K}^{2}$ Resolution FoM Temperature Sensor Using Astable Multivibrator.

Author

Wang, Bo, Law, Man-Kay, Tsui, Chi-Ying, and Bermak, Amine

Abstract

This brief presents a 0.9- $\mu \text{W}$ duty-cycle-modulated temperature sensor with a sub- $\mu \text{A}$ peak current for energy harvester- or micro-battery-powered systems. A compact sensing frontend is proposed to achieve low power, together with various device-level leakage and nonlinearity compensation techniques adopted to minimize the sensor error. In addition, a current-starved multivibrator which provides inherent clamping voltages is used for duty cycle modulation for overall energy savings. The sensor designed in 0.18- $\mu \text{m}$ CMOS process achieves a resolution figure of merit of 10.6 pJ $\cdot \text{K}^{2}$ , which is among the most energy-efficient designs to date. Trimmed at 30 °C, the sensor achieves ±0.85 °C precision from −30 °C to 120 °C. The maximum supply sensitivity is 0.7 °C/V for a 1.6–2 V supply. [ABSTRACT FROM AUTHOR]

Published
2018
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50. A 2- \mu\textW 45-nV/√Hz Readout Front End With Multiple-Chopping Active-High-Pass Ripple Reduction Loop and Pseudofeedback DC Servo Loop.

Author

Wu, Jiangchao, Law, Man-Kay, Mak, Pui-In, and Martins, Rui P.

Abstract

This brief presents an ultra-low-power low-noise chopped capacitively coupled instrumentation amplifier (CCIA) that is suitable for neural recording applications. An active high-pass filter is embedded in the ripple reduction loop (RRL) to suppress the residual noise and relax the capacitor size. Multiple chopping is employed to further reduce the residual output ripple due to the RRL offsets. A dc servo loop (DSL) using a 14-nA pseudofeedback amplifier is proposed to achieve a subhertz high-pass corner while using only a 15-pF on-chip capacitor. The complete CCIA is implemented in a standard 0.18- \mu\textm CMOS process. It occupies an area of 0.23 mm2 (including the DSL) and consumes 1.7 \mu\textA from a 1.25-V supply, achieving a noise efficiency factor of 2.9 that compares favorably with the state of the art. [ABSTRACT FROM AUTHOR]

Published
2016
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