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Arithmetic unit is the most important component of modern embedded computer systems. Arithmetic unit generally includes floating point and fixed-point arithmetic operations and trigonometric functions. Multipliers units are the most important hardware structures in a complex arithmetic unit. With increase in chip frequency, the designer must be able to find the best set of trade-offs. The ability for faster computation is essential to achieve high performance in many DSP and Graphic processing algorithms and is why there is at least one dedicated Multiplier unit in all of the modern commercial DSP processors. Tremendous advances in VLSI technology over the past several years resulted in an increased need for high speed multipliers and compelled the designers to go for trade-offs among speed, power consumption and area. A novel modified booth multiplier design for high speed VLSI applications using pre-computation logic has been presented in this paper. The proposed architecture modeled using Verilog HDL, simulated using Cadence NCSIM and synthesized using Cadence RTL Compiler with 65nm TSMC library.The proposed multiplier architecture is compared with the existing multipliers and the results show significant improvement in speed and power dissipation.

Magnetically impelled arc butt (MIAB) welding is a pressure welding process used for joining of pipes and tubes with an external magnetic field affecting arc rotation along the tube circumference. In this work, MIAB welding of low alloy steel (T11) tubes were carried out to study the microstructural changes occurring in thermo-mechanically affected zone (TMAZ). To qualify the process for the welding applications where pressure could be up to 300 bar, the MIAB welds are studied with variations of arc current and arc rotation time. It is found that TMAZ shows higher hardness than that in base metal and displays higher weld tensile strength and ductility due to bainitic transformation. The effect of arc current on the weld interface is also detailed and is found to be defect free at higher values of arc currents. The results reveal that MIAB welded samples exhibits good structural property correlation for high pressure applications with an added benefit of enhanced productivity at lower cost. The study will enable the use of MIAB welding for high pressure applications in power and defence sectors.

High speed and efficient multipliers are essential components in today’s computational circuits like digital signal processing, algorithms for cryptography and high performance processors. Invariably, almost all processing units will contain hardware multipliers based on some algorithm that fits the application requirement. Tremendous advances in VLSI technology over the past several years resulted in an increased need for high speed multipliers and compelled the designers to go for trade-offs among speed, power consumption and area. Amongst various methods of multiplication, Vedic multipliers are gaining ground due to their expected improvement in performance. A novel multiplier design for high speed VLSI applications using Urdhva-Tiryagbhyam sutra of Vedic Multiplication has been presented in this paper. The proposed architecture modeled using Verilog HDL, simulated using Cadence NCSIM and synthesized using Cadence RTL Compiler with 65nm TSMC library.The proposed multiplier architecture is compared with the existing multipliers and the results show significant improvement in speed and power dissipation.

The VLSI binary adder is the basic building block in any computation unit. It is widely used in the arithmetic logic unit, memory addressing computation and in many other places. In this paper the binary adder is presented with keeping in mind speed, power and finally area. In this paper the BCD adder is designed using the mixed approach such as hierarchical, muxing and variable grouping techniques. The design and result are presented in this paper

High speed and efficient multipliers are essential components in today’s computational circuits like digital signal processing, algorithms for cryptography and high performance processors. Invariably, almost all processing units will contain hardware multipliers based on some algorithm that fits the application requirement. Tremendous advances in VLSI technology over the past several years resulted in an increased need for high speed multipliers and compelled the designers to go for trade-offs among speed, power consumption and area. Amongst various methods of multiplication, Vedic multipliers are gaining ground due to their expected improvement in performance. A novel multiplier design for high speed VLSI applications using Urdhva-Tiryagbhyamsutra of Vedic Multiplication has been presented in this paper. The multiplier architecture is implemented using Verilog coding and synthesise during Cadence RTL Compiler. Physical design is implemented using Cadence Encounter RTL-to-GDSII System using standard 180nm technology. The proposed multiplier architecture is compared with the conventional multiplier and the results show significant improvement in speed and power dissipation.

Systems in which the dynamical behaviour evolves based on the interaction between the continuous dynamics and the discrete dynamics, present in the system, are called hybrid systems. Traditionally such systems were analysed either as purely continuous or purely discrete systems. The interactions between discrete and continuous systems in today’s technological problems have become so important that hybrid modelling of such systems is called for. In this paper a discrete controller is designed for such a hybrid system. Hybrid modelling technique is used to model the hybrid three tank systems. The hybrid model is simulated in SIMULINK and STATEFLOW is used to design the discrete controller.