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This study describes a high-performance second-generation Current Conveyor (CCII) operating at 0.35 V and achieving rail-to-rail operation at the Y terminal and class AB current drive at the X and Z terminals. The solution utilizes a low-voltage subthreshold bulk-driven CMOS OTA that was experimentally developed earlier, making systematic use of body terminals to improve small-signal and large-signal performance. The circuit has a high open-loop voltage gain and uses cascoded current mirror topologies, resulting in precise voltage and current transfer with bandwidths of 1.33 MHz and 2.13 MHz, respectively. The CCII offers a linear current drive up to 2.5 µA while consuming a total quiescent current of 2.86 µA (758 nA in the output branches), displaying one the highest figures of merit in terms of current utilization for sub 1 V solutions. [ABSTRACT FROM AUTHOR]

This paper investigates CMOS operational transconductance amplifier (OTA) design methodologies suitable for Internet of Things nodes. The use of MOS transistors in the subthreshold of the body terminal for signal input or bias, as well as newer inverter- and digital-based techniques, is considered. Solutions from the authors' work are utilized as main case examples. State-of-the-art ultra-low-power OTAs are then thoroughly compared using a data-driven approach. According to the findings, digital- and inverter-based solutions have the lowest area occupation and superior small-signal performance but are inherently susceptible to process, supply, and temperature (PVT) variations. The only "analog" approach suitable for a sub-0.6 V supply is body driving in conjunction with subthreshold bias. It offers competitive large-signal performance and, more importantly, is less sensitive to PVT variations at the expense of silicon area. [ABSTRACT FROM AUTHOR]

Solutions for the design of low-voltage sample-and-hold (S/H) circuits in CMOS nanometer technologies are presented. As a design example, a 0.8-V supply S/H is designed and simulated using a 130-nm CMOS process. It dissipates 0.5 mW at dc and provides almost a rail-to-rail signal swing. When clocked at 40 MS/s and with a 1.4-[V.sub.PP] differential input signal, the simulated spurious-free dynamic range, signal-to-noise ratio, and total harmonic distortion are 57, 67, and -56 dB (9 equivalent bits), respectively, with low sensitivity to supply, temperature, process, and mismatch variations. The proposed solution employs a three-stage low-voltage amplifier without a tail current source in the differential pair and a switch topology, which combines clock voltage doubling and dummy switches. Index Terms--Bootstrapped switch, nested Miller compensation, sample-and-hold (S/H), very low voltage circuits.

Several design options are nowadays available for the frequency compensation of CMOS two-stage transconductance q operational amplifiers, from the traditional Miller approach employing a nulling resistor or a voltage buffer, to a current buffer or the more modern current amplifier. However, designers have no results on the frequency performance achievable that allow to consciously choose the best approach to meet the prescribed specifications efficiently. In this paper, a comparison among the possible Miller approaches is carried out by exploiting an analytical figure of merit that expresses a tradeoff between gain--bandwidth product, load capacitance, and total transconductance for a given value of phase margin. Interesting and useful results, even unexpected, are found. The accuracy of the comparison is also validated through simulations. Index Terms--Analog integrated circuits, frequency compensation, feedback amplifier, CMOS, multistage amplifier.

The paper presents the derivation of Miller formulas for weakly nonlinear feedback networks. The expressions found are simple and compact and constitute a generalization of the well-known linear case. As an application example, the formulas are applied to a common-emitter amplifier to straightforwardly derive the closed-form expressions of second- and third-harmonic distortion factors. The results found, validated by Spectre simulations with a VBIC bipolar model, allow to understand in depth the contribution of each nonlinear element. Index Terms--Amplifiers, analog circuits, harmonic distortion, Miller theorem, nonlinear network analysis.

Theoretical study and design strategy for Wien oscillator circuits are presented. The analysis takes into account non-linearities and allows to define an optimum design procedure minimizing distortion. The accuracy and viability of both the proposed analysis and design approach are confirmed experimentally. Index Terms--Analog circuits, circuit optimization, harmonic distortion, nonlinear network analysis, oscillators.

Two internally compensated CMOS current-feedback operational amplifiers are discussed in this paper. The circuits are entirely made up of class AB stages, thereby increasing slew rate and drive capability, avoiding many of the drawbacks incurred by previous CMOS and even bipolar implementations. Experimental results on one prototype fabricated in a 0.35-[micro]m process using a 20-pF load and supplied with 3.3 V are also given, showing, as main performance parameters, a SR of 35 V/[micro]s and a constant closed-loop bandwidth (in inverting configuration with a 10- [ohm] feedback resistor) of about 2 MHz. Index Terms--Amplifiers, CMOS, current-feedback operational amplifiers (CFOAs).

A mixed-signal universal architecture able to emulate the behavior of an n-port analog circuit is presented. It exploits second-generation current conveyors as analog input/output blocks and a field programmable gale array circuit as digital processing element. A prototype is also discussed for the specific case of a two-port network synthesis and experimental results in agreement with expected ones arc provided. Index Terms--Current conveyor, floating impedance synthesis, network synthesis, vibration damping.

A supplementary linearization technique for CMOS differential pairs with resistive source degeneration is proposed. The approach exploits an auxiliary (degenerated) differential pair to drive the bulk terminals of the main pair. Transistor-level simulations on a design using a 0.25-[micro]m process and powered with 2.5 V and 1 mA, show that total harmonic distortion (THD) in the voltage-to-current conversion is decreased by 10 dB (for an input differential signal with a peak amplitude of 0.5 V and for frequencies up to 100 MHz) compared to the traditional source-degenerated transconductor. This THD improvement is achieved with a negligible increase in power consumption. Index Terms--Analog CMOS circuits, linearization technique, transconductors.

Two CMOS current output stages are presented. Compared to the traditional solution, which exhibits unbalanced operation, the proposed ones exploit an auxiliary high-gain feedback loop which provides differential drive, thereby highly improving the common-mode rejection ratio (CMRR). Prototypes are designed and fabricated in a 0.35-[micro]m technology and experimental results confirm that a CMRR increase greater than 20 dB can be achieved and, for one of the two solutions, without increasing the voltage requirements. Index Terms--Analog electronics, CMOS, current mode, output stage.

The use of two frequency compensation schemes for three-stage operational transconductance amplifiers, namely the reversed nested Miller compensation with nulling resistor (RNMCNR) and reversed active feedback frequency compensation (RAFFC), is presented in this paper. The techniques are based on the basic RNMC and show an inherent advantage over traditional compensation strategies, especially for heavy capacitive loads. Moreover, they are implemented without entailing extra transistors, thus saving circuit complexity and power consumption. A well-defined design procedure, introducing phase margin as main design parameter, is also developed for each solution. To verify the effectiveness of the techniques, two amplifiers have been fabricated in a standard 0.5-[micro] m CMOS process. Experimental measurements are found in good agreement with theoretical analysis and show an improvement in small-signal and large-signal amplifier performances. Finally, an analytical comparison with the nonreversed counterparts topologies, which shows the superiority of the proposed solutions, is also included. Index Terms--Analog integrated circuits, CMOS, feedback amplifier, frequency compensation, multistage amplifier.

Design procedures for three-stage CMOS operational transconductance amplifiers employing nested-Miller frequency compensation are presented in this paper. After describing the basic methodology on a Class-A topology, some modifications, to increase swing, slew-rate and current drive capability, are subsequently discussed for a Class-AB solution. The approaches developed are simple as they do not introduce unnecessary circuit constraints and yield accurate results. They are hence suited for a pencil-and-paper design, but can be easily integrated into an analog knowledge-based computer-aided design tool. Experimental prototypes, designed in a 0.35-[micro]m technology by following the proposed procedures, were fabricated and tested. Measurement results were found in close agreement with the target specifications. Index Terms--CMOS, multistage amplifiers, nested-Miller compensation, operational transconductance amplifiers (OTAs).

This brief introduces and develops a novel frequency compensation technique for three-stage operational transconductance amplifiers. The new compensation topology exploits a voltage buffer and a nulling resistor to achieve a double pole-zero cancellation, occurring beyond the gain-bandwidth product. To verify the effectiveness of the compensation scheme, an amplifier has been fabricated in a standard 0.5-[micro]m CMOS process. Experimental measurements are found to be in good agreement with the theoretical analysis and show an improvement in small-signal and large-signal performances. Index Terms--Frequency compensation, operational transconductance amplifier (OTA), reversed nested Miller (RNM).

A CMOS pseudo-differential-input differential-output amplifier operating in class AB and exhibiting high-current-drive capability is presented. The circuit operates from a minimum supply of [V.sub.T] + 2[V.sub.DS,SAT], provides fast settling response, and also characterized by a wide input differential range with high linearity that enables its use even as a transconductor for filtering applications. For this purpose, a common-mode feedback section is also included. A circuit prototype was fabricated using a 0.35-[micro]m technology and powered with 2 V. Using a quiescent current of 20 [micro]A, experimental measurements show a differential current-drive capability of 1 mA (which is 50 times greater than the quiescent value), with this value being solely limited by the input voltage swing allowed. Third-order harmonic distortion is lower than -64 dB for a 1-Vpp 100-kHz input. Index Terms--Class AB, CMOS, differential pair, transconductor.

A simple compensation strategy, which employs passive components only, is adopted to design a three-stage operational transconductance amplifier (OTA) suitable for driving high capacitive loads. Compared to the classical nested Miller compensation technique, the new solution exploits two additional resistors and allows a reduction in the values of the compensation capacitors of about an order of magnitude. The OTA was fabricated using 0.35-[micro]m CMOS technology and exhibits a 1.4-MHz gain--bandwidth with a load of 500 pF. Index Terms--Frequency compensation, nested Miller, operational transconductance amplifier (OTA).

This paper proposes a theoretical approach for evaluating distortion in the frequency domain of three-stage amplifiers adopting two commonly used compensation techniques, namely the nested Miller (NM) and the reversed NM. The analysis is based on appropriate amplifier modeling and on the assumption that the nonlinearity generated by each stage is static. Calculations are thus greatly simplified avoiding complex methods based on the Volterra series. Only dominant contributions need to be taken into account, thereby highlighting those mechanisms generating distortion and their features in the frequency domain. Moreover, the adopted approach provides useful design guidelines and explains why the NM compensation technique allows generally better linearity performance at low frequency and why the reversed NM is best suited to high frequencies. Simulation results with Spectre on two transistor-level CMOS circuits are also provided and found to be in very good agreement with expected results. Index Terms--Feedback circuits, harmonic distortion, Miller compensation, multistage amplifiers.

A simple methodology to evaluate harmonic distortion in the frequency domain for circuits and systems made up of a nonlinear high-gain path with a nonlinear feedback network is presented. The approach provides compact closed-form expressions which constitute a direct extension of the classic ones valid at dc. The result improve our understanding of nonlinear frequency behavior in general feedback circuits and can even be used in manual design. The accuracy of the equations obtained was evaluated by comparison with computer simulations and measurements on an example circuit. Simulated and experimental data highly agree with the theoretical model. Index Terms--Amplifiers, analog circuits, circuit analysis, circuit feedback, feedback, feedback amplifiers, frequency-domain analysis, harmonic distortion.

A new concept of current-mode interface circuit for differential-capacitance transducers is proposed. The solution is suitable for integration and comprises a capacitance-to-current conversion that enables low-voltage operation, provides both high speed and accuracy, and minimizes post-processing. Index Terms--Analog CMOS, capacitive transducers, current-mode, integrated sensors, low voltage.

A novel CMOS current feedback op-amp is presented. The solution works using a low supply voltage and provides a wide input/output swing as well as a high current driving capability. Experimental results from a prototype implemented in a 0.35-[micro]m technology and powered with 1.5 V are also given. The circuit exhibits a better than 500 kHz closed-loop bandwidth and a [+ or -] -1 mA current drive capability. Index Terms--CMOS, current feedback opamp, high drive, low voltage.

An analysis and comparison of the performance of Tow-Thomas biquadratic filter sections, implemented with Miller integrators based on current feedback opamps (CFOAs) and voltage opamps (VOAs) was carried out. We found that the implementations with CFOAs show less parameter accuracy and an increased tendency to become instable. Design criteria to partially overcome these drawbacks and to maximally exploit the inherent high-speed potential of CFOAs were also derived. The theoretical derivations and related results were experimentally validated through implementations from commercially available devices. Index Terms--Analog filters, biquad, current feedback opamp (CFOA), current mode, integrator, quality factor, Tow-Thomas.

The reversed nested Miller compensation technique applied to a three-stage operational amplifier is discussed in this paper and new and simple design equations, accurately predicting the loop-gain phase margin, are developed. Techniques for parasitic positive-zero cancellation are also investigated and compared. For this purpose, we found that using nulling resistors is unpractical. Instead, exploiting only one follower (either a voltage or a current one) in the compensation branch results to be more appropriate. Indeed, not only does it avoid any additional constraint on stage transconductance, but it also overcomes the inherent limitations incurred by voltage and current followers when used to compensate two-stage amplifiers. Post-layout simulations on a CMOS opamp using the parameters of a 0.35-[micro]m process are found to be in good agreement with the expected results. Index Terms--Analog circuits, CMOS, frequency compensation, Nested Miller, OTA.

A novel CMOS low-voltage positive current conveyor of second generation is described in this paper. This solution allows almost rail-to-rail input and output operation and a high driving capability, thanks to the adoption of a class AB current output stage. A prototype was fabricated in a 0.35-[micro]m technology and experimentally tested. Using a 1.5-V supply, the circuit exhibited an input resistance of lower than 100 [ohm] at terminal X and a better than [+ or -] 0.9 mA current drive capability, which was about 45 times the quiescent current in the output branch. Good frequency performance was also obtained. Index Terms--CMOS, current conveyor, low voltage.

An approach for the evaluation of high-frequency harmonic-distortion factors in feedback systems is proposed and the results obtained are applied to feedback amplifiers. Under the assumption that transistors are not driven out of their linear operating regions, small-signal analysis and conventional algebra are exploited to derive understandable and compact expressions highly improving the comprehension of harmonic-distortion generation. The impact of the frequency compensation utilized (namely, dominant-pole or Miller technique) on linearity performance is evaluated and the high-frequency distortion properties of closed-loop single-stage and two-stage amplifiers are analyzed and compared. The accuracy of the analysis, also in view of the given applications, is confirmed through extensive simulations with Spectre on idealized models as well as on CMOS transistor-level circuits. Despite the approximated nature of the analytical models, predicted data are found in very close agreement with simulations in nearly all the frequency range of interest. Index Terms--Analog integrated circuits, feedback amplifiers, harmonic distortion, nonlinear distortion.

The nested Miller compensation of three-stage amplifiers is reviewed by using a simple design-oriented approach. The method provides stable amplifiers by accurately controlling the overall phase margin as well as that of the internal loop. Furthermore, the use of nulling resistors to remove the RHP zeros is discussed and optimization criteria are described. A novel technique is presented which allows an amplifier's frequency and settling performance to be greatly improved without increasing power consumption. Thanks to the small compensation capacitors employed, the approach is amenable for integration and in particular where large load capacitors have to be driven. SPICE simulations based on a 0.8-[micro]m CMOS design are given and found in remarkable agreement with the theoretical analysis. Index Terms--Amplifiers, analog integrated circuits, circuit stability, CMOS analog integrated circuits, CMOSFET power amplifiers, compensation, feedback amplifiers, feedback circuits, frequency compensation, multistage amplifier, zero compensation.

An approach for designing analog current-mode circuits with very-low supply voltage requirements is described and applied to the implementation of basic complementary metal-oxide-semiconductor (CMOS) building blocks. The method is based on a biasing circuit exploiting poly resistors and auxiliary differential amplifiers which restricts supply requirements to one threshold voltage plus three saturation voltages. As design examples, a complementary current mirror, a current operational amplifier, and a transconductor are implemented adopting the proposed technique. SPICE simulations using a 0.5-[micro]m process are provided which closely confirm the expected overall good performance of these circuits especially in terms of low-voltage capability and speed. Index Terms--Class AB, complementary metal-oxide-semiconductor (CMOS), current amplifier, current comparator, current mirror, current-mode, low-voltage, transconductor.

Design guidelines for CMOS current amplifiers with a high-drive capability are discussed in detail, paying special attention to the implementation of output stages with improved linearity performance. As a design example, two different current amplifiers were realized in a 1.2-[micro]m process and experimentally tested. Both circuits used a 5-V power supply and dissipated 5.5 and 4 mW, respectively. The open-loop gain was found to be 90 and 100 dB and the gain-bandwidth product was 8 and 10 MHz. The two amplifiers provide bipolar output currents as high as 15 and 7 mA, with a maximum total harmonic distortion of around -54 dB, using a quiescent current in the output branches of only 200 [micro]A. Index Terms--CMOS analog integrated circuits, current mode, integrated circuit design, operational amplifiers, power amplifiers.