1. A full-adder-based methodology for the design of scaling operation in residue number system
- Author
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Dasygenis, M., Mitroglou, K., Soudris, D., and Thanailakis, A.
- Subjects
Digital integrated circuits -- Design and construction ,Pipe lines -- Design and construction ,Pipe lines -- Equipment and supplies ,Signal processing -- Technology application ,Circuit design -- Research ,Digital signal processor ,Circuit designer ,Integrated circuit design ,Technology application ,Business ,Computers and office automation industries ,Electronics ,Electronics and electrical industries - Abstract
Over the last three decades, there has been considerable interest in the implementation of digital computer elements using hardware based on the residue number system, (RNS) due to the carry free addition and other beneficial characteristics of this system. Scaling operation is one of the essential operations in this number system, and is required for almost every digital signal processing application. Up to now, researchers have suggested costly and low throughput read-only memoy-based approaches to address this need. We also address this need by presenting a novel graph-based methodology for designing high-throughput and low-cost VLSI RNS scaling architectures, based completely on full adders (FAs). Our formalized methodology consists of a number of steps, which specify the minimum number of FAs for performing the scaling operation as well as the interconnections among the FAs. We present our formalized methodology together with a running example to aid in comprehension. Negative residue numbers are covered as weli, requiring no additional effort. Finally, we have developed a design support tool that can provide structural VHDL descriptions of our RNS scalers, which can be synthesized in VLSI tools. Index Terms--Digital integrated circuits, pipelining, residue number system (RNS), scaling.
- Published
- 2008