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In this paper, a new type of shallow-water seismic survey vessel is proposed to solve the problem that the traditional seismic survey vessels cannot satisfy the requirements of the shallow-water marine resources exploration. To reveal the influence of shallow water effect on resistance and flow field, this research is to obtain the resistance and shallow-water characteristics of this shallow-water seismic survey vessel through ship model experiments and numerical methods. Firstly, the ship model experiment predicted the resistance at different speeds in shallow water and obtained the benchmark data to validate numerical methods. Then, the CFD methods were used to calculate the resistance of the ship in deep and shallow water. The numerical results are in good agreement with the experimental results. Finally, this paper provided details of the distribution of wave, pressure and flow fields at different water depth conditions in order to explain the causes of increased resistance in shallow water, providing a reference for the shallow-water seismic survey vessel design.

This paper presents a novel approach to counterbalance free-carrier-absorption (FCA) in electro-optic (E-O) Mach-Zehnder interferometer (MZI) cells by harnessing self-heating effect. We show insights on crosstalk limitations in MZIs with direct carrier-injection and provide a detailed design methodology on a differential phase shifter pair. Leveraging both free-carrier dispersion (FCD) and self-heating effects, our design enables arbitrary phase tuning with balanced FCA loss in the pair of arms, eliminating the need for additional phase corrections and creating ultralow crosstalk MZI elements. This neat design disengages from the commonly used nested structure and thus provides an opportunity of embedding tunable couplers for correcting imperfect splitting ratios given that only two of which are needed. We show that with the use of tunable direction couplers (DCs), a standard ±10 nm process variation is tolerated, whilst achieving below -40dB crosstalk ratio. By direct carrier injection in both arms, the proposed device operates at nanosecond scales and can bring about a breakthrough in the scalability of E-O switch fabrics, as well as other silicon integrated circuits that have stringent requirements on crosstalk leakage.

We present a compact, highly tolerant vertical coupling structure, which can be a generic design that bridges the gap between conventional resonant couplers and adiabatic couplers for heterogeneously integrated devices. We show insights on relaxing the coupler alignment tolerance and provide a detailed design methodology. By the use of a multisegmented inverse taper structure, our design allows a certain proportion of the odd supermode to be excited during the coupling process, which simultaneously facilitates high tolerance and compactness. With a total length of 87 μm, our coupler is almost threefold shorter than the state-of-the-art alignment-tolerant adiabatic couplers and outperforms them by demonstrating a more than 94% coupling efficiency (for < 0.3 dB coupling loss) with ± 1 μm misalignment tolerance, which, to our best knowledge, is a new record for III-V-on-silicon vertical couplers. Furthermore, our design has high tolerance to fabrication-induced structural deformation and ultrabroad bandwidth. These features make it particularly suitable for building densely integrated III-V-on-silicon photonic circuits with commercially available microtransfer printing assembly tools. The proposed design can be widely adopted in various integration platforms.

This paper presents a time-division-multiplexed (TDM) clocked-analog low-dropout regulator (CLDO) that shares one controller between multiple output channels. Clocked-analog operation is introduced to create idle periods that enable the shared controller to independently regulate different output channels through time-division multiplexing. Furthermore, an asynchronous transient enhancing technique is presented. Thanks to the controller sharing, the TDM CLDO is more area-efficient than conventional designs for supplying multiple outputs, especially when power stages and on-chip loads are small. To verify the effectiveness of the TDM CLDO, a dual-channel version is fabricated in a 130 nm CMOS process. Measurement results show that it can independently track two 100 kHz $0.3~\rm V_{pp}$ sinusoidal signals with 4 mV average output error at $100~\Omega $ load and 6 MHz clock frequency. For load transient responses, it can independently regulate two output channels to 1.05 V and 0.95 V with 41 mV/88 mV and 67 mV/39 mV overshoot/undershoot when both channels experience 5 mA current steps at $1.2~\rm V_{dd}$ . To the best of our knowledge, this is the first time that hardware sharing is implemented for continuous closed-loop systems.

Unprecedented levels of device connectivity and the emergence of futuristic digital services are driving fundamental changes to underlying fixed and wireless data transport networks. Projected bandwidth requirements, coupled with increased network centralization and virtualization, will lead to the convergence of data-center, fixed and wireless systems, and a greater onus being placed on the optical routing/transport portion of these networks. Such converged networks will require the development of optical technologies capable of servicing a multitude of network user types. In this work, we propose the use of a Silicon Photonic (SiP) space-and-wavelength selective switch fabric as a flexible wavelength provisioning platform for converged optical networks. The envisaged converged network is presented and an experimental test-bed which demonstrates flexible Cloud Radio Access Networking (C-RAN), using a 4 × 4 micro-ring resonator based switch, is described. Successful provisioning and transmission of Wavelength Division Multiplexed (WDM) based analog Radio-over-Fiber (RoF) services, over 10 km of fiber, in the converged test-bed is demonstrated and evaluated in terms of the received Bit Error Rate (BER) and Error Vector Magnitude (EVM). Furthermore, the wavelength multi-casting capabilities of the SiP switch is shown to enable dynamic resource allocation in the optical domain, and this is highlighted through the experimental implementation and evaluation of two C-RAN use cases - representing high and low mobile traffic demand scenarios.

Widespread adoption of silicon photonics into datacenters requires that the integration of the driving electronics with the photonics be an essential component of transceiver development. In this article, we describe our silicon photonic transceiver design: a 2.5D integrated multi-chip module (MCM) for 4-channel wavelength division multiplexed (WDM) microdisk modulation targeting 10 Gbps per channel. A silicon interposer is used to provide connectivity between the photonic integrated circuit (PIC) and the commercial transimpedance amplifiers (TIAs). Error free modulation is demonstrated at 10 Gbps with -16 dBm received power for the photonic bare die and at 6 Gbps with -15 dBm received power for the first iteration of the MCM transceiver. In this context, we outline the different integration approaches currently being employed to interface between electronics and photonics - monolithic, 2D, 3D, and 2.5D - and discuss their tradeoffs. Notable demonstrations of the various integration architectures are highlighted. Finally, we address the scalability of the architecture and highlight a subsequent prototype employing custom electronic integrated circuits (EICs).

An N × N iterative photonic processor is proposed for the first time, we believe, for fast computation of complex-valued matrix inversion, a fundamental but computationally expensive linear algebra operation. Compared to traditional digital electronic processing, optical signal processing has a few unparalleled features that could enable higher representational efficiency and faster computing speed. The proposed processor is based on photonic integration platforms–the inclusion of III-V gain blocks offers net neutral loss in the phase-sensitive loops. This is essential for the Richardson iteration method that is adopted in this paper for complex linear systems. Wavelength multiplexing can be used to significantly improve the processing efficiency, allowing the computation of multiple columns of the inverse matrix using a single processor core. Performances of the key building blocks are modeled and simulated, followed by a system-level analysis, which serves as a guideline for designing an N × N Richardson iteration processor. An inversion accuracy of > 98 % can be predicted for a 64 × 64 photonic processor with a > 80 times faster inversion rate than electronic processors. Including the power consumed by both active components and electronic circuits, the power efficiency of the proposed processor is estimated to be over an order of magnitude more energy-efficient than electronic processors. The proposed iterative photonic integrated processor provides a promising solution for future optical signal processing systems.

The demand for ultra-long waveguides with tunable refractive index keeps growing in various applications, such as tunable delay line, Fourier transform spectrometers, microwave filters, signal processors, programmable photonics circuits, Lidar etc. Thermal tuning using integrated heaters is so far the most popular option to modulate the waveguide index due to simplicity of fabrication, high tuning efficiency, wide tuning range as well as absence of spurious amplitude modulation. But for ultra-long waveguide, the heater design needs to take the in-plane geometry into consideration in order to optimize particular performance metrics. Therefore, in this manuscript we report both theoretical modelling and experimental characterization of integrated heaters for ultra-long waveguides that pays special attention to the impacts of heater geometry.

We propose and analyze a scalable microring-based Clos switch fabric architecture constructed with switch-and-select switching stages. A silicon 4 × 4 building block that was designed and fabricated through American Institute for Manufacturing Integrated Photonics is used for the proof-of-principle demonstration of a 16 × 16 Clos switch fabric. By fully blocking the first-order crosstalk, the 4 × 4 device is measured to show a crosstalk ratio in the range of –57 to –48.5 dB, enabling better than –39 dB crosstalk for the 16 × 16 switch. Our study shows that the three-stage Clos design enables up to a factor of 4 in the reduction of the number of switching cells compared to single-stage switch-and-select fabrics. We further explore the design space for both first-order and second-order switching elements using the foundry-validated parameters and how these factors impact the performance and scalability of the three-stage Clos switch. A detailed power penalty map is drawn for Clos switch fabrics with various scales, which reveals that the ultimate key limiting factor is the shuffle insertion loss. An optimized 32-port Clos switch fabric using foundry-enabled parameters is shown to have a less than 10-dB power penalty.

We propose a universal and analytic step-by-step method to calculate the optimal 90° and 180° waveguide bends (L-bends and U-bends) in silicon-on-insulator photonics platform. This approach consists of first building an analytic model of loss per unit length as a function of radius of curvature and then using a variational optimization of the bending loss. It is shown that the shape of the optimal bends is ultimately determined either by the radiation loss of tight bends if the curvature of the bend is set to eliminate mode-mismatch losses or by the sidewall roughness loss if the radius of curvature is large. Numerical results from full wave simulations and comparison of the optimal bend with the Bezier, Euler, and Hybrid Euler-Circular bend are also provided to show the validity of our approach.

We review the motivation, goals, and achievements of the Photonic Integrated Networked Energy efficient datacenter (PINE) project, which is part of the Advanced Research Projects Agency–Energy (ARPA-E) ENergy-efficient Light-wave Integrated Technology Enabling Networks that Enhance Dataprocessing (ENLITENED) program. The PINE program leverages the unique features of photonic technologies to enable alternative mega-datacenters and high-performance computing (HPC) system architectures that deliver more substantial energy efficiency improvements than can be achieved through link energy efficiency alone. In phase 1 of the program, the PINE system architecture demonstrated an average factor of 2.2 × improvement in transactions/joule across a diverse set of HPC and datacenter applications. In phase 2, PINE will demonstrate an aggressive 1.0 pJ/bit total link budget with high-bandwidth-density dense wavelength-division multiplexing (DWDM) links to enable additional 2.5 × or more efficiency gains through deep resource disaggregation.

We demonstrate an ultra-broadband silicon photonic interleaver capable of interleaving and de-interleaving frequency comb lines over a 125 nm bandwidth in the extended C- and L-bands. We use a ring-assisted asymmetric Mach Zehnder interferometer to achieve a flat-top passband response while maintaining a compact device footprint. The device has a 400 GHz free spectral range to divide an optical frequency comb with 200 GHz channel spacing into two output groups, each with a channel spacing of 400 GHz, yielding a potential capacity of 78 total wavelength-division multiplexed channels between 1525 nm and 1650 nm. This device represents an important step towards realizing highly parallel integrated optical links with broadband frequency comb sources within the silicon photonics platform.

We demonstrate the first 2.5D integrated, wavelength division multiplexing, silicon photonic receiver. The multi-chip module utilizes a silicon interposer to integrate the four-channel photonic cascaded microdisk receiver with four electronic transimpedance amplifiers.

We introduce a novel design of a space-and-wavelength selective switch based on microring-assisted Mach–Zehnder interferometers. Multiple pairs of overcoupled microring resonators are incorporated as efficient and narrowband phase shifters and are driven in push–pull scheme. We design and demonstrate a 2 × 2 × 2 λ elementary switch block with full spatial and spectral switching capabilities. The switching device’s cross talk suppression and extinction ratio both exceed 21 dB. We measure over 75 GHz optical bandwidth per channel and less than 1.5 dB power penalty at 10 − 9 BER when two 32 Gbps on–off keying signals are loaded simultaneously. This new class of switching elements can further enable compact and high-performance space-and-wavelength selective switch fabrics without the need for wavelength (de)multiplexers or parallel switching planes.

A detailed analysis of fundamental tradeoffs between ring radius and coupling gap size is presented to draw realistic borders of the possible design space for microring resonators (MRRs). The coupling coefficient for the ring-waveguide structure is estimated based on an integration of the nonuniform gap between the ring and the waveguide. Combined with the supermode analysis of two coupled waveguides, this approach is further expanded into a closed-form equation that describes the coupling strength. This equation permits to evaluate how the distance separating a waveguide from a ring resonator, and the ring radius, affect coupling. The effect of ring radius on the bending loss of the ring is furthermore modeled based on the measurements for silicon MRRs with different radii. These compact models for coupling and loss are subsequently used to derive the main optical properties of MRRs, such as 3-dB optical bandwidth, extinction ratio of resonance, and insertion loss, hence identifying the design space. Our results indicate that the design space for add-drop filters in a wavelength division multiplexed link is currently limited to 5–10 $\mu$ m in radius and gap sizes ranging from 120 to 210 nm. The good agreement between the results from the proposed compact model for coupling and the numerical FDTD and experimental measurements indicate the application of our approach in realizing fast and efficient design space exploration of MRRs in silicon photonic interconnects.

We report on the first monolithically integrated microring-based optical switch in the switch-and-select architecture. The switch fabric delivers strictly non-blocking connectivity while completely canceling the first-order crosstalk. The 4×4 switching circuit consists of eight silicon microring-based spatial (de-)multiplexers interconnected by a Si/SiN dual-layer crossing-free central shuffle. Analysis of the on-state and off-state power transfer functions reveals the extinction ratios of individual ring resonators exceeding 25 dB, leading to switch crosstalk suppression of up to over 50 dB in the switch-and-select topology. Optical paths are assessed, showing losses as low as 0.1 dB per off-resonance ring and 0.5 dB per on-resonance ring. Photonic switching is actuated with integrated micro-heaters to give an ∼24 GHz passband. The fully packaged device is flip-chip bonded onto a printed circuit board breakout board with a UV-curved fiber array.

We live in an era of information explosion and digital revolution that has resulted in rapid technological developments in different aspects of life [...]

Photonic switches are increasingly considered for insertion in high performance datacenter architectures to meet the growing performance demands of interconnection networks. We provide an overview of photonic switching technologies and develop an evaluation methodology for assessing their potential impact on datacenter performance. We begin with a review of three categories of optical switches, namely, free-space switches, III-V integrated switches and silicon integrated switches. The state-of-the-art of MEMS, LCOS, SOA, MZI and MRR switching technologies are covered, together with insights on their performance limitations and scalability considerations. The performance metrics that are required for optical switches to truly emerge in datacenters are discussed and summarized, with special focus on the switching time, cost, power consumption, scalability and optical power penalty. Furthermore, the Pareto front of the switch metric space is analyzed. Finally, we propose a hybrid integrated switch fabric design using the III-V/Si wafer bonding technique and investigate its potential impact on realizing reduced cost and power penalty.

We review possible architectures for 400 Gigabit Ethernet links based on advanced modulation formats for the first time. Their optical link power budget, digital complexity, and power dissipation are compared via simulations. The challenges of implementing the physical layer are discussed.

In this paper, we propose a faster-than-Nyquist (FTN) non-orthogonal frequency-division multiplexing (NOFDM) scheme for visible light communications (VLC) where the multiplexing/demultiplexing employs the inverse fractional cosine transform (IFrCT)/FrCT. Different to the common fractional Fourier transform-based NOFDM (FrFT-NOFDM) signal, FrCT-based NOFDM (FrCT-NOFDM) signal is real-valued which can be directly applied to the VLC systems without the expensive upconversion. Thus, FrCT-NOFDM is more suitable for the cost-sensitive VLC systems. Meanwhile, under the same transmission rate, FrCT-NOFDM signal occupies smaller bandwidth compared to OFDM signal. When the bandwidth compression factor $\alpha$ is set to $0.8$, $20\%$ bandwidth saving can be obtained. Therefore, FrCT-NOFDM has higher spectral efficiency and suffers less high-frequency distortion compared to OFDM, which benefits the bandwidth-limited VLC systems. As the simulation results show, bit error rate (BER) performance of FrCT-NOFDM with $\alpha$ of $0.9$ or $0.8$ is better than that of OFDM. Moreover, FrCT-NOFDM has a superior security performance. In conclusion, FrCT-NOFDM shows great potential for application in the future VLC systems., Comment: Under review of Journal of Lightwave Technology

Faster-than-Nyquist (FTN) signal achieves higher spectral efficiency and capacity compared to Nyquist signal due to its smaller pulse interval or narrower subcarrier spacing. Shannon limit typically defines the upper-limit capacity of Nyquist signal. To the best of our knowledge, the mathematical expression for the capacity limit of FTN non-orthogonal frequency-division multiplexing (NOFDM) signal is first demonstrated in this paper. The mathematical expression shows that FTN NOFDM signal has the potential to achieve a higher capacity limit compared to Nyquist signal. In this paper, we demonstrate the principle of FTN NOFDM by taking fractional cosine transform-based NOFDM (FrCT-NOFDM) for instance. FrCT-NOFDM is first proposed and implemented by both simulation and experiment. When the bandwidth compression factor $\alpha$ is set to $0.8$ in FrCT-NOFDM, the subcarrier spacing is equal to $40\%$ of the symbol rate per subcarrier, thus the transmission rate is about $25\%$ faster than Nyquist rate. FTN NOFDM with higher capacity would be promising in the future communication systems, especially in the bandwidth-limited applications., Comment: 11 pages, 11 figures

Optical transmitters typically require electrical pre-amplification using driver amplifiers to optimize the optical modulation depth. To enhance the detection sensitivity and optimize the overall link budget, equalization is required to compensate for undesired signal distortion induced by the transmitter. In this paper, we propose and demonstrate a novel optical equalization scheme using a silicon photonic micro-ring resonator (MRR)-based switching circuit for mitigating driver-amplifier-induced pulsewidth distortion. The switching circuit simultaneously functions as a spatial optical switch as well as a two-stage optical bandpass filter for optical equalization. The experimental results indicate a 4.5-dB detection sensitivity enhancement at a data rate of 12.5 Gbits/s. The proposed approach is robust to different levels of pulsewidth distortion without additional signal processing, and has possibilities to support higher data rates by adjusting the MRR parameters.

Modern data centers increasingly rely on interconnects for delivering critical communications connectivity among numerous servers, memory, and computation resources. Data center interconnects turned to optical communications almost a decade ago, and the recent acceleration in data center requirements is expected to further drive photonic interconnect technologies deeper into the systems architecture. This review paper analyzes optical technologies that will enable next-generation data center optical interconnects. Recent progress addressing the challenges of terabit/s links and networks at the laser, modulator, photodiode, and switch levels is reported and summarized.

Silicon photonics based switches offer an effective option for the delivery of dynamic bandwidth for future large-scale Datacom systems while maintaining scalable energy efficiency. The integration of a silicon photonics-based optical switching fabric within electronic Datacom architectures requires novel network topologies and arbitration strategies to effectively manage the active elements in the network. We present a scalable software-defined networking control plane to integrate silicon photonic based switches with conventional Ethernet or InfiniBand networks. Our software-defined control plane manages both electronic packet switches and multiple silicon photonic switches for simultaneous packet and circuit switching. We built an experimental Dragonfly network testbed with 16 electronic packet switches and 2 silicon photonic switches to evaluate our control plane. Observed latencies occupied by each step of the switching procedure demonstrate a total of 344 µs control plane latency for data-center and high performance computing platforms.

In recent years, there has been much interest in the development of optical switches which can route optical signals from different input guides to different outputs based on thermo-optic and electro-optic technologies. Such switches, which can be reconfigured on millisecond and microsecond timescales, have already attracted commercial interest. However switches which are able to reconfigure on the nanosecond timescales required for packet switching have been more challenging and only in recent years, have router concepts been devised to allow lossless routers to be constructed able to switch on nanosecond timescales with more than 16×16 ports. This paper will therefore review the advances that have occurred to allow such operation and then describe recent studies that have begun to determine the electronic control and functionality required to enable full and practical operation of such switches in high performance networks.

We demonstrate the first monolithically-integrated active-passive lossless 8×8 SOA switch. A wide IPDR of 14.5dB for penalty

Hybrid multiband (HMB) CAP/QAM transmitter/receiver systems are proposed for the first time. Simulation results are provided to show the feasibility of 100 Gb Ethernet links employing a single-laser source transmitting HMB CAP-16/QAM-16, CAP-32/QAM-32, and CAP-64/QAM-64 signals. The proposed hybrid scheme has low sensitivity to directly modulated laser nonlinearities. We found that QAM receivers bring about identical jitter tolerance to ideally phase compensated CAP receivers, and QAM receivers are more practical since no phase tracking and compensation are required. Compared with the case of using a standard non phase compensated CAP receiver, the use of the modified QAM-16/32/64 receiver significantly lowers system timing jitter sensitivity in the multiband, as well as single-band case. Results also show that the use of increasing number of bands causes increased system power margin. For practical jitter conditions of ±6 ps, three HMB CAP/QAM systems with optimum band counts are identified to be capable of supporting single-laser 100 Gb/s transmission over 15-km SMF.

The control tolerances of large-port-count optical switches with up to 128×128 ports using the MZI-SOA hybrid design are investigated. The first quantitative analysis is presented showing tolerant control requirements of the hybrid switch design.

A practical path-selection algorithm is proposed to optimize the worst-case path loss and IPDR for large-scale integrated switches. The modeling of an 8×8 Clos-tree switch shows an improvement of up to 2.7dB/1.9dB in loss/IPDR.

Power density and cooling issues are limiting the performance of high performance chip multiprocessors (CMPs), and off-chip communications currently consume more than 20% of power for memory, coherence, PCI, and Ethernet links. Photonic transceivers integrated with CMPs are being developed to overcome these issues, potentially allowing low hop count switched connections between chips or data center servers. However, latency in setting up optical connections is critically important in all computing applications, and having transceivers integrated on the processor chip also pushes other network functions and their associated power consumption onto the chip. In this paper, we propose a low latency optical switch architecture that minimizes the power consumed on the processor chip for two scenarios: multiple-socket shared memory coherence networks and optical top-of-rack switches for data centers. The switch architecture reduces power consumed on the CMP using a control plane with a simplified send and forget server interface and the use of a hybrid Mach-Zehnder interferometer and semiconductor optical amplifier integrated optical switch with electronic buffering. Results show that the proposed architecture offers a 42% reduction in head latency at low loads compared with a conventional scheduled optical switch as well as offering increased performance for streaming and incast traffic patterns. Power dissipated on the server chip is shown to be reduced by more than 60% compared with a scheduled optical switch architecture with ring resonator switching.

We propose the first combined 4×100Gb/s hybrid multiband CAP-16 transmitter and QAM-16 receiver system and simulations show that it has 0.7 dBo (2.2 dBo) more power margin than 8×50Gb/s (4×100Gb/s) PAM-4 over DML (EML) SMF link.

In this paper, we propose a real-valued interleaved single-carrier frequency-division multiplexing (I-SC-FDM) scheme for intensity-modulation and direct-detection optical interconnects. By simplifying the encoding structure, the computational complexity can be reduced from Nlog2N complex multiplications to N complex multiplications. At the complementary cumulative distribution function of 10-2, a reduction of 10 dB and 7.5 dB for the peak-to-average power ratio (PAPR) of the I-SC-FDM is achieved than that of orthogonal frequency-division multiplexing modulated with QPSK and 16QAM, respectively, when the subcarrier number is set to 4096. We experimentally demonstrate the I-SC-FDM scheme for optical interconnects with data rates of 12 Gbit/s, 24 Gbit/s and 128 Gbit/s transmitted over 22.5-km, 22.5-km and 2.4-km standard single mode fiber, respectively. The I-SC-FDM scheme shows great potential for cost-sensitive and power-sensitive optical interconnects owing to its low computational complexity and low PAPR.

Analysis shows that 400 GbE links using DSP-enabled 5×80Gb/s PAM-4, 4×100Gb/s hybrid CAP-16/QAM-16 and 4×100Gb/s QAM-16-OFDM have relative complexities of 1:5.4:5.7 and consume power of 0.71, 0.67 and 0.75 times that of 16×25Gb/s NRZ benchmark links.

For the first time, the feasibility of nanosecond large-scale optical switches is demonstrated using a novel MZI-SOA hybrid approach. In a filter-free recirculating loop, the potential performance of up to 128×128 port switch is demonstrated.