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ABSTRACTThe digital filters play a significant role in the field of digital signal processing (DSP). The finite impulse response (FIR) filter is an attractive choice because of the ease of design and good stability. The digital filters have a wide variety of applications such as signal processing, control systems, telecommunication, etc. They are better than the analogue filters due to their performance. In recent times, software radios have achieved attention owing to requirements for integrated and reconfigurable communication systems. Hence, reconfigurations have emerged as a significant problem in the designs of FIRs. To match the frequencies of DSP applications, higher-order FIRs are required. If length of filters rises, addition and multiplication operations also increase. This paper proposes an efficient hardware design of RFIR that employs modified bacterial foraging optimizations (MBFOs) and common sub-expression eliminations (CSEs) in its executions. MBFOs output restricted counts of filter coefficients with sums of signed-power-of-two (SPT) terms while maintaining the quality of filtered responses. On obtaining coefficients, eliminations are executed by CSEs where hardware complexities are determined in terms of adders. Model sim software validated RFIRs using the Verilog code. The proposed design of RFIRs was compared with existing designs in terms of power usages, frequencies and areas.

The topic of load balanced task scheduling has emerged as a prominent and intricate area of study within the realm of Cloud computing. Swarm intelligence-based meta-heuristic algorithms are commonly considered more suitable for the purposes of Cloud scheduling and load balancing. These algorithms employ a combination of local and global search strategies in order to ascertain the ideal location. To achieve an optimal mapping strategy for task allocation to resources, it is imperative to find a suitable equilibrium between local and global search techniques, since this approach has demonstrated significant efficacy. This research introduces a new approach to task scheduling using the Autodidactic Interactive School Optimization Algorithm (IASOA). The objective of this method is to decrease the time required for job execution while also enhancing throughput. The assessment of the suggested methodology has been executed, and a comparative analysis has been performed with five established algorithms in relation to makespan and throughput. The tests were subsequently extended to encompass a comparative analysis of the suggested methodology alongside four other established meta-heuristic scheduling methodologies. The study of the simulated experimentation reveals that the proposed approach yielded noteworthy advantages in makespan and throughput, with improvements of up to 10% and 60% respectively.

An adaptive real-time gate scheduling scheme for time perceptive stream or packet flow is proposed to improve the standards of Ultra Low Latency during data transmission. For highly dynamic network conditions, the conventional configuration scheme is not suitable and therefore an adaptive real-time gate scheduling method is proposed for time perceptive streams. This dynamicity reconfiguration is difficult and the scheduling problem is formulated using Field Programmable Gate Array – Boolean Satisfiability Problem (FPGA-BSP) solver. This proposed scheme highly helps in network dynamicity conditions with good bandwidth utilization and high flexibility. End-to-end latency is required to be on sub-milliseconds order deal with the applications such as Industrial Internet of Things, 5G and 6G mobile, tactile internet and so on. Simulation analysis is carried out to prove the efficiency of the proposed model.