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In many NAND flash-memory storage systems, invalidated pages can occupy the storage space until being erased. In order to preserve sustained write performance and effective storage capacity, the flash translation layer (FTL) must recycle these pages through garbage collection (GC) operations. Many previous studies have investigated GC techniques, most of which have focused on the effective selection of victim blocks to reduce the operational overhead. However, methods to reduce the cost overhead of the victim selection process, as well as to improve the responsiveness of storage systems during GC, have not yet been explored. In this paper, therefore, we propose a novel GC mechanism, called link-based GC (LINK-GC), which provides fast victim selection and preemptive operation with small additional space overhead to existing page-mapped FTLs. In our experiments, when compared with a GC scheme based on an on-demand victim search, the proposed mechanism increases the average input-output operations per second (IOPS) by up to 15.8% and decreases the standard deviation of IOPS by up to 6.16 times. Additionally, the LINK-GC shows better performance than the existing preemptive GC techniques in terms of responsiveness to host requests.

Due to the rapid development of flash memory technology, NAND flash has been widely used as a storage device in portable embedded systems, personal computers, and enterprise systems. However, flash memory is prone to performance degradation due to the long latency in flash program operations and flash erasure operations. One common technique for hiding long program latency is to use a temporal buffer to hold write data. Although DRAM is often used to implement the buffer because of its high performance and low bit cost, it is volatile; thus, that the data may be lost on power failure in the storage system. As a solution to this issue, recent operating systems frequently issue flush commands to force storage devices to permanently move data from the buffer into the non-volatile area. However, the excessive use of flush commands may worsen the write performance of the storage systems. In this paper, we propose two data loss recovery techniques that require fewer write operations to flash memory. These techniques remove unnecessary flash writes by storing storage metadata along with user data simultaneously by utilizing the spare area associated with each data page.

NAND flash memories have been used in many mobile consumer devices as storage media because they are small, fast, shock-resistant, and energy-efficient. However, the flash storage systems based on these flash devices need a special software layer, the FTL, to translate logical addresses from a host system to physical addresses in NAND flash memories. Recently, the flash storage systems in mobile devices tend to employ a page-level mapping scheme as they are required to yield higher access bandwidth. Unlike common SSDs, which often keep the majority of mapping information in fast but volatile DRAM, the flash storage systems in mobile consumer devices keep only a limited subset of mapping information in a small-sized SRAM due to the restrictions in size, cost, and power consumption. For this reason, many cache management schemes proposed for SSDs may not be suitable for the flash storage systems in mobile consumer devices, though most map cache management schemes used in mobile storage are basically designed for SSD. This paper proposes a novel cache management scheme targeting mobile consumer devices. The proposed scheme uses different management granularities in allocating and evacuating cache space. Experimental results show that the proposed scheme improves map cache performance by up to 36% compared to the existing cache management techniques.

NAND flash memory is widely used in many embedded systems owing to such advantages as a small size, shock resistance, and low power consumption. However, NAND flash memory has certain hardware limitations such as an "erase-before-write" constraint, which creates a long write latency. Therefore, many studies have been performed to reduce the write latency of NAND flash, one of which uses phase-changed RAM (PRAM) as a supplemental device to overcome the disadvantages of NAND flash memory. However, it is difficult to apply PRAM to storage systems owing to its limited density and high cost per capacity. To solve this problem, a novel management scheme for PRAM/NAND flash hybrid storage is proposed. Our proposed method uses limited PRAM space more efficiently by reducing the size of the data to be stored through an efficient compression scheme using differential values and rates. In addition, the proposed method improves the performance and durability of storage systems by efficiently reducing the flash program operation. Our experiments show that the proposed scheme can improve the performance and durability of PRAM/NAND flash hybrid storage with only slight increases in hardware costs.

Recently, NAND flash memory has been widely adopted as a storage medium in various devices such as mobile phones, MP3 players, and digital cameras. In particular, Solid State Drives (SSDs), which are composed of multiple NAND flash memories, have gradually replaced hard disk drives (HDD). However, SSDs have an inherent weakness stemming from NAND flash memory and its complex architecture. This phenomenon makes it difficult to analyze and optimize the performance of SSD controllers. To overcome this weakness, highly accurate system simulations are needed for exploring architectural parameters to maximize the performance during the design phase. In this paper, we implement a simulator that considers all of the hardware components in SSD to assist in generating quantitatively accurate analysis when an algorithm or controller is realized. This simulator models the detailed characteristics of hardware components such as operation clock frequency and resource conflicts in order to represent SSD in great detail. In the experiments section, we verify the impacts of interface speed, page size, and other configuration parameters by using this cycle accurate simulator. These analysis results can then be used as raw data for optimization.

The popularity of NAND flash memory has been growing rapidly in recent years, but the SSD (Solid-State Disk) has shown limited success in its battle against the hard disk. Besides the high price, SSD suffers performance degradation under random write requests, due to the intrinsic weak points of NAND flash: erase-before-write, asymmetric read/write access time, and limited program/erase cycles. In order to overcome these drawbacks, many buffer replacement algorithms have been proposed. However, considering the cost of write operations, it would be beneficial to have dirty pages updated before being flushed to flash memory. In this paper, we propose a new buffer management scheme to retain write-intensive pages in the buffer, and we confirm its effectiveness by applying it to one of the existing buffer management schemes. The simulation results indicate that the proposed scheme reduces up to 30% of the write count, and, therefore, extends the lifetime of NAND flash memories.

NAND flash memory has attractive features compared to hard disk drives such as small size, no mechanical noise and shock resistance. But it also has some drawbacks such as no support for in-place updates and limited program/erase cycles, which trigger the development of sophisticated buffer management algorithms in order to reduce write and/or erase operations to flash memory. The significant gap in update frequency between hot and cold data motivates us to separate hot and cold data on different flash blocks to avoid unnecessary program/erase cycles. Many buffer management algorithms determine a request to be hot or cold based on its requested data size. However, the data size could become a wrong indicator of update frequency in many applications. In this paper, we propose a new hot/cold identification scheme in order to increase identification accuracy and, thus, to enhance storage performance and durability by reducing program/erase cycles. The proposed technique uses the process identification used in many operating systems as a hot/cold indicator. The experimental results show that the proposed scheme contributes to high performance and durability as compared to previously proposed identification schemes.

The use of NAND flash memory for building permanent storage has been increasing in many embedded systems due to idiosyncrasies such as non-volatility and low energy consumption. The persistent requirements for high storage capacity have given rise to the increase of bit density per cell as in multi-level cells but this has come at the expense of performance and has resulted in degradation of durability. In this paper, we introduce a complementary approach to boost the performance and durability of MLC-based storage systems by employing a non-volatile buffer that temporarily holds the data heading to MLCs. We also propose algorithms to efficiently eliminate unnecessary write and erase operations in MLCs by performing a pre-merge in the buffer. Our experiments show that the proposed approach can decrease average response time by up to 4 times and increase durability by 4 times by adding only a small hardware cost.

This study proposes a compact broadband 180° Wilkinson divider which is composed of rightand lefthanded (RH-LH) transmission lines and an additional λ/2 transmission line to realise a 180° phase difference. In order to reduce the circuit size while maintaining the required broad band performance, all the transmission lines with positive or negative electrical lengths in the sub-compact 180° Wilkinson divider are realised by means of double-sectioned structures using π-type lumped passive networks, except for the λ/2 transmission line. The compact divider has a lumped passive realisation, even for the λ/2 transmission line in order to further reduce the size. The measured bandwidths of the conventional 180° Wilkinson divider, the conventional 180° Wilkinson divider using LH transmission lines, the semi-compact divider and the proposed compact divider, for the given specifications of 1 dB loss, 0.5 dB magnitude difference and 10° phase imbalance between the two output ports, are 240 MHz, 840 MHz, 1.06 GHz and 950 MHz, respectively. The proposed compact divider has a 89.2% reduction in the circuit size, compared to the conventional 180° Wilkinson divider.