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In this brief, we present an embedded picoampere-level leakage current sensor of low hardware complexity for quantum computing applications. It senses a leakage current on capacitors comprising a capacitive DAC (CDAC) intended for the control of energy confinement levels and quantum states of a nearby quantum dot structure integrated on the same die. As the quantum states exhibit an exponential sensitivity to the control voltages, any changes in the output voltage of the CDAC due to noise, ripples or leakage current should be monitored and characterized accurately. For this purpose, we exploit a 1-bit continuous-time comparator to digitize the slope of the CDAC output voltage due to the leakage current. The proposed system occupies 0.013 mm2 and measures the leakage current over varied temperature from 3.8 K to 270 K. The average leakage current of the CDAC at 3.8 K was measured at 3.57 pA.

This brief presents a 2-stage, low-power, millimeter-wave (mm-wave) LNA that aims at first to reduce its passive area through a transformer formed with inductors between the gate and source sides of the input transistor in a source-degenerated cascode. While reducing the passive area, the introduced transformer creates a magnetic feedback that further reduces the LNA’s noise figure (NF). We provide a theoretical analysis of this feedback-based noise reduction method and validate it with simulations and experimental results. The LNA has been fabricated in 22-nm FD-SOI CMOS and has a core area of only 0.09 mm2. The measurement results show that this design achieves a minimum 2.1 dB NF and a maximum 23.1 dB gain between 23.7–28.5 GHz at a power dissipation of only 5.6 mW from a 0.6V supply. Furthermore, despite using only a 0.6V supply voltage, IIP3 can still reach −16.5 dBm at 28 GHz. Targeting mm-wave 5G applications, the presented LNA is among the best-in-class with a sub-1V supply voltage.

This paper presents a simple yet effective $G_{m}$ -boosting technique for improving gain and noise performance of millimeter-wave (mm-wave) low-noise amplifiers (LNAs) comprising triple-well transistors typically found in the modern bulk CMOS processes. The proposed technique uses a resistor that connects the p-well and deep n-well terminals of the triple-well transistor, leaving the terminals floating instead of conventionally connecting them to the ground and supply voltage. This arrangement exploits a leakage current through a diode formed between the drain/source and p-well of each transistor, thus autonomously setting its bulk potential for increased transconductance, while ensuring its robustness to the process variation. The improved isolation between the p-well and the substrate further improves the gain and noise performance. We provide a theoretical analysis of this floating resistor-based body biasing method and support it with simulation results. For experimental validation, a two-stage cascode LNA was designed and fabricated in 28-nm bulk CMOS. The measurement results show that 3.3–4dB noise figure (NF) and 19.1–16.1dB gain are achieved at 24.7–29.5GHz. To ensure a fair comparison, another identical LNA with the normally expected triple-well biasing was also fabricated. The proposed method reveals a 0.6dB improvement in minimum NF and an additional ~3.5dB gain without any significant linearity degradation.