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This paper explores the design and hardware efficient realization of low complexity filter bank-based reconfigurable channelizers suitable for wireless receivers. The reconfigurability is achieved by deriving a set of non-uniform filter banks with different sampling factor combinations from a low complexity partial cosine modulated uniform filter bank, by combining different number of its neighbouring channels. The hardware complexity comparison of the filter bank channelizer designed by the proposed approach, with the existing works proves that this approach requires less number of multipliers in its realization to extract the same set of communication standards. To reduce the power and complexity of the multipliers needed for the hardware realization of the filter coefficients, an approximation algorithm, which increases the zeros in the binary represented filter coefficients is employed. The synthesis results show that the algorithm offers a considerable reduction in the hardware and power consumptions of the filter bank.

This paper proposes the realization of perceptual wavelet approximation of Bark scale using a linear-phase integer decimated non-uniform filter bank (IDNUFB), designed by merging the channels of a partially cosine-modulated uniform filter bank. In effect, the channels with different sampling factors of the IDNUFB can be derived from the same prototype filter using the proposed method of design. Also, the proposed IDNUFB is employed for the realization of Bark frequency partitioning. The proposed method of IDNUFB design using PCM and merging is found to have linear-phase property and reduced hardware complexity, when compared to the existing filter bank-based methods for Bark frequency partitioning.

This paper proposes the design and analysis of different rational decimated non-uniform filter banks (RDNUFBs), in which channels with different rational sampling factors are derived by merging the channels of an initial RDNUFB. The feasibility of the merged RDNUFB is analyzed in terms of frequency selectivity, aliasing cancellation, phase distortion, and amplitude distortion. The necessary conditions for the resultant filter bank to be alias free and to possess the linear phase property, are derived. The proposed reconfigurable RDNUFB is deployed to extract various communication standards in the software defined radio (SDR) channelizer, and is found to reduce the hardware complexity when compared to other filter bank based SDR channelizers, when a large number of channels are extracted.

In this brief, a power efficient reconfigurable non-maximally decimated filter bank-based modified frequency response masking technique is proposed to generate sharp transition width channels for wideband applications. The structure enables cost and power efficient processing of wideband signals. The main benefit of the proposed scheme is that the computational workload and hardware complexity of the modified frequency response masking technique is considerably less than that of the approaches existing in the literature. The hardware complexity of the design is further reduced by joint optimization of all the canonical signed digit represented filters using Pareto-based meta-heuristic algorithm.

Digital hearing aids can be made less expensive if they are reconfigurable and of low hardware complexity. Hence, this work proposes a hardware-efficient, reconfigurable filter bank structure, based on fractional interpolation. The proposed structure is reconfigurable since a single structure can be used for different patients with different types of hearing impairments. The proposed structure consists of a masking stage and a scheme generation stage with a prototype filter in each stage. The prototype filters are made multiplier-less by representing their coefficients in the CSD space. The filter characteristics are improved by deploying a MOABC optimization algorithm. The number of adders is reduced using the SIDC-CSE technique. The low-complexity structure can be used for all types of hearing impairments, with the matching error and delay within tolerable ranges. The proposed structure has been implemented on an FPGA to support the analytical results for low hardware complexity and hence low power.

In this paper, two reconfigurable architectures based on frequency-response masking (FRM) and non-maximally decimated filter bank system are proposed. The proposed methods are suitable for sharp wideband channelizers. The basic FRM structure consists of an interpolated modal filter and its masking filters. In both the proposed methods, the masking filters are synthesized by means of reconfigurable non-maximally decimated polyphase filter bank system. The second proposed method also exploits the LTI property of the FRM filter. The methods are beneficial when the number of bandwidths to be realized is large. The effective reduction in the multipliers and adders helps in reducing the hardware size. Both the methods are found to reduce the number of operations per second and hence the power consumption, when compared to the existing methods.

This paper proposes a reconfigurable digital filter bank structure, which is suitable for designing hearing aids for most types of hearing losses. The proposed structure exploits the fractional interpolation and symmetry property of linear phase filters. The structure has two stages; the first one is called masking stage and the second one is called multiple passbands generation stage. The second stage i.e., multiple passband generation stage has 2 levels. By adjusting a 7-bit control signal, different sub-bands generated by the two stages can be obtained for audiogram matching. The number of sub-bands can be increased by increasing the number of fractional interpolated filters in level 2 of the multiple passbands generation block. Using the proposed structure, various types of audiograms can be matched with acceptable delay and matching error. The merits of the proposed structure are low hardware complexity and good audiogram matching with tolerable matching error and acceptable delay, when compared to the state of the art techniques for audiogram matching. Moreover, it is a reconfigurable structure. FPGA implementation of the proposed structure is also done to supplement the theoretical claim for low hardware complexity and power.

The significant advantage of modified discrete Fourier transform (MDFT) filter banks over the conventional discrete Fourier transform (DFT) filter banks is the structure inherent alias cancellation in the former. When the number of channels is increased, the filters in the filter bank need to be of sharp transition width. This increases the complexity of the filters and hence that of the filter bank. Frequency Response Masking (FRM) approach is known to reduce the complexity of sharp transition width filters. This paper proposes a method to realize MDFT filter banks using FRM with much lesser complexity. To further reduce the complexity, the filter banks are made totally multiplier-less. This is done by converting the coefficients to the canonic signed digit (CSD) representation. Metaheuristic algorithms are used to improve the performance of the CSD represented filter banks. Modified integer coded genetic algorithm, differential evolution, artificial bee colony, harmony search and gravitational search algorithms are proposed to be used for the optimization of the proposed multiplier-less MDFT filter banks. This design method reduces the complexity, power consumption and chip area for the implementation of the uniform filter banks.

Reconfigurable non-uniform channel filters are now being widely used in software define radio (SDR). The hardware implementation of these filters requires low complexity, low chip area and low power consumption. The frequency response masking (FRM) approach is proved to be a good candidate for the realization of a sharp digital finite impulse response (FIR) filter with low complexity. To reduce the complexity further, this paper gives an optimal design method which makes the channel filters totally multiplier-less. This is done in two steps. The channel filters are designed using the FRM approach with continuous filter coefficients. To obtain multiplier-less design, these filter coefficients are converted to finite-precision coefficients using signed power of two (SPT) space and the filter coefficients are synthesized in the canonic signed-digit (CSD) format. But this may lead to degradation of the filter performance. Hence the filter coefficients synthesis in the CSD format is formulated as an optimization problem. Several meta-heuristic algorithms like Differential Evolution (DE), Artificial Bee Colony (ABC), Harmony Search Algorithm (HSA) and Gravitational Search Algorithm (GSA) are modified and deployed and the best one is selected.

Low complexity and reconfigurability are reported to be the key features in a software defined radio (SDR). To obtain these features, a reconfigurable architecture based on frequency response masking (FRM) technique can be used for the implementation of the channel filters in the SDR. The frequency response masking approach is proved to be a good candidate for the realization of a sharp digital finite impulse response (FIR) filter with low complexity. To reduce the complexity and power consumption for hardware realization, a design method which makes the channel filters totally multiplierless is proposed in this paper. Continuous filter coefficients are first converted to finite precision coefficients using signed power of two (SPT) space to obtain a multiplier-less filter. The representation of the FRM filter coefficients in the SPT space can degrade the filter performance. This calls for the use of a suitable optimization technique. The classical gradient based optimization techniques cannot be deployed here, because the search space consists of integers. In this context, meta-heuristic algorithm is a good choice as it can be tailor made to suit the problem under consideration. They are especially useful in finding near optimal solutions in multimodal, multidimensional space. Several meta-heuristic algorithms are modified in this paper to be used for the discrete optimization.