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The scaling of the metal-oxide-semiconductor field-effect transistor (MOSFET) has been the driving force for the enormous increase in computational power in everyday digital electronics since the 1960's. Today, this trend is reaching its limits, as the MOSFET supply voltage can no longer be scaled at the same pace as the device dimensions. This is due to a lower limit on the subthreshold swing (SS). As a result, the power density of integrated circuits rises with each new generation, which is eventually untenable. The tunnel field-effect transistor (TFET) has been developed to break this detrimental evolution. Its operating principle based on band-to-band tunneling (BTBT) enables a low SS and hence low supply voltage operation. Silicon implementations, however, have shown insufficient ON-currents. Research is therefore turning to III-V materials, which can be combined in heterostructures. Furthermore, lineTFET configurations are being investigated in which the tunneling is oriented more orthogonal to the gate than in the standard pointTFET configurations. Standard commercial semiclassical modeling approaches are poorly suited to assess TFET performance for these new material systems and configurations. This is because they neglect quantum phenomena such as size-induced and field-induced quantum confinement, and reflections at the heterojunction. In this thesis, we therefore develop a fully quantum mechanical simulator, called Pharos, based on the multi-band envelope function formalism to simulate BTBT in direct semiconductors. Our approach allows for computationally efficient performance predictions and optimization of heterostructure TFETs, and enables the comparison between different III-V material options and configurations. We implement our formalism for a two-, fifteen-, and thirty-band model, with each subsequent model enabling the simulation of a wider variety of configurations. The two-band model is only suited to simulate pointTFETs. For this configuration, we find a counteracting effect between gate control and size-induced quantum confinement for decreasing device dimensions. The fifteen-band model is implemented with a spectral approach and enables the simulation of lineTFETs, which we compare to pointTFET configurations. We find that an optimized pocketed pointTFET has similar performance than an optimized pocketed lineTFET. We also introduce an improved source design, which brings the performance of the pTFET to the same level as the nTFET, enabling complementary logic applications. With a thirty-band model, we assess whether strain can further improve the heterostructure TFET performance. We find that uniform strain can improve the ON-currents of heterostructure TFETs, if our improved source design is applied. We also assess non-uniform strain profiles which arise at a lattice-mismatched heterojunction and find that the lattice mismatch can be used as an additional design parameter to enlarge the TFET design space. We also develop a self-consistent procedure, which couples the calculated charge density to the electrostatic potential using a Gummel scheme for Poisson's equation. This allows us to identify the impact of quantum effects on the electrostatic potential. We find that self-consistent simulations are required for strongly confined structures. Finally, we report on simulations done during a research stay at Purdue University in IN, USA, which compare the sensitivity to electron-phonon scattering in conventional heterostructure TFET and resonant TFET configurations. We find a larger sensitivity for the resonant TFET, although it still offers superior performance to the conventional configuration. status: published

© 2017 IEEE. I. Introduction The growing demand for power efficient devices has accelerated the research into the use of the tunnel field-effect transistor (TFET) in future ultra-low power applications because of its promising potential for sub-60 mV/dec subthreshold swing achieved through quantum mechanical band-To-band tunneling (BTBT) [1]-[3]. Unfortunately, a significant gap between theoretical predictions and experiments remains to be bridged [2]. Considerable efforts are being made to develop models for some of the main causes of suboptimal TFET performance such as trap-Assisted tunneling (TAT) [4], [5], phonon-Assisted tunneling (PAT) [6], and Auger generated leakage currents [7]. However, aside from qualitative analyses [8] and purely predictive work on the device impact of tunneling transitions involving high-doping induced band-Tails states in InSb nanowire TFETs [9] and 2D-TFETs [10], no attempts have been made to calibrate these contributions. This work aims to fill this gap by developing and calibrating an approximate ballistic semi-classical (SC) model for high-doping induced band-Tails using the experimental I-V data of In0.53Ga0.47As p-i-n Esaki diodes [11]. The hypothesis is posited that the mismatch between measurement and simulation in the negative differential resistance regime (see Fig. 1), which cannot be explained by SC TAT models, is caused by ballistic band-Tails tunneling. The calibration thus gives an upper limit to the band-Tails current. Lastly, the impact of band-Tails on the performance of a p-n-i-n TFET is investigated. ispartof: Fifth Berkeley Symposium on Energy Efficient Electronic Systems and Steep Transistors Workshop vol:2018-January ispartof: Fifth Berkeley Symposium on Energy Efficient Electronic Systems and Steep Transistors Workshop location:Berkeley, CA USA date:10 Jan 2017 status: published