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Always-on keyword spotting (KWS) hardware is gaining popularity in ultra-low power IoT applications where specific words are used to wake up and activate the power hungry downstream system. This work proposes a low power KWS engine with a power-optimized Mel-frequency cepstral coefficients (MFCC) feature extraction module and a memoryoptimized long short term memory (LSTM) accelerator. Our LSTM model is pruned and compressed to reduce 89% of model size and 76% of computation. The LSTM accelerator adopts the weight stationary dataflow to reduce energy. Our simulation using a 40nm CMOS process achieves a power consumption of 2.51 μW, which is at least 2× lower than the state-of-the-art.

In recent years, fast computation, low power, and small footprint are the key motivations for building SNN hardware. The unique features of SNN hardware have not been fully exploited, where the computation speed and energy efficiency of the SNN hardware can be improved according to the sparse spiking and non-uniform traffic of SNN. In this paper, we propose a 5.28-mm² 4096-neuron 1M-synapse energy-efficient digital SNN hardware that can achieve ultra-low energy per synaptic operation of 4.5 pJ. The proposed neuron computing unit is implemented in pipeline architecture to achieve high synaptic processing speed. The proposed spike processing unit can significantly increase the processing speed of the neuron core by 1.9x and 9.4x when the spike injection rate is 50% and 10%, respectively. Besides, the increase in the processing speed of the neuron core leads to a reduction in energy consumption of up to 81.5%. An event-driven clock gating circuit that can reduce the power consumption of the proposed neuron block by more than 70% is proposed in this paper. This paper proposes a supervised STDP+ algorithm for SNN training, and the classification accuracy of the MNIST digits is 89.6% with 73.6% weight sparsity of the output layer.

This brief presents a neuromorphic processor with asynchronous routers and configurable LIF neuron models. The neurocore microarchitecture revolves around a high- $V_{th}$ SRAM to reduce leakage, alongside reconfigurable neuron compute logic circuits and async routers to maximize energy efficiency. The neuron compute module achieves low power via an area efficient ALU implementation by using only adder and bitshifter circuits. We describe this LIF neuron model ALU design, and also include key neurocore verification scenarios (i.e., router deadlocks and functional coverage), CPU-neurocore control flow, and asynchronous router performance analysis. Our 16-core fabricated chip in 40 nm CMOS process works down to 0.5V. The measured leakage and average energy efficiency are $0.93~\mu \text{W}$ /core and 4.8 pJ/SOP respectively (at 0.5V), which is 20% better than state of the art.

With the ability to generate different spiking patterns, Izhikevich model has well been considered a computationally efficient and biologically plausible neuron model for applications such as brain dynamic behavior study. This brief presents a low-cost, high-throughput digital hardware design for Izhikevich neuron model. The proposed design requires only addition, subtraction and logic shifts operations to achieve the low hardware cost. The dynamic behaviors of both the proposed neuron model and the original Izhikevich model were analyzed using the phase portraits. The FPGA implementation results demonstrated that the proposed design can reproduce different spiking patterns with very high throughput. Compared to existing designs, the proposed design achieves the lowest slices and LUTs utilization, which are 73% and 11% lower than the latest design (HOMIN), respectively.

Neuromorphic (NC) designs have gained significant interest in recent hardware research due to its low-power consumption. Low-power and low-latency router design is one of the most critical component to ensure NC hardware’s scalability and energy efficiency. Various router designs have been proposed to achieve high performance. However, this leads to complex router architectures and thus high area and power consumption. Furthermore, non-uniform traffic patterns of spiking neurons can cause network congestion and unnecessary power consumption. In this brief, we propose a congestion-aware routing algorithm to alleviate the congestion of routers in the middle and reduce network latency. Besides, a globally asynchronous, locally synchronous low-cost router architecture is deployed to relax the global clock tree constraint at chip level. Finally, a novel clock gating circuit is proposed to reduce the dynamic power consumption of routers. Our results show that averagely it reduces the router power consumption by more than 50%. The proposed router achieves ultra-low energy consumption of $2.3\times 10^{-2}$ pJ/bit and a small area of only 0.007 mm2.

Activation functions such as hyperbolic tangent (tanh) and logistic sigmoid (sigmoid) are critical computing elements in a long short term memory (LSTM) cell and network. These activation functions are non-linear, leading to challenges in their hardware implementations. Area-efficient and high performance hardware implementation of these activation functions thus becomes crucial to allow high throughput in a LSTM accelerator. In this work, we propose an approximation scheme which is suitable for both tanh and sigmoid functions. The proposed hardware for sigmoid function is 8.3 times smaller than the state-of-the-art, while for tanh function, it is the second smallest design. When applying the approximated tanh and sigmoid of 2% error in a LSTM cell computation, its final hidden state and cell state record errors of 3.1% and 5.8% respectively. When the same approximated functions are applied to a single layer LSTM network of 64 hidden nodes, the accuracy drops by 2.8% only. This proposed small yet accurate activation function hardware is promising to be used in Internet of Things (IoT) applications where accuracy can be traded off for ultra-low power consumption. Accepted version We thank the Programmatic grant no. A1687b0033, Singapore RIE 2020, AME domain.

High performance but computationally expensive Convolutional Neural Networks (CNNs) require both algorithmic and custom hardware improvement to reduce model size and to improve energy efficiency for edge computing applications. Recent CNN architectures employ depthwise separable convolution to reduce the total number of weights and MAC operations. However, depthwise separable convolution workload does not run efficiently in existing CNN accelerators. This paper proposes an energy-efficient CONV unit for pointwise and depthwise operation. The CONV unit utilizes weight stationary to enable high efficiency. The row partial sum reduction is engaged to increase parallelism in pointwise convolution thereby lightening the memory requirements on output partial sums. Our design achieves a maximum efficiency of 3.17 TOPS/W at 0.85V/40nm CMOS which is well-suited for energy constrained edge computing applications. Accepted version

This paper presents a real-time image acquisition system with an improved image quality assessment module to acquire high-quality near infrared (NIR) images. Thermal imaging plays a vital role in a wide range of medical and military applications. The demand for high-throughput image acquisition and image processing has continuously increased especially for critical medical and military purposes where executions under real-time constraints are required. This work implements an NIR image quality assessment module, which utilizes improved two-dimensional entropy and mask-based edge detection algorithms. The effectiveness of the proposed image quality assessment algorithms is demonstrated through the implementation of a complete finger-vein biometric system. The proposed model is implemented as an embedded system on a field programmable gate array prototyping platform. By including the image quality assessment module, the proposed system is able to achieve a recognition accuracy of 0.87 % equal error rate, and can handle real-time processing at 15 frames/s (live video rate). This is achieved through hardware acceleration of the proposed image quality assessment algorithms via a novel streaming architecture.

The internet is an insecure medium and hence, there is an increasing demand for measures to guarantee data privacy and integrity in the associated computer systems and networks. However, data protection and network security comes at a very high cost in the supporting embedded systems. While there are freely available solutions such as the OpenSSL library, the performance of most embedded processors, on their own, are just not adequate enough to perform cryptography for real-time network security applications. In this paper, we focus on the implementation of a cryptographic (crypto) embedded system, deploying an Altera Nios II embedded processor working with an AES encryption hardware accelerator. The RTOS applied is uClinux, on which the OpenSSL library has been ported and cross-compiled. Experimental results show that hardware acceleration can improve, significantly, the performance of OpenSSL crypto functions and hence, of the SSL connection as well.