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The design of gate drivers for silicon carbide (SiC) power mosfets needs to address various adverse effects induced by the parasitic inductance in the gate loop, such as false turn-on, gate overstress, and reduced switching speed. In this work, a single-polarity gate driver design featuring a low-voltage (LV) gallium nitride (GaN) high-electron-mobility transistor (HEMT) for Miller clamping is presented. The lateral LV GaN HEMT can switch at a much higher speed than that of the SiC mosfet, so that the proposed gate driver can well suppress false turn-on with a user-friendly off-state gate voltage of 0 V. Meanwhile, the reverse-conduction characteristics of the LV GaN HEMT allow the clamping of negative voltage spikes to protect the SiC mosfet against gate overstress, which is shown to be detrimental to the gate reliability. In addition, the LV GaN HEMT can accelerate the turn-off process and suppress the gate-loop oscillation, thereby further reducing the switching loss, as verified by experiment results.

The human-body-model (HBM) electrostatic discharge (ESD) robustness can be directly evaluated through the ESD simulator designed for product qualification or indirectly by the transmission line pulse (TLP) I–V system. Although the TLP test can be used to estimate drain-to-source HBM ESD robustness of Si mosfets, it causes misleading estimation for GaN HEMTs. To understand this miscorrelation, the behaviors of 100-V Schottky-type p-GaN gate HEMTs and Si mosfets under HBM ESD tests are characterized and compared in this work, especially the rise time (tR) of terminal voltages in the devices. In drain-to-source ESD of the Si mosfet and gate-side ESD of the GaN HEMT, the high leakage current and the device voltage clamping result in short tR (∼10 ns) and strong ESD robustness. In most other HBM ESD tests, the two devices behave like variable capacitors with long tR (>100 ns) due to the insignificant leakage current. Moreover, the breakdown voltage of GaN HEMTs is dependent on the voltage stress time. Since the appropriate HBM–TLP correlation is based on the assumption of short tR and weak time dependence of device breakdown, the TLP I–V test is not suitable for HBM ESD robustness evaluation of GaN HEMTs. Instead, a more accurate and simpler estimation of HBM ESD robustness can be realized by a versatile pulse I–V system with adjustable tR.

The planar nature of the GaN heterojunction devices provides extended dimensions for implementing monolithic power integrated circuits. This article presents a comprehensive review of the advancements in GaN power integration. Basic building blocks in a power integration platform based on p-GaN gate HEMT technology are discussed, including high- and low-voltage transistors, lateral field-effect rectifiers, resistors, and capacitors. Exemplary designs of monolithic gate driving circuit and detection/protection circuits based on this platform are demonstrated. Technologies to address other challenges, including the lack of mature complementary logic (CL) and the substrate-induced crosstalk effect, are also demonstrated. More forward-looking development of power integration based on wide bandgap semiconductors is also presented in a hybrid GaN/SiC field-effect transistor that is expected to harness the complementary merits of GaN and SiC, and ON-chip GaN-based nonvolatile memory device that could provide versatile intelligence.