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In this work, a charge-based memristor emulator is designed using a single active current mode component Differential Voltage Current Conveyor Transconductance Amplifier with one capacitor and two resistors as passive components. Importantly, the proposed circuit topology can be changed to either grounded or floating configuration using a single switch. Moreover, the proposed memristor design can be operated either in incremental or decremental configuration by using another switch. Therefore, using only two switches, the same circuitry can be utilized to design the floating/grounded incremental/decremental memristor. The pinched hysteresis loop area can be controlled by applying different biasing voltages. Further, the mathematical analysis is performed to drive the theoretical TiO2 based results for the proposed memristor emulator. In addition, simulations confirming the theoretical analysis are conducted in PSPICE using the 180 nm TSMC technology with a supply voltage of ± 0.9 V by varying frequencies and capacitances to obtain a pinched hysteresis loop. The presented circuit performs effectively for frequencies upto 500 MHz while operating with grounded type memristor and 300 MHz with floating type design. To check the ability to remember the history of the proposed memristor, the non-volatility test is performed for both the incremental and decremental configurations. Moreover, the suggested memristor design is applied in an adaptive learning circuit to prove its feasibility in neuromorphic applications. [ABSTRACT FROM AUTHOR]

This paper presents a current-mode VCSEL driver (CMVD) implemented using 180 nm CMOS technology for application in short-range LiDAR sensors, in which current-steering logic is suggested to deliver modulation currents from 0.1 to 10 mApp and a bias current of 0.1 mA simultaneously to the VCSEL diode. For the simulations, the VCSEL diode is modeled with a 1.6 V forward-bias voltage and a 50 Ω series resistor. The post-layout simulations of the proposed CMVD clearly demonstrate large output pulses and eye-diagrams. Measurements of the CMVD demonstrate large output pulses, confirming the simulation results. The chip consumes a maximum of 11 mW from a 3.3 V supply, and the core occupies an area of 0.1 mm2. [ABSTRACT FROM AUTHOR]

Log and Antilog Amplifiers are two very important functions in many electronic devices. Thus, in this article a new current mode (CM) log and antilog amplifier using current follower transconductance amplifier (CFTA) are presented. The logarithmic circuit is constructed using only one CFTA as active elements and one metal oxide semiconductor (MOS) transistor as diode operation and antilogarithmic amplifier circuit is implemented using only one CFTA as the active component, one MOS transistor as diode operation and two MOS transistor as active resistors. It provides the advantage of using MOS transistor instead of a resistor and diode that is beneficial to IC implementation in terms of space consideration which are suitable for IC implementation. These circuits provide logarithmic and antilogarithmic responses. Additionally, there is no demand to set selection criteria for components. The operation of the circuit in the current mode was verified by a nonideality study. PSPICE was used to test the scheme's functioning. The output curves coincide very close with the theoretical expectation. [ABSTRACT FROM AUTHOR]

Recent developments in multiplication circuits with fewer transistors, higher speed, and reduced energy consumption are lowering hardware costs. Approximate multiplication is used for fault-tolerant applications, such as image and signal processing. These applications offer considerable improvement at the cost of reduced accuracy. Compressors are the main component of any multiplier structure. In this work, the design of an approximate multiplier based on current mode, using 4:2 and 5:2 approximate compressors and current over scaling technique is suggested to reduce power consumption, delay, and hardware components compared to existing architectures. In the proposed approach for the design of compressor circuits, current mode binary converters with 32 nm CNTFET technology are used. This work is done in three steps: (1) converting input currents into voltage and creating multi-level voltages. (2) Implementing voltage level detector. (3) Generation of output current based on threshold voltage. The proposed technique uses less number of transistors. The simulation was done under HSPICE software and the efficiency of the compressors was compared in terms of delay, power, and power delay product (PDP). Based on the simulation results, the PDP value for 4:2 and 5:2 compressor circuits is calculated as 0.0097 and 0.0131 fJ, respectively. Then, an approximate multiplication of 8 × 8 using these compressors is designed for multiplying images under MATLAB software. This multiplier has achieved a good improvement in terms of PSNR and MSSIM (respectively 9.14 and 2.85%) compared to advanced approximate multipliers. Also, the proposed approach performs better in terms of accuracy, power consumption, and delay. [ABSTRACT FROM AUTHOR]

An adaptive biased architecture of voltage differencing transconductance amplifier (AB-VDTA) with high transconductance gain is proposed in this paper. The proposed AB-VDTA is very efficient in terms of power. The structure proposed involves of two units namely two transconductance amplifiers (TAs) and two squarer. The bias current of the TA is made to vary with a square relation of the differential input voltage. Therefore, the proposed structure provides tunable gain depending on the input differential voltage. The proposed AB-VDTA exhibits improved transconductance gain, transient characteristics, reduced standby power dissipation and linearity for large range of inputs. The mathematical formulation has been presented to establish the characteristics of the proposed AB-VDTA. The proposed structure of AB-VDTA is validated through SPICE simulations using 180 nm complementary metal oxide semiconductor (CMOS) technology. The proposed scheme has an edge over the existing ones as the outlined methods enhance the transconductance gain by increasing the bias current. The g m 1 values are observed to be 2.3 and 1.4 mS for proposed AB-VDTA and conventional VDTA, respectively, with the corresponding 3 dB frequencies 620 and 348 MHz. Therefore, 64% improvement in transconductance gain is recorded for same value of bias currents. The linear input range of TA1 is observed to be ± 1 5 0 mV and the overall linear range of the VDTA is ± 1 0 0 mV for the proposed AB-VDTA. The PVT analysis is carried out to show the effect of process corners. To check the robustness of the proposed VDTA, Monte Carlo analysis is performed, and results have been included in the form of histograms. As an application example, a current mode (CM) universal single input multiple output (SIMO) biquad filter is also designed using the proposed VDTA to show its usefulness, and a 2.7 times higher pole frequency is obtained at equal bias current. [ABSTRACT FROM AUTHOR]

In the analog and mixed-signal integrated circuits, voltage references that are independent of various factors such as temperature drift, noise, supply voltage, etc., and efficient in terms of power as well as area, are highly in demand to improve the efficiency of the overall circuits. Voltage references are one of those circuits that have applications in both high-power systems and low-power system-on-chip (SoC) designs for wireless connectivity like the internet of the things (IoT) or the internet of the medical things (IoMT). They are responsible for providing a stable bias or reference voltage. Thus, voltage reference influences directly or indirectly the performance of these systems. A comparative study between the techniques used in bandgap voltage references and CMOS voltage references, in terms of performance parameters such as line sensitivity, output noise, PSRR, temperature coefficient, etc., is presented in this paper so that we can choose the voltage references as per the applications and environment. [ABSTRACT FROM AUTHOR]

This paper presents a current-mode VCSEL driver (CMVD) implemented using 180 nm CMOS technology for application in short-range LiDAR sensors, in which current-steering logic is suggested to deliver modulation currents from 0.1 to 10 mApp and a bias current of 0.1 mA simultaneously to the VCSEL diode. For the simulations, the VCSEL diode is modeled with a 1.6 V forward-bias voltage and a 50 Ω series resistor. The post-layout simulations of the proposed CMVD clearly demonstrate large output pulses and eye-diagrams. Measurements of the CMVD demonstrate large output pulses, confirming the simulation results. The chip consumes a maximum of 11 mW from a 3.3 V supply, and the core occupies an area of 0.1 mm2.

This work presents a flux-controlled memristor structure employing a Current-Controlled Current Differencing Transconductance Amplifier (CCCDTA) with a grounded capacitor. The proposed emulator's invariant and variant parts can be safely adjustable, showing promising characteristics of up to 1.5 MHz operating frequency. Furthermore, there is no need for an additional circuit, switching mechanism or changing the circuit topology for the changing of operation modes. To justify the performance of the emulator with incremental and decremental mode operations, a Monte Carlo and temperature analysis are validated using TSMC 0.18 µm technology under a symmetrical supply voltage of ±0.9 V. Furthermore, the workability of the proposed circuit is tested with commercial elements such as ALD1116, AD844 and LM13700. When compared with other studies, the presented emulator circuit demonstrates promising performance in various features. [ABSTRACT FROM AUTHOR]

In this study, a novel DDCC-based two-integrator-loop universal active-C biquad with a companding process scheme is proposed. The proposed filter employs some processing blocks such as integrators and summing blocks. The use of the block diagram design procedure is attractive and systematic. The state space synthesis technique is utilized for the topology of the integrator design. Several advantages of the proposed filter are briefly expressed as: simultaneously realizing five second-order filter functions such as low-pass, high-pass, band-pass, all-pass and notch filter responses; offering resistorless realization; dissipating low power; having electronic tunability feature of its pole frequency and quality factor orthogonally; not suffering from disadvantages of the passive element matching problems. Some simulation results including frequency and time domain analysis results by using the PSpice program are carried out to confirm the theoretical ones. All the obtained simulation results are discussed. [ABSTRACT FROM AUTHOR]

This work presents a new active block called the differential current conveyor cascaded transconductance amplifier (DCCCTA) and implemented multi-mode biquadratic universal shadow filter. The frequency-hopping filter is implemented using a multi-mode universal shadow filter. The proposed circuit has two modes of operation: current mode (CM) and transadmittance mode (TAM). All-pass (AP), band-pass (BP), band-reject (BR), high-pass (HP), and low-pass (LP) responses are simultaneously accomplished. As intended, low input impedance for CM and high input impedance for TAM are acquired, while high output impedance is attained for both modes of operation. Inter-modulation distortion (IMD), percentage total harmonic distortion (%THD), and Monte Carlo analysis are also obtained. The theoretical results are verified using Cadence Virtuoso in 180 nm TSMC technology.

This paper describes a new CMOS current mode four-quadrant analog multiplier circuit. The proposed design is based on a high performance squarer cell, whose main core is realized by the up–down topology trans-linear loop using flipped voltage followers (FVF). The simulation results are verified by TSPICE simulator based on the BSIM3v3 transistor model for TSMC 0.18 µm CMOS process available from level 49 MOSIS at 25◦C with ± 0.75 V supply voltage. The proposed multiplier offers improved characteristics compared to the multipliers previously exposed in the literature. It has a wide dynamic range. The total harmonic distortion is about 0.42% at 1 kHz with peak-to-peak input current of 40 µA. The −3 dB bandwidth is more than 850 MHz and a maximum power consumption is of approximately 105 µW.

Compared to voltage mode circuits, current mode circuits have advantages such as large dynamic range, fast speed, wide frequency band, and good linearity. In recent years, the development of call flow modeling technology has been rapid and has become an important foundation for analog integrated circuits. In this paper, a current mode chaotic oscillation circuit based on current differential transconductance amplifier (CDTA) is proposed. This proposed circuit fully utilizes the advantages of current differential transconductance amplifier: a current input and output device with a large dynamic range, virtual ground at the input, extremely low input impedance, and high output impedance. The linear and non-linear parts of the proposed circuit operate in current mode, enabling a true current mode multi scroll chaotic circuit. Pspice simulation results show that the current mode chaotic circuit proposed can generate multi scroll chaotic attractors.

In a conventional current-mode dc–dc buck converter, two sensed inductor current signals are processed in three separate comparators to regulate the converter under various load conditions. These independent sensing currents and comparators not only consume large quiescent current and silicon areas but also cannot guarantee the accuracy of the current limit threshold. This article proposes a current-mode dc–dc buck converter with an accurate current limit using a multiplex pulsewidth modulation (PWM) comparator. Through a multiplex PWM comparator, only one sensing current and one comparator are required to process the inductor current information and complete the regulation of the converter under various load conditions. The response speed of overcurrent protection is also increased without consuming more power and silicon area. Moreover, by generating the zero temperature coefficient (ZTC) sensing current and adding ZTC reference current with slope compensation information, the accuracy of the current limit threshold is greatly improved under various temperatures in a wide input voltage range. The proposed buck converter with a multiplex PWM comparator was fabricated using a standard 1P3M 0.18 μm BCD (BiCMOS/DMOS) process and the experimental results show that the proposed scheme functions properly in the 5-A load range, and the current limit threshold also varies only 8.1% in the temperature range from −40 to 125 °C with the input voltage up to 60 V. [ABSTRACT FROM AUTHOR]

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This paper presents the high-output-impedance current-mode multiphase sinusoidal oscillators (MSO) using voltage differencing current conveyor (VDCC)-based lossy integrators, which consist of one VDCC, one grounded capacitor, and two grounded resistors. The proposed oscillator can provide an odd-phase and even-phase system without the use of an additional amplifier. The frequency of oscillation (FO) is electronically tuned via the bias current without affecting the condition of oscillation (CO). The proposed oscillator is designed to obtain three-phase sinusoidal waveforms (n = 3). The effect of non-idealities of VDCC on the lossy integrator section is also investigated. The validity of the proposed circuit is demonstrated by PSPICE simulation using 0.18 µm TSMC CMOS process parameters with ±0.9V power supply. The frequency of oscillation obtained from the simulation is 1.43 MHz. The total harmonic distortions of the sinusoidal output currents IO1, IO2, and IO2 are 1.22%, 1.18%, and 0.57%. The IO1–IO2 and IO2–IO3 phase differences are approximately 121 and 119 degrees, respectively. The feasibility of the proposed MSO is also verified with experimental results using the VDCC constructed from the commercially available ICs (LT1288 and AD844) with ±5 V power supply. The results of PSPICE simulations and experiments are closely consistent with the theoretical expectation. [ABSTRACT FROM AUTHOR]

This study shows the electrodeposition of Fe-Cr-Ni alloys using the advantages of a stepped direct-current deposition in a Cr(III)-containing electrolyte, and its influence on the pH value. The resulting coatings are uniform and free of microcracks, with a Cr content around 30% and thicknesses above 10 µm. The influence of the current mode (direct current, stepped direct current, pulsed current) on pH development is investigated and correlated with the arising microstructure and alloy composition. Considering the current flow, it can be stated that pauses interrupt high overvoltage and restrain the pH increase at the cathode. The associated formation of chromium hydrides and their deposition onto the chromium layer, leading to cracking, is thus reduced. In this work, direct evidence for this theory and a suggestion for near-surface pH measurement during electrodeposition are presented. [ABSTRACT FROM AUTHOR]

In this paper, a new mixed-mode first-order universal filter configuration is presented that employs three operational transconductance amplifiers (OTAs) and one grounded capacitor (eminently suitable for IC chip fabrication). All three first-order generic filter functions, namely low pass filter (LPF), high pass filter (HPF) and all pass filter (APF) in all the four possible modes, namely voltage mode (VM), current mode (CM), transresistance mode (TRM) and transconductance mode (TCM) can be realized. The proposed configuration offers high input impedance and high output impedance. The pole frequency of the filter can be controlled electronically by varying a single transconductance. Nonideal analysis of the proposed filter structure has also been carried out and the results have been compared with those obtained from ideal analysis. The performance of the presented filter configuration has been corroborated through PSPICE simulations as well as experimental results. The various simulation and experimental results validate the practical viability of the proposed configurations. [ABSTRACT FROM AUTHOR]

With rapid social and economic development, high-efficiency welding technology has become an important development direction in the field of welding. In recent years, scholars and professionals in many countries have devoted themselves to further increasing the welding efficiency by improving welding materials, welding process, and arc-welding equipment. The welding efficiency can be increased using two approaches: one is increasing the welding speed, the other is increasing the welding deposition rate. Considering these two methods, typical technologies such as multiwire submerged arc welding (SAW) and multiwire gas metal arc welding (GMAW) were proposed. A twin-arc integrated cold wire hybrid welding system was established. The mechanical effect of the cold wire position on the welding process was studied, including its effects on heating, melting, and weld surface formation. Results show that the melting of cold wire depends on the front end of the weld pool, and the melting effect of the weld pool on the cold wire is not sufficient when the cold wire is fed in front of two leading wires. The end of the cold wire makes contact with the bottom surface of the weld pool with the continuous feeding of the cold wire. Droplets melted at the wire ends are ejected and fall on the base metal surface to generate a globular spatter with the backward motion of the base metal. The thermal distribution on the side of the weld pool decreases as the cold wire is fed inside of the two leading wires. Hence, the flow of molten metal is affected, ultimately leading to an uneven weld formation. The cold wire is stably inserted into the weld pool when fed behind the two leading wires, representing the optimum cold wire position. Moreover, the deposition rates increase with an increase in the cold wire feed speed and show little change under two-pulse phase differences (in-phase and reverse-phase pulse differences). The effect of arc heating and melting on the cold wire was most intense at the in-phase pulse current, followed by the reverse-phase pulse current and subsequently direct current.

This work presents a flux-controlled memristor structure employing a Current-Controlled Current Differencing Transconductance Amplifier (CCCDTA) with a grounded capacitor. The proposed emulator’s invariant and variant parts can be safely adjustable, showing promising characteristics of up to 1.5 MHz operating frequency. Furthermore, there is no need for an additional circuit, switching mechanism or changing the circuit topology for the changing of operation modes. To justify the performance of the emulator with incremental and decremental mode operations, a Monte Carlo and temperature analysis are validated using TSMC 0.18 µm technology under a symmetrical supply voltage of ±0.9 V. Furthermore, the workability of the proposed circuit is tested with commercial elements such as ALD1116, AD844 and LM13700. When compared with other studies, the presented emulator circuit demonstrates promising performance in various features.

This study develops the control and driver for active Micro LED panel with chip-level design. The chip includes constant current circuit, digital-to-analog converter, SPI control interface, and active-matrix display control. The design process uses TSMC0.18um HVG2 CMOS technology, to realize 30 channels for micro LED driver. To reduce I/O pins, the input signals feed to the dynamic shift register in serial, and the results are loaded to the digital-to-analog converter (DAC) in parallel. The DAC module consists of R2R network, unity-gain buffer and sample-and-hold circuits. The DAC outputs with constant current for micro LED driving from voltage-to-current conversion. To reduce the number of DAC component, one DAC can share the common circuit to drive RGB LED of one pixel based on the selected current mirror structure. This chip can greatly reduce resistor and switches about 92% and 96% respectively, compared with the conventional R DAC structure. The measurements result with good linear for the current dimming control, which the test digital signals are generated by Verilog codes to estimate the gray current of this chip. [ABSTRACT FROM AUTHOR]

This article presents a novel charge-controlled memristor emulator circuit. The proposed memristor emulator utilizes a single Current Follower Transconductance Amplifier (CFTA) as an active current mode analog building block and a grounded capacitor as a passive element. The circuit presented follows all the fingerprints of an ideal memristor. It operates in both incremental as well as decremental mode. The functional performance of the emulator circuit is verified at different operating frequencies and performs well up to 9 MHz. The theoretical and non-ideal analyses are verified for the proposed emulator. Moreover, Monte Carlo sampling and non-volatility analysis are performed to investigate the robustness of the emulator circuit. The functionality of the proposed model has been verified through PSPICE simulation using TSMC 0.18 $\mu m$ CMOS technology at the supply voltage of $\pm 1.2~V$ . The experimental confirmation of the presented circuit is also performed by building a breadboard micromodel using ICs CA3080 and AD844AN. Memristor based Chua’s circuit model is included as one of its applications.

This paper presents a modified Current Follower Transconductance Amplifier (CFTA). It provides the essential features of high transconductance, wide bandwidth besides a wide linear range. It records the highest transconductance of 18.2 mS and power dissipation of 1.12 mW. Moreover, the linear range ( i F versus i x ) of CFTA is found as ± 8 0 μ A. All these essential performance parameters are found much better than the available literature. As an application, a novel second-order universal filter is implemented using the proposed CFTA. It is found that the performance of the filter improves with the use of the proposed CFTA. [ABSTRACT FROM AUTHOR]

A novel solution of a reconnection-less reconfigurable filter is being presented. The filter works in the current mode, voltage mode, and mixed mode (voltage tocurrent) offering sixteen transfer functions in total. The structure utilizes a voltage differencing transconductance amplifier, current follower and voltage, and current amplifiers. The designed structure offers the control of the pole frequency and quality factor and the adjustment of the band-stop/band-pass area of available functions. The proposed design is supported by the PSpice simulations using available simulation models.

This paper presents a non-inverting buck-boost converter for high-voltage automotive applications. The converter includes a newly proposed controller chip and four off-chip NMOS power transistors with two bootstrap capacitors. Conventional non-inverting buck-boost converters have two operation modes: the buck and boost modes. This study implements four operation modes for smooth transition between these modes. In converters with four operation modes, non-switching high-side power transistors require continuous high gate-driving voltages without the bootstrapping operation. The designed non-inverting buck-boost converter drives non-switching high-side NMOS transistors through the proposed bootstrap-sharing technique. A new current sensing technique is also proposed that works reliably under high-voltage operating conditions. This current sensing enables the converter's modulation scheme of the current programmed control. The proposed converter was fabricated using a 0.18 μm BCD 1P4M process. The total chip area is 2.50 × 2.50 mm2, including the bonding pads. The output voltage range is from 1.05 to 60 V, with a typical input automotive battery voltage of 14 V. Because the automotive battery exhibit a wide voltage fluctuation, the input voltage range is designed from 7 to 60 V. Its switching frequency range is from 600 to 1000 kHz and the maximum power efficiency is 96.1% at a load current of 1.5 A.

Recently, second generation voltage conveyor (VCII)-based transimpedance amplifiers (TIAs) have begun to find their way in different applications, among which, silicon photomultipliers (SiPMs) interfacing circuitry. There are many advantages which make VCII-based TIAs attractive over conventional circuits: the intrinsic low impedance at VCII current input Y port is very helpful to mitigate the effect of high value sensor capacitance and provides fast response time; the achieved bandwidth is high and due to current mode operation; the circuits enjoy the low-voltage low-power features. As signal-to-noise ratio is a crucial parameter in SiPMs interface circuit applications, here we consider the noise specifications and optimization of VCII-based SiPM interface circuits. The noise model of VCII is introduced and equivalent noise of a VCII-based interface circuit is derived. Methods to optimize trade-offs existing between key parameters including power consumption, gain and noise performance are discussed. Simulation results are also provided showing a considerable reduction of two orders of magnitude in most of the noise performances when compared to the previous work while preserving other performance parameters. [ABSTRACT FROM AUTHOR]

In this research, voltage differencing buffered amplifier (VDBA) is utilized in designing three novel multi-input single output (MISO) topologies of universal filters. The designed filters employ minimum number of passive components and did not require any passive component matching condition. Two of the designed filters can work in dual mode of operation simultaneously. The designed filters have inbuilt tunability property. The nonideal gain analysis and sensitivity analysis of the filters are also carried out to study the effect of process variations and process spread on the filter responses. The complete layout of the VDBA is designed using 0.18μm Silterra Malaysia process design kit (PDK) in Cadence design software. The parasitic extraction is done using Mentor graphics Calibre tool. The postlayout simulations bear close resemblance with the theoretical predictions. [ABSTRACT FROM AUTHOR]

In this paper, a new low-voltage low-power circuit is introduced for implementing CMOS-based basic logic functions using the analog current-mode techniques. The logic functions have been realized by using their expansion in Power Series representation, a Squaring circuit and a Geometric Mean circuit. To illustrate the proposed method, simultaneous realization of the basic logic functions NOT, OR, AND, XOR, NOR, NAND and XNOR in a single circuit is considered. Furthermore, these functions have been used to realize various combinational circuits including full-adder, full-subtractor, etc. SPICE simulation results, obtained with 1.5-V supply, are included. [ABSTRACT FROM AUTHOR]

In this paper, a new current-mode instrumentation amplifier is presented using a single current differencing current controlled current conveyor building block and one grounded resistor. The proposed instrumentation amplifier (IA) can easily be cascaded due to the possession of low impedance current input, and high impedance current output. It offers a high differential gain (73.35 dB) and high bandwidth (BW), 44.8 MHz. Moreover, the common-mode rejection ratio (CMRR) is also very high (93.58 dB), and CMRR BW 5.5 kHz. Power dissipation is found to be low at 132 µW. Furthermore, the electronic tuning of gain is the added feature of the circuit. The non-ideality performance of IA is investigated. The proposed IA functionality is verified through the Cadence ORCAD PSPICE simulator using 0.18 µm TSMC (Level 7) technology parameters. The circuit's workability has also been presented experimentally using commercially available current feedback operational amplifier ICs AD844. Comparison of the performances such as differential gain, BW, CMRR, power consumption, and ease of cascading is reported. [ABSTRACT FROM AUTHOR]

This brief presents an adjustable third-order filter without employing passive elements. The proposed filter combines two low-pass and band-pass MOSFET-only topologies to configure a dual-output structure, while the transconductances and parasitic gate-source capacitances of the transistors act as the required passive elements. The main core of the proposed filter contains just 3 transistors that with the elimination of passive elements results in a small silicon area and low power consumption. The proposed filter benefits from low-input and high-output impedances that is an advantage for cascading in current-mode systems. Moreover, a kind of self-biasing topology is used to configure the proposed filter in which a control voltage is provided to move the center frequency of both outputs in a wide frequency range. The proposed circuit was fabricated using TSMC 0.18 μm CMOS process. Experimental and simulation results at a supply voltage of 1.8 V show a bandwidth range from 38.1 MHz to 99.5 MHz for a capacitive load bigger than 15 pF, while the average power consumption is 435 μW. It occupies a silicon area of just 43 μm × 86 μm. [ABSTRACT FROM AUTHOR]

This paper proposes a multi-attractor period multi-scroll chaotic system and a second-generation current-controlled current conveyor (CCCII) with a wide tunable range of intrinsic resistance. The newly proposed multi-attractor period multi-scroll chaotic system is constructed by this CCCII. The proposed chaotic system can generate single-attractor period, double-attractor period, three-attractor period, and even more attractor period multi-scroll. The four-dimensional state equation of the chaotic system contains four nonlinear functions for generating multi-attractor period multi-scroll chaos. Since the intrinsic resistance of the CCCII can be adjusted by external voltages or currents, the multi-attractor period multi-scroll chaotic integrated circuit based on the proposed CCCII have a tunable characteristic. It is worth noting that a chaotic integrated circuit has been implemented completely using current signals instead of voltage signals, and more interestingly, it does not contain any passive resistor. The dynamic characteristics of the multi-attractor period multi-scroll chaotic system are given. The circuit designs of the CMOS CCCII and the corresponding chaotic circuit are made in detail. We conduct the numerical and circuit simulations of the proposed chaotic system and the integrated circuit implementation of the chaotic circuit based on the CMOS CCCII. The correctness of the CCCII circuit and the chaotic system are proved through hardware experiments. The comparison between the implementation scheme of the chaotic circuit in this paper and several reported chaotic circuits is conducted.

This paper proposes a new current-mode digital modulation circuit. The proposed circuit is MOS only hence, easily integrable. It employs an Extra X Current Conveyor (EX-CCII), two MOS transistors as switches, and a two MOS transistor-based active resistor. The amplitude shift keying/phase shift keying/frequency shift keying (ASK/PSK/FSK) modulator is obtained by proper selection of carriers (I C1 , I C2). This circuit provides the current output signal at high output impedance, which is favorable for cascading. Also, the circuit is employing only MOS transistors, so it can be monolithically IC implementable. The effects of non-idealities and parasitics of the active element on the circuit performance are also investigated in detail. The functionality of the proposed digital modulator is verified through the Cadence Virtuoso tool using 0.18 μm Generic Process Design Kits parameters with the ±0.9 V supply voltage. The total area of the layout is 968.75 μm2. Also, the experimental results are verified by using the IC AD-844 and IC CD4007. • A novel current-mode digital modulation circuit with no-passive component has been presented. • The ASK/PSK/FSK current modulated signals are available at high impedances. • The circuit uses MOS only. • The circuit is easily integrable. • The circuit can be operable at a high frequency of carrier signal. [ABSTRACT FROM AUTHOR]

An accuracy-improved and internal regulator-free temperature on-chip sensor is proposed. The proposed sensor outputs an accuracy-enhanced pulse width modulation (PWM) signal with a nonlinear current mode feedback pseudo-PLL (Phase-Locked Loop). The pseudo-PLL is able to greatly mitigate the nonlinearity caused by process parameters (eg. threshold voltage and mobility of MOS transistor) without careful compensation. Furthermore, to optimize the area and power supply rejection without an internal regulator, a current mode input and feedback approach in the pseudo-PLL is also presented. The proposed sensor is fabricated with 0.18 2μm standard CMOS process. The measurement results show that the power consumption of the sensor is only 2 μW under 1.2V supply voltage. With the supply voltage varying within 1~1.2V, the temperature detection error is maintained within +/−0.2°C in the range of −20°C to 100°C. And the corresponding power supply rejection (PSR) ratio and resolution achieve about 0.15°C/100mV and 0.12°C, respectively. [ABSTRACT FROM AUTHOR]

With the focus of employing single Voltage Differencing Transconductance Amplifier (VDTA) in designing of electronically tunable oscillators, three configurations have been proposed in this manuscript. Each configuration enjoys an efficient integrated circuit implementation due to use of grounded capacitors. Unambiguous and independent control of its condition and frequency of oscillation is an additional feature which is available in all the configurations along with the quadrature outputs in voltage mode. The designed configurations have been tested both through simulation and experimental setup employing a newly proposed hardware arrangement of VDTA designed using off the shelf IC, i.e., OPA860. Moreover, the oscillators have also been experimentally justified with already available hardware realization of VDTA. Experimentation results generated using two different ICs, with two different hardware setups, have been tabulated so as to provide an illustrative study of the performances of oscillators. [ABSTRACT FROM AUTHOR]

In this work, novel first order MOS-C phase shifter structures are proposed in NMOS and PMOS configurations. Core circuits consist of only three transistors and a single capacitor. The pole frequency of the phase shifters can be easily controlled by the bias voltage. The presented circuits in this work bring advantages such as low power consumption and small chip area when compared to other works including large numbers of active and passive elements in the literature. Furthermore, the proposed circuits are designed with a simple design automation flow that is proper for MOS-Only or MOS-C architectures. It is shown by simulations that the simulation results agree with the theoretical results for a wide frequency range. DOI: http://dx.doi.org/10.5755/j01.eie.24.1.20157

In this paper, a novel universal filter using single Four Terminal Floating Nullor Transconductance Amplifier (FTFNTA), two capacitors and one/two resistor has been proposed. Sensitivity of pole frequency (0) and quality factor (Q0) is analysed. Workability of proposed filter has been demonstrated by PSPICE simulations in 0.18µm TSMC CMOS technology. [ABSTRACT FROM AUTHOR]

A novel solution of a reconnection-less reconfigurable filter is being presented. The filter works in the current mode, voltage mode, and mixed mode (voltage tocurrent) offering sixteen transfer functions in total. The structure utilizes a voltage differencing transconductance amplifier, current follower and voltage, and current amplifiers. The designed structure offers the control of the pole frequency and quality factor and the adjustment of the band-stop/bandpass area of available functions. The proposed design is supported by the PSpice simulations using available simulation models. [ABSTRACT FROM AUTHOR]

In this paper, a new active element namely Dual-X current conveyor differential input transconductance amplifier (DXCCDITA) is proposed. The DXCCDITA is utilized in designing four minimum component fully cascadable all pass filter (APF) structures. The designed all pass filters require only single active element and one/two passive elements for realization thus making them a minimum component implementation. Two among the four presented all pass structures require only a single capacitor for implementation. A scheme for realizing nth order all pass filter is also suggested and a fourth order voltage mode (VM) filter is developed from the proposed scheme. The effect of non-idealities on the proposed all pass filters is also studied. A simple oscillator is also developed using one of the all pass filter structure. The oscillator required only one DXCCDITA, two capacitors and one resistor for implementation. The DXCCDITA is implemented in 0.35 μ m TSMC CMOS technology parameters and tested in Tanner EDA. Sufficient numbers of simulations are provided to establish the functionality of all pass structures. The experimental results using commercially available integrated circuits (ICs) are also provided. [ABSTRACT FROM AUTHOR]

The article presents a 65 nm technology implementation of a low-power artificial spiking neuron intellectual property (IP) core. The concept of the circuit is based on modeling the mechanism of a perikaryon membrane and the propagation of the action potential in an axon. Nerve impulses are generated using a current-controlled oscillator. Thanks to this oscillator, the circuit is implemented exclusively using metal-oxide semiconductor transistors, with the omission of capacitors. The main advantage of the presented implementation is the possibility of implementing the IP-core using nanometer digital complementary metal-oxide semiconductor technologies with the possibility of placing it within a common substrate with a digital processor. The circuit operates in weak-inversion mode with a 0.3 V power supply and does not require additional polarization voltages. The maximum frequency of impulse generation equals 2.5 kHz. The paper describes two operating modes of the circuit: a cortical mode with power consumption of 60 pW and a processing mode with power consumption of 52.2 pW. The power reduction was obtained using a circuit structure in which the power supply current consumption is reduced with the moment the circuit starts processing. The article also contains results of a process–voltage–temperature analysis. [ABSTRACT FROM AUTHOR]

In this paper, a novel quasi-resonant flyback converter that mainly comprises two modules of flyback converters is proposed. A relay is connected in series to the input terminals of two transformers, and the transformer input structure is adjusted according to the input voltage to improve the conversion efficiency. In addition, a novel frequency-limiting quasi-resonant control strategy for solving the limitations of the conventional quasi-resonant control strategies is proposed, wherein the switching frequency is increased under light load conditions. Here, the current-mode pulsewidth modulation IC is used as the core controller. The operating principle and design parameters of the converter are analyzed and discussed in detail. The experimental results prove the feasibility of the proposed circuit. [ABSTRACT FROM AUTHOR]

A 13.56 MHz current-mode wireless power receiver with energy-investment capability is presented. An investing voltage controller and a zero-crossing current switching controller are presented to control the switching timing of the power MOSFETs. Both the controllers use the sample-and-hold circuits and the digital controlled delay lines to tolerate the process variations. The highest operation frequency of the controllers is 6.78 MHz. This chip is fabricated in a 0.18- ${\mu}\text{m}$ CMOS process. It achieves a peak power conversion efficiency of 67.1% when the input power is 6 mW. [ABSTRACT FROM AUTHOR]

In this paper a review on design perspective of current-mode current differential trans-conductance amplifier (CDTA) is presented for the state of the art analog signal processing/generating modules design as the main objective. The CDTA circuits are classified according to the active element used for the design with all related parameters taken into consideration. Likelihood implementations of different analog signal processing/generating modules are covered and a comparison of their main parameters trans-conductance, bandwidth, port impedances and power consumption is given. The feasibility of implementing with a lesser area is also considered from the VLSI design viewpoint. The review concludes with CDTA structures with the best possible parameters obtained and future possibilities. [ABSTRACT FROM AUTHOR]

This paper presents an electronically tunable current-mode first-order universal filter. The proposed circuit employs only a single Extra-X Current-Controlled Conveyor (EX-CCCII) and a single grounded capacitor, which is suitable for IC implementation. The circuit can realize three current transfer functions simultaneously, namely low-pass, high-pass and all-pass. The proposed circuit exhibits low-input and high-output impedance, which is suitable for cascading. The pole frequency of the filter can be electronically tuned, by varying the bias current of EX-CCCII. The nonidealities and parasitic effects on the circuit performance are investigated in detail. Also, the Monte Carlo analysis is done to show the effect of active and passive element mismatches on the pole frequency. An eight-phase current-mode sinusoidal oscillator and current-mode second-order filter are further realized using the proposed circuit. The functionality of the proposed circuits is verified through PSPICE simulations, using 0.25- μ m TSMC CMOS technology parameters. [ABSTRACT FROM AUTHOR]

The aim of this paper is to prove that, through a canonic approach, sinusoidal oscillators based on second-generation voltage conveyor (VCII) can be implemented. The investigation demonstrates the feasibility of the design results in a pair of new canonic oscillators based on negative type VCII (VCII−). Interestingly, the same analysis shows that no canonic oscillator configuration can be achieved using positive type VCII (VCII+), since a single VCII+ does not present the correct port conditions to implement such a device. From this analysis, it comes about that, for 5-node networks, the two presented oscillator configurations are the only possible ones and make use of two resistors, two capacitors and a single VCII−. Notably, the produced sinusoidal output signal is easily available through the low output impedance Z port of VCII, removing the need for additional voltage buffer for practical use, which is one of the main limitations of the current mode (CM) approach. The presented theory is substantiated by both LTSpice simulations and measurement results using the commercially available AD844 from Analog Devices, the latter being in a close agreement with the theory. Moreover, low values of THD are given for a wide frequency range.

This brief presents a bipolar junction transistor (BJT)-based CMOS temperature sensor without trimming. A current-mode readout scheme with dynamic current gain compensation is proposed to reduce the error caused by the low current gain $\beta $ of the substrate BJT in nanometer CMOS technologies. Combining this readout scheme with techniques, such as chopping and dynamic element matching (DEM), the sensor achieves a high untrimmed accuracy for auto-calibration in thermal management applications. Fabricated in a standard digital 55-nm CMOS process, the sensor shows a measured inaccuracy within ±1.7 °C ($3\sigma $) from −40 °C to 125 °C without calibration. It occupies a die area of 0.0146 mm2 and has a power consumption of $37~\rm \mu \text{W}$ with an adjustable resolution from 12 to 15 bit and a conversion time of 4.1–32.8 ms. [ABSTRACT FROM AUTHOR]

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Current-mode signaling significantly is known for increasing the bandwidth of on-chip interconnects and reduces the overall propagation delay. In this paper feature of current mode interconnects is exploited for investigating the performance of RLC equivalent ReffCT mathematical delay model of interconnects. This is due to a simple RC interconnects model which results a significant error in delay estimation. Due to this equivalency the non ideal effect of inductive behavior at high frequencies and scaled technologies can be suppressed. The dominance of inductance effect is optimized by Simulative Sweep Analysis Techniques (SSAT). Accuracy is verified by analytical and SPICE simulation results. The performance of delay model is further estimated for voltage and current mode interconnects. When test results are estimated with voltage and current mode systems, it is observed that the equivalent model is superior to the traditional Elmore and Sakurai delay model. [ABSTRACT FROM AUTHOR]

This paper presents the CMOS realization of the first generation orderly current buffer, OCBI. Its design is inspired by BJT version OCB. Employing CMOS technology leads to highly desired features of lower voltage operation, greatly lower power consumption and more economic integration compared to its BJT version. It has modular and fully differential structure in which a core cell is repeated as many times as required to provide the desired parameters. To practically study the performance of the block, it is simulated up to 3rd order. Pre and post-layout plus Monte Carlo simulations are performed under ± 0.75 V by Cadence using TSMC 0.18 µm CMOS technology. Its performance is significantly improved especially in higher orders so that in Post-layout plus Monte Carlo simulations show the differential input impedance of 40.37 Ω and 5.97 Ω, and the CMRR of 82.7 dB and 102.1 dB for the 1st and the 3rd order, respectively. This structure is greatly suitable for wide band applications by providing − 3 dB gain bandwidth in the range of 400 MHz and wider. OCBI dissipates 365 µW in 1st order and because of the added blocks, relatively more in higher orders. Corner cases simulation results are also provided indicating its well PVT insensitivity advantage. [ABSTRACT FROM AUTHOR]