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Several types of low-power passive equalizer are investigated and optimized in this paper. The equalizer topologies include T-junction, parallel R-C, and series R-L structures. These structures can be inserted either at the driver or the receiver side at both the chip and package level to improve the channel bandwidth of central processing unit (CPU)-memory links. Using the eye area as the objective function to be maximized, we optimize these equalizers for the CPU–memory interconnection of an IBM POWER6 system with and without practical constraints on the RLC parameter values. An efficient optimization flow combined with an algorithm predicting the worst case eye diagram is proposed and employed to optimize 42 equalizer schemes. Simulation results show that, without employing any equalizer, the data eye is closed for the bit rate of 6.4 Gb/s, while the equalized schemes can work at the bit rate of 8 Gb/s. Very promising improvements in eye height and jitter are observed with little power overhead. Simulation results also show the sensitivity of the equalization schemes to the RLC values and the effect of coupling noise. [ABSTRACT FROM PUBLISHER]