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Generating dense multilevel voltage space structure using polygons of higher sides is one of the novel and elegant method to suppress low-order harmonics and to obtain refined sinusoidal voltages using voltage source inverters for variable frequency drive application without passive filters. Apart from the advantages of conventional multilevel inverter topologies, schemes generating polygonal voltage space vector structure can equip full dc-bus utilization, low switching frequency strategies to eliminate low-order harmonics, and increased linear modulation range. In this paper, an induction motor drive scheme generating a highly dense multilevel 24-sided polygonal voltage space vector structure using a single dc source, which can eliminate harmonics till 23rd order from phase voltages, is presented. Cascaded power circuit topology with a flying capacitor inverter fed with a dc source and two low voltage floating capacitor fed H-bridge inverters is used. Detailed experimentally validated results, under scalar as well as indirect rotor field oriented control of induction motor are provided. Studies on voltage ripple and reactive energy in various floating capacitors, harmonic performance of output voltage for wide range of speed operation, are also included. [ABSTRACT FROM AUTHOR]

Multilevel inverters with hexagonal and dodecagonal voltage space vector structures have improved harmonic profile compared to two-level inverters. Further improvement in the quality of the waveform is possible using multilevel octadecagonal (18-sided polygon) voltage space vectors. This paper proposes an inverter circuit topology capable of generating multilevel octadecagonal voltage space vectors, by cascading two asymmetric three-level inverters. By the proper selection of dc-link voltages and the resultant switching states for the inverters, voltage space vectors, whose tips lie on three concentric octadecagons, are obtained. The advantages of octadecagonal voltage space vector-based pulsewidth modulation (PWM) techniques are the complete elimination of fifth, seventh, eleventh, and thirteenth harmonics in phase voltages and the extension of linear modulation range. In this paper, a simple PWM timing calculation method is also proposed. Experimental results have been presented in this paper to validate the proposed concept. [ABSTRACT FROM PUBLISHER]

A new hybrid five-level inverter topology with common-mode voltage (CMV) elimination for induction motor drive is proposed in this paper. This topology has only one dc source, and different voltage levels are generated by using this voltage source along with floating capacitors charged to asymmetrical voltage levels. The pulsewidth modulation (PWM) scheme employed in this topology balances the capacitor voltages at the required levels at any power factor and modulation index while eliminating the CMV. This inverter has good fault-tolerant capability as it can be operated in three- or two-level mode with CMV elimination, in case of any failure in the H-bridges. More voltage levels with CMV elimination can be realized from this topology but only in a limited range of modulation index and power factor. Extensive simulation is done to validate the PWM technique for CMV elimination and balancing of the capacitor voltages. The experimental verification of the proposed inverter-fed induction motor is carried out in the linear modulation and overmodulation regions. The steady-state and transient operations of the drive are verified. The dynamics of the capacitor voltage balancing is also tested. The experimental results demonstrate that the proposed topology can be considered for industrial drive applications. [ABSTRACT FROM AUTHOR]

Modulation using a higher sided polygonal space vector structure (SVS) is an elegant method to increase the linear modulation range and to eliminate the undesired lower order harmonics from motor phase voltage. This article presents the generation of a dense 15-concentric 30-sided multilevel SVS using a single dc-link for an open end induction motor (OEIM) drive. The proposed scheme eliminates lower order harmonics till 25th order from motor phase voltage throughout the modulation range. The $dv/dt$ stress in the phase voltage applied to the motor will also be highly reduced owing to the multilevel structure. The pulsewidth modulation scheme employed utilizes the denseness of SVS and avoids iterative searches to find the triangle, which encompasses the tip of reference voltage vector, which are typical in multilevel polygonal SVS. The topology consists of an active dc-link fed three-level primary inverter and a capacitor fed five-level secondary inverter connected to either end of an OEIM. The primary inverter acts as the active power supplier for the drive and the secondary inverter filters out the undesirable lower order harmonics from motor phase voltage. The proposed scheme is experientially validated and the results are included in this article. [ABSTRACT FROM AUTHOR]

This paper presents a nine-level inverter topology for an open-end induction motor drive requiring only eight switches per phase, using two three-level inverters with two isolated dc links in a 3:1 ratio. A space-vector-based formulation is used to determine pole voltages such that both inverters supply power to the load over the full modulation range, eliminating the possibility of dc bus overcharging. Proper selection of switching states ensures that all floating capacitor voltages are kept tightly balanced. A digital state machine is used to select sequences of switching states in order to eliminate deadtime-induced pole voltage transients, further improving the output-voltage quality. A level-shifted carrier-based pulse width modulation scheme is used. The steady-state and transient performance of this topology were verified and the experimental results are included. [ABSTRACT FROM AUTHOR]

For cascaded multilevel inverter topologies with a single dc supply, closed-loop capacitor voltage control is necessary for proper operation. This paper presents zero and reduced common-mode voltage (CMV) operation of a hybrid cascaded multilevel inverter with predictive capacitor voltage control. Each phase of the inverter is realized by cascading two- three-level flying capacitor inverters with a half-bridge module in between. For the presented inverter topology, there are redundant switching states for each inverter voltage levels. By using these switching state redundancies, for every sampling instant, a cost function is evaluated based on the predicted capacitor voltages for each phase. The switching state that minimizes cost function is treated as the best and is switched for that sampling instant. The inverter operates with zero CMV for a modulation index upto 86%. For modulation indices from 86% to 96%, the inverter can operate with reduced CMV magnitude (Vdc/18) and reduced CMV switching frequency using the new space-vector pulsewidth modulation (SVPWM) presented herein. As a result, the linear modulation range is increased to 96% as compared to 86% for zero CMV operation. Simulation and experimental results are presented for the inverter topology for various steady state and transient operating conditions by running an induction motor drive with open loop $V/f$ control scheme. [ABSTRACT FROM PUBLISHER]

A multilevel inverter for generating 17 voltage levels using a three-level flying capacitor inverter and cascaded H-bridge modules with floating capacitors has been proposed. Various aspects of the proposed inverter like capacitor voltage balancing have been presented in the present paper. Experimental results are presented to study the performance of the proposed converter. The stability of the capacitor balancing algorithm has been verified both during transients and steady-state operation. All the capacitors in this circuit can be balanced instantaneously by using one of the pole voltage combinations. Another advantage of this topology is its ability to generate all the voltages from a single dc-link power supply which enables back-to-back operation of converter. Also, the proposed inverter can be operated at all load power factors and modulation indices. Additional advantage is, if one of the H-bridges fail, the inverter can still be operated at full load with reduced number of levels. This configuration has very low dv/dt and common-mode voltage variation. [ABSTRACT FROM AUTHOR]

A voltage source inverter generating a polygonal voltage space vector structure (SVS) having 117- concentric 30-sided polygons of different radii are proposed. Modulation using a 30-sided SVS eliminates lower order harmonics till 25th order from motor phase voltage. The proposed scheme combines the advantages of a 30-sided SVS with that of a multilevel inverter. The topology consists of two cascaded five-level inverters feeding from either end of the open-end induction motor stator windings. One of the cascaded five-level inverter is connected to an active dc source and delivers the required active power for the scheme, while the other is capacitor fed and acts as a switched capacitive filter. In this article, nonaligned 30-sided polygons, i.e., regular 30-sided polygons that are not symmetric with respect to $\alpha$ and $\beta$ axis are also considered for inverter operation. The harmonic analysis of such nonaligned 30-sided polygons is investigated in this article. Nearest level switching is employed throughout the modulation range, enabling further reduction of switching loss in the system. Extensive hardware experimentations are carried out to validate the proposed scheme and the results are included in the article. [ABSTRACT FROM AUTHOR]

The open-loop control scheme presented in part I of this paper for a dual five-level-inverter-fed induction motor (IM) drive with two dc power supplies maintains dc-link capacitor voltage balancing and common-mode voltage (CMV) elimination throughout the operating range of the drive. The operating limitation of the proposed open-loop control scheme to take corrective action toward the existing unbalance in the dc-link-capacitor voltages is also pointed out in part I of this paper. As a solution to this, a simple closed-loop control scheme, which is based only on the switching-state redundancy, is proposed in this part of the paper. The proposed closed-loop control scheme not only prevents further unbalancing of capacitor voltages but also takes corrective actions to bring back the capacitor voltages in the balanced state. The proposed closed-loop scheme achieves dc-link capacitor voltage balancing and elimination of CMV together in the complete modulation range, including overmodulation of up to the 24-step operation. The proposed control scheme does not affect the output fundamental voltage generated by the inverter, as it effectively utilizes only the availability of redundant switching states of the inverter, and does not call for additional power circuit hardware. The scheme is presented with the simulation studies and experimentally verified with a 1.5-kW open-end winding IM drive. [ABSTRACT FROM AUTHOR]

For a dual five-level inverter-fed induction motor (IM) drive, effects of dc-neutral currents on dc-link capacitor voltage fluctuations are analyzed in this paper. Operating limitations in achieving the dual task of common-mode voltage elimination and dc-link capacitor voltage balancing with a single dc power supply are further investigated for the proposed drive. In this paper, an open-loop control scheme, which uses only the availability of redundant switching states for the inverter control, is presented. Limitation of proposed open-loop control to take corrective action for any existing unbalance in capacitor voltages calls for a closed-loop control scheme, which is presented in Part II of this paper. [ABSTRACT FROM AUTHOR]

In this article, a method is proposed for the first time, to increase the linear modulation range till full base speed irrespective of load power factor for a multilevel inverter fed induction motor drive. A five-level inverter with a single dc source is used for the proposed scheme. Using this method, linear pulsewidth modulation (PWM) operation of the inverter can be achieved till peak phase fundamental voltage of 0.637 Vdc without exceeding machine phase voltage rating. This method eliminates all the lower order harmonics from machine phase voltage till the full speed range of operation. The proposed five-level inverter scheme is realized by cascading a two-level inverter with a capacitor fed H-bridge, feeding open-end induction motor drive from one end and a capacitor fed two-level inverter from the other end. The proposed scheme uses space vector redundancy to balance all the capacitors during its operation. Operation of the proposed drive is analyzed extensively for normal five-level operation as well as during the extended modulation range. Experimental results for steady state and transient state operation are presented to validate the proposed scheme [ABSTRACT FROM AUTHOR]

In this paper, a new space vector pulse width modulation method to extend the linear modulation range of a cascaded five level inverter topology with a single dc supply is presented. Using this method, the inverter can be controlled linearly and the peak phase fundamental output voltage of the inverter can be increased from 0.577 to 0.637 V\text{dc} without increasing the dc bus voltage and without exceeding the induction motor voltage rating. This new technique makes use of cascaded inverter pole voltage redundancy and property of the space vector structure for its operation. Using this, the induction motor drive can be operated till the full speed range (0–50 Hz) with the elimination of lower order harmonics in the phase voltage and phase current. The five-level topology presented in this paper is realized by cascading a two-level inverter and two full bridge modules with floating capacitors. The inverter topology and its operation for extending the modulation range is analyzed extensively. Simulation and experimental results for both steady-state and dynamic operating conditions are presented in this paper. [ABSTRACT FROM AUTHOR]

Zero-common-mode-voltage (CMV) operation of multilevel inverters results in reduced dc-bus utilization and reduced linear modulation range. In this paper, a method to increase the linear modulation range for zero-CMV operation without increasing the dc-bus voltage using a cascaded multilevel inverter with a single dc supply is presented. Using this method, the peak fundamental output voltage can be increased from 0.499 to 0.637  \textV\text{dc} with zero CMV inside the linear modulation range. Also, various pulse width modulation (PWM) switching sequences are analyzed in this paper, and the PWM sequence that gives minimum current ripple is used for the zero-CMV operation of the inverter. The inverter topology with single dc supply is realized by cascading a two-level inverter with two floating-capacitor-fed full-bridge modules. Simulation and experimental results for steady-state and dynamic operating conditions are presented to validate the proposed method. [ABSTRACT FROM AUTHOR]

In this paper, a current error space vector (CESV)-based hysteresis current controller for a multilevel 12-sided voltage space vector-based inverter-fed induction motor (IM) drive is proposed. The proposed controller gives a nearly constant switching frequency operation throughout different speeds in the linear modulation region. It achieves the elimination of 6n \pm 1, n = odd harmonics from the phase voltages and currents in the entire modulation range, with an increase in the linear modulation range. It also exhibits fast dynamic behavior under different transient conditions and has a simple controller implementation. Nearly constant switching frequency is obtained by matching the steady-state CESV boundaries of the proposed controller with that of a constant switching frequency SVPWM-based drive. In the proposed controller, the CESV reference boundaries are computed online, using the switching dwell time and voltage error vector of each applied vector. These quantities are calculated from estimated sampled reference phase voltages. Vector change is decided by projecting the actual current error along the computed hysteresis space vector boundary of the presently applied vector. The estimated reference phase voltages are found from the stator current error ripple and the parameters of the IM. [ABSTRACT FROM PUBLISHER]

A three-level common-mode voltage eliminated inverter with single dc supply using flying capacitor inverter and cascaded H-bridge has been proposed in this paper. The three phase space vector polygon formed by this configuration and the polygon formed by the common-mode eliminated states have been discussed. The entire system is simulated in Simulink and the results are experimentally verified. This system has an advantage that if one of devices in the H-bridge fails, the system can still be operated as a normal three-level inverter at full power. This inverter has many other advantages like use of single dc supply, making it possible for a back-to-back grid-tied converter application, improved reliability, etc. [ABSTRACT FROM AUTHOR]

A current-error space-vector-based hysteresis current controller for a general n-level voltage-source inverter (VSI)-fed three-phase induction motor (IM) drive is proposed here, with control of the switching frequency variation for the full linear modulation range. The proposed current controller monitors the space-vector-based current error of an n -level VSI-fed IM to keep the current error within a parabolic boundary, using the information of the current triangular sector in which the tip of the reference vector lies. Information of the reference voltage vector is estimated using the measured current-error space vectors, along the \alpha- and \beta-axes. Appropriate dimension and orientation of this parabolic boundary ensure a switching frequency spectrum similar to that of a constant-switching-frequency voltage-controlled space vector pulsewidth modulation (PWM) (SVPWM)-based IM drive. Like SVPWM for multilevel inverters, the proposed controller selects inverter switching vectors, forming a triangular sector in which the tip of the reference vector stays, for the hysteresis PWM control. The sector in the n-level inverter space vector diagram, in which the tip of the fundamental stator voltage stays, is precisely detected, using the sampled reference space vector estimated from the instantaneous current-error space vectors. The proposed controller retains all the advantages of a conventional hysteresis controller such as fast current control, with smooth transition to the overmodulation region. The proposed controller is implemented on a five-level VSI-fed 7.5-kW IM drive. [ABSTRACT FROM PUBLISHER]

In this paper, a new three-phase, five-level inverter topology with a single-dc source is presented. The proposed topology is obtained by cascading a three-level flying capacitor inverter with a flying H-bridge power cell in each phase. This topology has redundant switching states for generating different pole voltages. By selecting appropriate switching states, the capacitor voltages can be balanced instantaneously (as compared to the fundamental) in any direction of the current, irrespective of the load power factor. Another important feature of this topology is that if any H-bridge fails, it can be bypassed and the configuration can still operate as a three-level inverter at its full power rating. This feature improves the reliability of the circuit. A 3-kW induction motor is run with the proposed topology for the full modulation range. The effectiveness of the capacitor balancing algorithm is tested for the full range of speed and during the sudden acceleration of the motor. [ABSTRACT FROM AUTHOR]

In this paper, a new five-level inverter topology for open-end winding induction-motor (IM) drive is proposed. The open-end winding IM is fed from one end with a two-level inverter in series with a capacitor-fed H-bridge cell, while the other end is connected to a conventional two-level inverter. The combined inverter system produces voltage space-vector locations identical to that of a conventional five-level inverter. A total of 2744 space-vector combinations are distributed over 61 space-vector locations in the proposed scheme. With such a high number of switching state redundancies, it is possible to balance the H-bridge capacitor voltages under all operating conditions including overmodulation region. In addition to that, the proposed topology eliminates 18 clamping diodes having different voltage ratings compared with the neutral point clamped inverter. On the other hand, it requires only one capacitor bank per phase, whereas the flying-capacitor scheme for a five-level topology requires more than one capacitor bank per phase. The proposed inverter topology can be operated as a three-level inverter for full modulation range, in case of any switch failure in the capacitor-fed H-bridge cell. This will increase the reliability of the system. The proposed scheme is experimentally verified on a four-pole 5-hp IM drive. [ABSTRACT FROM PUBLISHER]

This paper proposes a multilevel inverter configuration which produces a hexagonal voltage space vector structure in the lower modulation region and a 12-sided polygonal space vector structure in the overmodulation region. A conventional multilevel inverter produces 6n ± 1 (n = odd) harmonics in the phase voltage during overmodulation and in the extreme square-wave mode of operation. However, this inverter produces a 12-sided polygonal space vector location, leading to the elimination of 6n ± 1 (n = odd) harmonics in the overmodulation region extending to a final 12-step mode of operation with a smooth transition. the benefits of this arrangement are lower losses and reduced torque pulsation in an induction motor drive fed from this converter at higher modulation indexes. The inverter is fabricated by using three conventional cascaded two-level inverters with asymmetric dc-bus voltages. A comparative simulation study of the harmonic distortion in the phase voltage and associated losses in conventional multilevel inverters and that of the proposed inverter is presented in this paper. Experimental validation on a prototype shows that the proposed converter is suitable for high-power applications because of low harmonic distortion and low losses. [ABSTRACT FROM AUTHOR]

This paper develops a seven-level inverter structure for open-end winding induction motor drives. The inverter supply is realized by cascading four two-level and two three-level neutral- point-clamped inverters. The inverter control is designed in such a way that the common-mode voltage (CMV) is eliminated. DC-link capacitor voltage balancing is also achieved by using only the switching-state redundancies. The proposed power circuit structure is modular and therefore suitable for fault-tolerant applications. By appropriately isolating some of the inverters, the drive can be operated during fault conditions in a five-level or a three-level inverter mode, with preserved CMV elimination and dc-link capacitor voltage balancing, within a reduced modulation range. [ABSTRACT FROM AUTHOR]

In this paper, a 12-sided polygonal voltage space vector generation with common-mode voltage elimination (CME) is proposed for an induction motor drive. An open-end winding configuration is used for the motor. The proposed multilevel structure is achieved by cascading only the conventional two-level inverters with asymmetrical dc link voltages. By appropriately selecting the voltage vectors with identical common-mode voltage from the opposite ends, a pulsewidth modulation (PWM) strategy with zero common-mode voltage variation can be achieved for the entire modulation range with a common dc link requirement for both the inverter systems. Along with the CME, the proposed 12-sided polygonal space vector based multilevel inverter structure has increased modulation range with the absence of 5th, 7th, 17th, 19th, etc., harmonics up to 12-step operation. The bandwidth problems associated with conventional hexagonal voltage space vector structure current controllers due to the presence of 5th and 7th harmonics in the overmodulation region are absent in the present 12-sided structure. So a simple PWM voltage control with linear voltage control up to 12-step operation is possible from the present 12-sided scheme with less current control complexity. [ABSTRACT FROM AUTHOR]