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Wafer map defect pattern recognition provides useful clues to yield learning. However, most wafer maps have no special spatial patterns and are full of noises, which make pattern recognition difficult. Especially, recognizing scratch and line types of defect patterns is challenging for process and test engineers. It takes a lot of manpower to identify such patterns, as hidden defective dies may exist on the scratch contour and become discontinuity points. Hidden scratch defective dies may suffer from latent and leakage faults, which usually deteriorate quickly and need to be screened by burn-in test to improve quality. A possible solution is to locate the obscure defective dies in scratch patterns and mark them as faulty. As a result, the quality and reliability of products is significantly improved and cost of final test is reduced. In this article, we propose a systematic methodology to search for potential hidden scratch/line defects in wafers. A five-phase method is developed to enhance wafer maps such that automatic hidden scratch defect pattern recognition can be carried out with high accuracy. Experimental results show the proposed method achieves higher than 89% recognition rate for scratch/line patterns, and higher than 94% for all common wafer defect pattern types. [ABSTRACT FROM AUTHOR]

Spatial failure patterns in wafer defect maps are very useful for root cause analysis, which is essential for yield optimization in the manufacturing process. Especially, the scratch defect type is the most challenging pattern to recognize because the position, shape, size and curvature vary widely from one scratch to another. Discontinuity points within scratches also contribute to the low recognition rate, and such points are often hidden defective dies that become reliability threat. Previous studies on defect pattern identification show that the recognition rate for scratches is among the lowest in all patterns even if the overall accuracy is high. In this paper, we propose a novel scratch pattern recognition method. In this paper, image processing techniques are applied to recognize scratch patterns in wafer maps. The Hough transform is first employed to identify line segments, from which scratches can be reconstructed. In contrast to previous machine-learning based methods, there is no need to train a complicated prediction model so that the computation time is small. The method is validated by using wafer maps from six real products and public data. Experimental results show that the proposed method achieves high recall, precision and accuracy in all cases. [ABSTRACT FROM AUTHOR]

Wafer failure pattern recognition can be used for root cause analysis, which is very important for yield learning. Recently, TestDNA was proposed to improve diagnosis resolution with data collected from wafer test. Previous studies on wafer failure pattern recognition using machine learning achieve good classification results. In this letter, we propose to enhance the classification accuracy with the help of spatial information and ensemble learning algorithms. Experimental results indicate that the proposed method can further improve the accuracy by 8.9%. [ABSTRACT FROM AUTHOR]