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Interconnect congestion estimation plays an important role in the physical design of integrated circuits. Fast congestion analysis prior to global routing enhances the placement quality and improves the routability for the subsequent routing phases. This article presents a novel congestion estimation method for a wire layout with bounded detours and bends. Experimental results on benchmarks demonstrate the efficiency and accuracy of our approach. [ABSTRACT FROM AUTHOR]

Three dimensional (3-D) routing is an important step in deep submicrometer very large-scale integrated design. Given a 3-D grid graph and a set of two-terminal nets to be routed, we propose a probabilistic model to calculate the routing density (congestion) on each edge of the grid graph. The routing density provides a direct congestion estimation. Our experimental results demonstrate the effectiveness of the method on routing benchmarks. [ABSTRACT FROM AUTHOR]

Abstract: Congestion estimation plays an important role in the physical layout of VLSI design. This paper presents a new probabilistic estimation model that improves the previous estimators by relaxing the constraint on detours in a route. The model is more general and realistic for it gives the flexibility for the wires to have wider usage area to bypass the congestion regions and blockages. Given a routing grid and a set of nets to be routed, the model predicts the routing density on each edge of the grid. The routing density provides direct congestion estimation. We compare our estimation results to the actual routing results. Experimental results show the effectiveness of our estimator. [Copyright &y& Elsevier]