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In this work, a multilevel 42-sided polygonal space vector structure for suppression of lower order harmonics for open-end induction motor (OEIM) drive applications is proposed. The proposed power circuit topology consists of two inverters feeding an OEIM from either side. The main inverter fed with a single dc-link providing active power for motoring operation is switched at low switching frequency. The secondary inverter fed with a capacitive supply is switched at high frequency to suppress lower order harmonics upto 39th order, up to the base speed of operation allowing maximum utilization of the dc-link. The advantages of lower order harmonic suppression in motor phase voltage, for polygonal space vector structures, are combined with multilevel inverter topology. This offers various advantages like multilevel operation with low inverter switching for the main power delivery inverter and harmonic suppression throughout the modulation range. The low switching frequency primary inverter generates harmonics of the order $6*k \pm 1$ , where $k = 1, 2, 3,{\ldots }$. The harmonics are suppressed by the capacitor-fed secondary inverter, which supplies only reactive power for suppression of lower order harmonics in motor phase voltage. Use of a single dc-link facilitates four-quadrant operation of the inverter. The proposed scheme is validated for steady-state and dynamic performance by experimental results. [ABSTRACT FROM AUTHOR]

This paper proposes a new 7-level inverter topology for induction motor drives. It is a hybrid topology formed by cascading a 5-level active neutral-point-clamped inverter with a 3-level T-type converter. It is obtained using low-voltage semiconductor devices with voltage blocking capability of Vdc/3 and Vdc/6. The topology uses three floating capacitors per phase, which are balanced within a pulsewidth modulation (PWM) switching duration using switching-state redundancies for each pole-voltage level. Topology forms two stacks at the front-end, which requires individual symmetrical dc source. The analysis of switching loss and conduction loss is performed and compared with some of the existing 7-level multi-level inverters reported in various literatures to show the advantages of the proposed topology. Furthermore, the single dc source operation with two stacked capacitors and closed-loop control of neutral-point voltage using symmetrical six-phase induction motor is proposed. The voltage-control algorithms for floating capacitors and dc-link stacked capacitors are proposed, which are independent of load power factor and modulation index. Open-loop V/f and closed-loop rotor field oriented control are performed, and various results at steady and transient states are presented to validate the aforementioned claims. [ABSTRACT FROM AUTHOR]

This paper proposes a novel method for instantaneous balancing of neutral-point (NP) voltages with stacked multilevel inverters (MLIs) for variable-speed drives. The stacked MLI uses series-connected dc sources and NPs (connecting points of dc sources) to obtain the desired levels. The balancing of NP voltages are obtained by using a low-voltage-capacitor-fed cascaded H-bridge (CHB) per phase of a symmetrical six-phase induction machine (IM), which ensures zero current drawn from NPs (at any given instant). Since no current is drawn from NPs, the single dc-link operation with stacked capacitors is also possible. The scheme is suitable for applications, where low-voltage dc sources and batteries are stacked to form a dc link. A variable-speed operation is done using a seven-level inverter scheme for a symmetrical six-phase IM, which is formed by three dc-link stacked capacitors cascaded with two low-voltage-capacitor-fed CHBs per phase. Furthermore, the method is extended for an open-end IM to obtain a seven-level common-mode eliminated space vector structure using a single dc link. The generalization of this method for any stacked $n$ -level inverter without NP voltage deviation is also presented in this paper. The experimental results and analysis are included to validate the proposed method. [ABSTRACT FROM AUTHOR]

Conventional two-level as well as multilevel voltage-source-inverter topologies with a hexagonal voltage-space vector structure generate low-order harmonics in the machine terminal voltages when operated beyond the linear modulation range in variable speed drive application. Progressing from hexagonal to a higher sided polygonal voltage-space-vector structure (VSVS) suppresses significant low-order harmonics throughout the modulation range. In addition, the linear modulation range will also be enhanced very near to the base speed. In this paper, for the first time, the generation of a multilevel 24-sided VSVS using a single dc source for induction-motor drives is proposed. A cascaded topology with a dc-source-fed flying-capacitor inverter and two low-voltage capacitor-fed H-bridge cells forms the power circuit. The features and advantages of the proposed scheme are validated through experimental results and discussions. [ABSTRACT FROM AUTHOR]

This paper proposes a novel 49-level stacked inverter topology for drives. The 49 levels are achieved by stacking three 17-level inverters. Each of the 17-level inverter is developed by cascading a flying capacitor (FC) inverter with three capacitor-fed H-bridges. The device count can be reduced by making the FC and the three cascaded H-bridges common to the dc link in each phase using selector switches in between them. The selector switches need to operate at fundamental frequency only. Also, the devices need to block very low voltages. Hence, MOSFETs can be used. This topology requires three dc sources, each of V\text{dc} /6 only, which can be replaced with stacked batteries for electric vehicle applications. The reduction in the dc voltage requirement is achieved by using a normal symmetric six-phase induction motor with parallel connection of the opposite phase windings. All the floating capacitors in the topology can be balanced irrespective of any modulation index or load power factor. Due to the high number of voltage levels, nearest level control can be used instead of pulse width modulation, which reduces the switching losses. The $dv/dt$ during the inverter operation is also less. Detailed experimental results at different speeds of operation and during transients ensure that the novel topology can be a viable option for high-power adjustable speed drives. [ABSTRACT FROM PUBLISHER]

In this paper, a multilevel dodecagonal voltage space vector structure with nineteen concentric dodecagons is proposed for the first time. This space vector structure is achieved by cascading two sets of asymmetric three-level inverters with isolated H-bridges on either side of an open-end winding induction motor. The dodecagonal structure is made possible by proper selection of dc link voltages and switching states of the inverters. The proposed scheme retains all the advantages of multilevel topologies as well as the advantages of dodecagonal voltage space vector structure. In addition to that, a generic and simple method for calculation of pulsewidth modulation timings using only sampled reference values ( $v_\alpha$ and $v_\beta$) is proposed. This enables the scheme to be used for any closed-loop application such as vector control. In addition, a new method of switching technique is proposed, which ensures minimum switching while eliminating the fifth- and seventh-order harmonics and suppressing the eleventh and thirteenth harmonics, eliminating the need for bulky filters. The motor phase voltage is a 24-stepped waveform for the entire modulation range thereby reducing the number of switchings of the individual inverter modules. Experimental results for steady-state operation, transient operation, including start-up have been presented and the results of fast Fourier transform analysis is also presented for validating the proposed concept. [ABSTRACT FROM PUBLISHER]

Multilevel inverters with dodecagonal (12-sided polygon) voltage space vector structure have advantages, such as complete elimination of fifth and seventh harmonics, reduction in electromagnetic interference, reduction in device voltage ratings, reduction of switching frequency, extension of linear modulation range, etc., making it a viable option for high-power medium-voltage drives. This paper proposes two power circuit topologies capable of generating multilevel dodecagonal voltage space vector structure with symmetric triangles (for the first time) with minimum number of dc-link power supplies and floating capacitor H-bridges. The first power topology is composed of two hybrid cascaded five-level inverters connected to either side of an open-end winding induction machine. Each inverter consists of a three-level neutral-point-clamped inverter, which is cascaded with an isolated H-bridge making it a five-level inverter. The second topology is for a normal induction motor. Both of these circuit topologies have inherent capacitor balancing for floating H-bridges for all modulation indexes, including transient operations. The proposed topologies do not require any precharging circuitry for startup. A simple pulsewidth modulation timing calculation method for space vector modulation is also presented in this paper. Due to the symmetric arrangement of congruent triangles within the voltage space vector structure, the timing computation requires only the sampled reference values and does not require any offline computation, lookup tables, or angle computation. Experimental results for steady-state operation and transient operation are also presented to validate the proposed concept. [ABSTRACT FROM PUBLISHER]

Multilevel inverters with hexagonal and dodecagonal voltage space vector structures have improved harmonic profile compared to two-level inverters. Further improvement in the quality of the waveform is possible using multilevel octadecagonal (18-sided polygon) voltage space vectors. This paper proposes an inverter circuit topology capable of generating multilevel octadecagonal voltage space vectors, by cascading two asymmetric three-level inverters. By the proper selection of dc-link voltages and the resultant switching states for the inverters, voltage space vectors, whose tips lie on three concentric octadecagons, are obtained. The advantages of octadecagonal voltage space vector-based pulsewidth modulation (PWM) techniques are the complete elimination of fifth, seventh, eleventh, and thirteenth harmonics in phase voltages and the extension of linear modulation range. In this paper, a simple PWM timing calculation method is also proposed. Experimental results have been presented in this paper to validate the proposed concept. [ABSTRACT FROM PUBLISHER]

This paper proposes a current-error space-vector-based hysteresis controller with online computation of boundary for two-level inverter-fed induction motor (IM) drives. The proposed hysteresis controller has got all advantages of conventional current-error space-vector-based hysteresis controllers like quick transient response, simplicity, adjacent voltage vector switching, etc. Major advantage of the proposed controller-based voltage-source-inverters-fed drive is that phase voltage frequency spectrum produced is exactly similar to that of a constant switching frequency space-vector pulsewidth modulated (SVPWM) inverter. In this proposed hysteresis controller, stator voltages along α- and β-axes are estimated during zero and active voltage vector periods using current errors along α- and β-axes and steady-state model of IM. Online computation of hysteresis boundary is carried out using estimated stator voltages in the proposed hysteresis controller. The proposed scheme is simple and capable of taking inverter upto six-step-mode operation, if demanded by drive system. The proposed hysteresis-controller-based inverter-fed drive scheme is experimentally verified. The steady state and transient performance of the proposed scheme is extensively tested. The experimental results are giving constant frequency spectrum for phase voltage similar to that of constant frequency SVPWM inverter-fed drive. [ABSTRACT FROM AUTHOR]

Modulation using a higher sided polygonal space vector structure (SVS) is an elegant method to increase the linear modulation range and to eliminate the undesired lower order harmonics from motor phase voltage. This article presents the generation of a dense 15-concentric 30-sided multilevel SVS using a single dc-link for an open end induction motor (OEIM) drive. The proposed scheme eliminates lower order harmonics till 25th order from motor phase voltage throughout the modulation range. The $dv/dt$ stress in the phase voltage applied to the motor will also be highly reduced owing to the multilevel structure. The pulsewidth modulation scheme employed utilizes the denseness of SVS and avoids iterative searches to find the triangle, which encompasses the tip of reference voltage vector, which are typical in multilevel polygonal SVS. The topology consists of an active dc-link fed three-level primary inverter and a capacitor fed five-level secondary inverter connected to either end of an OEIM. The primary inverter acts as the active power supplier for the drive and the secondary inverter filters out the undesirable lower order harmonics from motor phase voltage. The proposed scheme is experientially validated and the results are included in this article. [ABSTRACT FROM AUTHOR]

In this article, a multilevel inverter scheme to generate a 30-sided space vector structure (SVS) with congruent triangles is proposed. The 30-sided SVS eliminates all the lower order harmonics till 25th order from motor phase voltage throughout the modulation range. The proposed scheme is implemented using a single dc-link on an open-end induction motor (OEIM). The OEIM is fed with primary inverter from one end and secondary inverter from the other end. Primary inverter is fed from an active dc-link and supplies all the required active power for the scheme. Secondary inverter is a capacitor fed inverter, which acts as the switched capacitive filter. In this work, a simple algorithm is proposed, which calculates the timings required for a 2-level 30-sided SVS from sampled reference voltages. The algorithm requires only simple operations such as addition, multiplication, and comparisons. From the obtained timing values, the space vector location of three nearest multilevel 30-sided vectors and its time duration can be identified. The feasibility of the proposed scheme is proved by experimental results. [ABSTRACT FROM AUTHOR]

This article proposes an inverter topology for the first time for suppression of all lower order harmonics (5th, 7th, 11th, 13th, etc.) up to 39th harmonic. The lower order harmonic suppression is achieved by switching the 42-sided polygonal vectors, which eliminates harmonics in phase voltage without using a passive LC filtering technique. The power circuit topology uses a single dc-link supply for the primary inverter. The secondary inverter is fed with a capacitive supply. A novel topology is proposed for the dense six-level secondary inverter. The lower order harmonics in phase voltage are suppressed using the secondary inverter, which acts like a switched-capacitive filter. This article also proposes a novel capacitor voltage-balancing scheme for the first time, which achieves voltage balancing for secondary inverter capacitors. The voltages of secondary inverter capacitors are balanced using the power balance relationship between the primary inverter and the motor load. An experimental study of the topology and the capacitor-balancing scheme is presented for the validation of proposed scheme. [ABSTRACT FROM AUTHOR]

This paper presents a 5-level inverter topology for open-end induction motor drives by using a single dc source. The open stator windings of the drive are supplied with a 3-level flying capacitor inverter from one end and capacitor-fed 2-level inverter from another end. The voltage ratio of the dc link to the capacitor in 2-level inverter is maintained at 4:1 ratio to generate five-level voltage output. The capacitor in 2-level inverter is balanced by the switching redundant vector combinations from both the inverters while the floating capacitors in the 3-level inverter are balanced by using redundant switching states. The proposed topology gives 5-level operation with less number of floating capacitors and power semiconductor switches compared to other existing topologies. Also, the balancing of the capacitors is independent of load power factor and modulation index. Further, the generalization of the proposed dual inverter scheme for any n-level inverter is also included in this paper. The experimental results and required analysis are also presented to validate the inverter scheme. [ABSTRACT FROM AUTHOR]

Conventional voltage-source inverters used for induction motor drives generate a hexagonal space vector structure. In the overmodulation range, the hexagonal space vector structure generates low-order harmonics in the phase voltage resulting in low-order torque ripple in the motor. Inverter topologies with an octadecagonal (18 sided) space vector structure eliminate fifth-, seventh-, eleventh-, and thirteenth-order harmonics from the phase voltage, and hence, the dominant sixth- and twelfth-order torque ripple generation is eliminated. Octadecagonal space vector structures proposed in the past require multiple dc sources, which makes four-quadrant operation of the drive system difficult and costly. In this paper, the formation of a multilevel nine-concentric octadecagonal space vector structure using a single dc source is proposed. Detailed experimental results, using open-loop $V/f$ control and rotor field-oriented control, are presented to validate the effectiveness of the proposed drive scheme. [ABSTRACT FROM PUBLISHER]

This paper presents a nine-level inverter topology for an open-end induction motor drive requiring only eight switches per phase, using two three-level inverters with two isolated dc links in a 3:1 ratio. A space-vector-based formulation is used to determine pole voltages such that both inverters supply power to the load over the full modulation range, eliminating the possibility of dc bus overcharging. Proper selection of switching states ensures that all floating capacitor voltages are kept tightly balanced. A digital state machine is used to select sequences of switching states in order to eliminate deadtime-induced pole voltage transients, further improving the output-voltage quality. A level-shifted carrier-based pulse width modulation scheme is used. The steady-state and transient performance of this topology were verified and the experimental results are included. [ABSTRACT FROM AUTHOR]

For cascaded multilevel inverter topologies with a single dc supply, closed-loop capacitor voltage control is necessary for proper operation. This paper presents zero and reduced common-mode voltage (CMV) operation of a hybrid cascaded multilevel inverter with predictive capacitor voltage control. Each phase of the inverter is realized by cascading two- three-level flying capacitor inverters with a half-bridge module in between. For the presented inverter topology, there are redundant switching states for each inverter voltage levels. By using these switching state redundancies, for every sampling instant, a cost function is evaluated based on the predicted capacitor voltages for each phase. The switching state that minimizes cost function is treated as the best and is switched for that sampling instant. The inverter operates with zero CMV for a modulation index upto 86%. For modulation indices from 86% to 96%, the inverter can operate with reduced CMV magnitude (Vdc/18) and reduced CMV switching frequency using the new space-vector pulsewidth modulation (SVPWM) presented herein. As a result, the linear modulation range is increased to 96% as compared to 86% for zero CMV operation. Simulation and experimental results are presented for the inverter topology for various steady state and transient operating conditions by running an induction motor drive with open loop $V/f$ control scheme. [ABSTRACT FROM PUBLISHER]

In this article, a nine-level multilevel topology is proposed by stacking of low voltage basic inverter cells and then cascading with H-bridges. The dc-link is split into four equal halves by series-connected capacitors from a common dc-link. Three common coupling points (CCPs) are formed due to the stacking of four capacitors, which are connected across the dc-link. The CCP voltage balancing is ensured by drawing or injecting zero instantaneous currents from each of these points at any instant. A six-phase symmetrical IM is used to generate equal and opposite instantaneous phase currents by applying exactly equal and opposite phase voltages for two opposite phases from the six-phase inverter. Simultaneously, the capacitor voltage balancing of H-bridge inverter cells is also achieved by proper selection of redundancies from the available pole voltage redundancies. The concept is verified with a nine-level inverter laboratory prototype, which consists of a five-level stacked inverter, and followed by two low voltage cascaded H-bridge inverters in each phase. Detailed experimental results of steady-state and transient conditions are included to validate the proposed scheme. [ABSTRACT FROM AUTHOR]

This article proposes a method of generating 24-sided polygonal voltage space vector structure composed of 24 real active vectors and a zero vector. Each active vector is a real vector in contrast to switched average vectors in literature. Generation of real 24-sided vectors minimizes switching losses and improves quality of phase voltage compared to switched averaged vectors technique. An important feature of the presented scheme is elimination of lower order harmonics up to 19th order from motor phase voltage throughout the modulation range that gives reduction in torque pulsation and near sinusoidal phase current. The proposed scheme extends the linear modulation range till 99.42 $\%$. Open-end winding induction motor is fed with primary and secondary inverters from either ends. Primary and secondary inverters are implemented by cascading two-level inverters. DC sources for both the inverters are realized using a simple star-delta transformer combination. The proposed concepts are verified with laboratory prototype and the respective results during the steady-state, transient, and fault scenario are presented. The supporting loss analysis and harmonic performance of the proposed drive is performed with existing topologies. [ABSTRACT FROM AUTHOR]

This article proposes a novel nine-level multilevel inverter topology with an instantaneous voltage balancing scheme of stacked dc-link capacitors for an induction motor (IM) drive application. Three neutral points (NPs, terminal joints of four series-connected capacitors) across a single dc-link are balanced instantaneously (within a sampling interval) by ensuring zero current at the NPs. The proper selection of pole voltage from the redundancies provides zero current at any NP during the pulsewidth modulation operation under a steady-state and transient operation. A five-level stacked inverter and three cascaded hybrid-bridge (CHB) inverter cells are used in each phase. Along with the balancing of dc-link capacitors, CHB capacitors’ voltage balancing is also achieved using the pole voltage redundancies at all modulation indexes for all power factor and load. It is also possible to increase more number of levels using more low-voltage switches, and a generalized form of the topology is presented. The concept is validated using a laboratory-developed nine-level inverter with a three-phase IM load, operated under “V/f” control. The detailed experimental results for the steady and transient condition, simulation studies for switching loss, and harmonic content in the phase voltage are also presented. [ABSTRACT FROM AUTHOR]

A new scheme for nine-level voltage space-vector generation for medium-voltage induction motor (IM) drives with open-end stator winding is presented in this paper. The proposed nine-level power converter topology consists of two conventional three-phase two-level voltage source inverters powered by isolated dc sources and six floating-capacitor-connected H-bridges. The H-bridge capacitor voltages are effectively maintained at the required asymmetrical levels by employing a space vector modulation (SVPWM) based control strategy. An interesting feature of this topology is its ability to function in five- or three-level mode, in the entire modulation range, at full-power rating, in the event of any failure in the H -bridges. This feature significantly improves the reliability of the proposed drive system. Each leg of the three-phase two-level inverters used in this topology switches only for a half cycle of the reference voltage waveform. Hence, the effective switching frequency is reduced by half, resulting in switching loss reduction in high-voltage devices. The transient as well as the steady-state performance of the proposed nine-level inverter-fed IM drive system is experimentally verified in the entire modulation range including the overmodulation region. [ABSTRACT FROM PUBLISHER]

A voltage source inverter generating a polygonal voltage space vector structure (SVS) having 117- concentric 30-sided polygons of different radii are proposed. Modulation using a 30-sided SVS eliminates lower order harmonics till 25th order from motor phase voltage. The proposed scheme combines the advantages of a 30-sided SVS with that of a multilevel inverter. The topology consists of two cascaded five-level inverters feeding from either end of the open-end induction motor stator windings. One of the cascaded five-level inverter is connected to an active dc source and delivers the required active power for the scheme, while the other is capacitor fed and acts as a switched capacitive filter. In this article, nonaligned 30-sided polygons, i.e., regular 30-sided polygons that are not symmetric with respect to $\alpha$ and $\beta$ axis are also considered for inverter operation. The harmonic analysis of such nonaligned 30-sided polygons is investigated in this article. Nearest level switching is employed throughout the modulation range, enabling further reduction of switching loss in the system. Extensive hardware experimentations are carried out to validate the proposed scheme and the results are included in the article. [ABSTRACT FROM AUTHOR]

This article introduces a hybrid nine-level inverter topology with extended dc-bus utilization for operation at over modulation range without the presence of lower order harmonics (predominantly fifth and seventh) when compared to conventional two-level and multilevel inverter with hexagonal voltage space vector structure. The proposed inverter is a cascade of a five-level T-type unit and an H-bridge (HB) unit. An increase in the dc-bus utilization is possible by increasing the pole voltage levels to ± (Vdc/2 + Vdc/8) using the HB capacitor voltage and also the capacitor voltages are balanced by adding a offset to sine reference. The aforementioned pulsewidth modulation strategy allows us to increase the peak phase fundamental voltage from 0.577Vdc to 0.625Vdc in case of unity power factor (p.f) load and to 0.637Vdc for 0.82 p.f load with the proposed nine-level inverter. The limiting factor on increasing the dc bus utilization such as p.f, HB capacitor balancing are analysed broadly in this article. The proposed inverter scheme and its claim of increasing the peak phase fundamental voltage is experimentally validated in a laboratory prototype. [ABSTRACT FROM AUTHOR]

In this article, a method is proposed for the first time, to increase the linear modulation range till full base speed irrespective of load power factor for a multilevel inverter fed induction motor drive. A five-level inverter with a single dc source is used for the proposed scheme. Using this method, linear pulsewidth modulation (PWM) operation of the inverter can be achieved till peak phase fundamental voltage of 0.637 Vdc without exceeding machine phase voltage rating. This method eliminates all the lower order harmonics from machine phase voltage till the full speed range of operation. The proposed five-level inverter scheme is realized by cascading a two-level inverter with a capacitor fed H-bridge, feeding open-end induction motor drive from one end and a capacitor fed two-level inverter from the other end. The proposed scheme uses space vector redundancy to balance all the capacitors during its operation. Operation of the proposed drive is analyzed extensively for normal five-level operation as well as during the extended modulation range. Experimental results for steady state and transient state operation are presented to validate the proposed scheme [ABSTRACT FROM AUTHOR]

This paper proposes a novel polygonal voltage space vector structure (SVS) having 30 sides, for a star-connected induction motor drive. The SVS eliminates the presence of harmonics up to 25th order from motor phase voltage throughout the entire modulation range, providing a torque profile devoid of lower order pulsations. Linear modulation is extended till 99.63% of base speed without exceeding the motor phase voltage rating. Topology consists of a dc-link fed primary inverter and two equal low voltage modular capacitor fed secondary inverters. Here the harmonics generated by the primary inverter is canceled by the secondary inverter which acts as a switched capacitive filter. Detailed description of the SVS generation and timing calculations are provided in this paper. Effectiveness of the proposed scheme is validated using experimental results, inverter loss calculations, and harmonic analysis. [ABSTRACT FROM AUTHOR]

A multilevel dodecagonal voltage space vector generation scheme for variable-speed drive applications with single-dc-link operation requires a large value of capacitance for cascaded H-bridge (CHB) filters, when operated at lower speeds. In existing schemes, the multilevel dodecagonal structure is obtained by cascading a flying capacitor inverter with a CHB. In this paper, a new scheme has been proposed to minimize the capacitance requirement for full speed operation by creating vector redundancies using modular and equal voltage CHBs. Also, an algorithm has been developed to optimize the selection of vector redundancies among the CHBs in order to minimize the voltage ripple of the floating capacitors. The proposed algorithm considers instantaneous capacitor voltages and phase currents for optimal selection of vector redundancies. A mathematical model for capacitor voltage deviation is presented, and the effectiveness of the proposed algorithm is verified in both the simulation and the experiment. [ABSTRACT FROM AUTHOR]

This paper proposes generation of a 15-level (14 concentric) dodecagonal voltage space vector structure (DVSVS) for a star connected induction motor drive. The proposed multilevel DVSVS is obtained by cascading two inverters, namely a primary and secondary inverter. The primary inverter is a five-level (5L) structure formed by stacking two three-level flying capacitors with individual reduced dc sources and the secondary inverter is also a 5L structure formed by cascading two capacitor-fed cascaded H-bridges (CHB). The active power is supplied by the primary inverter, while the secondary inverter acts as switched capacitor harmonics filter, and capacitors in the secondary inverter are balanced naturally irrespective of load power factor for entire modulation index. The high-voltage dc supply fed primary inverter is operated in quasi-square wave mode, while the high frequency switching is applied to low voltage CHBs, thus, reducing the overall switching loss. The proposed scheme gives the advantages of both DVSVS and multilevel structure, thus, making it one of the solutions for battery or stacked dc-fed applications. The paper also presents the experimental results as well as comparison study with the existing topologies to support the advantages of proposed scheme. [ABSTRACT FROM AUTHOR]

In this paper, a new space vector pulse width modulation method to extend the linear modulation range of a cascaded five level inverter topology with a single dc supply is presented. Using this method, the inverter can be controlled linearly and the peak phase fundamental output voltage of the inverter can be increased from 0.577 to 0.637 V\text{dc} without increasing the dc bus voltage and without exceeding the induction motor voltage rating. This new technique makes use of cascaded inverter pole voltage redundancy and property of the space vector structure for its operation. Using this, the induction motor drive can be operated till the full speed range (0–50 Hz) with the elimination of lower order harmonics in the phase voltage and phase current. The five-level topology presented in this paper is realized by cascading a two-level inverter and two full bridge modules with floating capacitors. The inverter topology and its operation for extending the modulation range is analyzed extensively. Simulation and experimental results for both steady-state and dynamic operating conditions are presented in this paper. [ABSTRACT FROM AUTHOR]

This paper proposes a novel harmonic suppression scheme for two-level inverter fed three-terminal induction motor drives using switched capacitive filter. Capacitor fed H-bridges used as filters are cascaded to conventional two-level inverter to eliminate fifth- and seventh-order harmonics for the full modulation range including a six-step operation. For the first time, two-level dodecagonal voltage space vector is implemented with single dc supply for three-terminal induction motor drive. Enabling the switched capacitive filtering at low-voltage domain and shifting the high frequency switching to the switched capacitive filter is shown. A uniform pulse width modulation technique is shown which charges and maintains the capacitor voltages while eliminating the fifth- and seventh-order harmonics for the full speed range. [ABSTRACT FROM AUTHOR]

This paper presents a method for generating a multilevel dodecagonal voltage space vector structure using a single dc source for induction motor drives. Multilevel dodecagonal structure combines the advantages of both multilevel and dodecagonal structures, and hence, generates low dv/dt phase voltage along with the elimination of fifth- and seventh-order harmonics over the entire modulation range. This eliminates low-order harmonic currents and prevents the generation of sixth-order torque ripple in the motor. The topology used requires only one dc source making four-quadrant operation of the drive system simpler compared to previously proposed multilevel topologies generating dodecagonal space vector structures. The topology used consists of a three-level flying capacitor (FC) inverter cascaded with a capacitor fed H-bridge. The FC inverter operates at a lower switching frequency and the low-order harmonics are eliminated by the switching action of the cascaded H-bridge inverter. The capacitors in the cascaded H-bridge modules are maintained at a substantially smaller voltage compared to the dc-link voltage and are inherently balanced during the pulsewidth modulation operation. This results in low switching loss, in the FC inverter as well as in the cascaded H-bridge inverter. Experimental results are included to validate the operation of the topology and modulation scheme presented in this paper. [ABSTRACT FROM AUTHOR]

This paper proposes a new method of generating higher number of levels in the voltage waveform by stacking multilevel converters with lower voltage space vector structures. An important feature of this stacked structure is the use of low voltage devices while attaining higher number of levels. This will find extensive applications in electric vehicles since direct battery drive is possible. The voltages of all the capacitors in the structure can be controlled within a switching cycle using the switching state redundancies (pole voltage redundancies). This helps in reducing the capacitor size. Also, the capacitor voltages can be balanced irrespective of modulation index and load power factor. To verify the concept experimentally, a nine-level inverter is developed by stacking two five-level inverters and an induction motor is run using V/f control scheme. Both steady state and transient results are presented. [ABSTRACT FROM AUTHOR]

Zero-common-mode-voltage (CMV) operation of multilevel inverters results in reduced dc-bus utilization and reduced linear modulation range. In this paper, a method to increase the linear modulation range for zero-CMV operation without increasing the dc-bus voltage using a cascaded multilevel inverter with a single dc supply is presented. Using this method, the peak fundamental output voltage can be increased from 0.499 to 0.637  \textV\text{dc} with zero CMV inside the linear modulation range. Also, various pulse width modulation (PWM) switching sequences are analyzed in this paper, and the PWM sequence that gives minimum current ripple is used for the zero-CMV operation of the inverter. The inverter topology with single dc supply is realized by cascading a two-level inverter with two floating-capacitor-fed full-bridge modules. Simulation and experimental results for steady-state and dynamic operating conditions are presented to validate the proposed method. [ABSTRACT FROM AUTHOR]

This paper presents a harmonic elimination technique based on a three-level dodecagonal space vector structure for open-end winding induction motor (IM) drives with a single-dc supply. Advantages of dodecagonal space vector switching and multilevel inverters are achieved with a single-dc supply. A dc supply-fed three-level flying capacitor (FC) inverter feeds active power to one end of the IM winding terminals and H-bridge connected capacitors eliminate fifth- and seventh-order harmonics from the other end. A pulsewidth modulation (PWM) technique is developed to switch the three-level dodecagonal space vectors and simultaneously control the H-bridge capacitors at 0.1445V\text{dc}. The fifth- and seventh-order harmonics are eliminated for the full modulation range of the three-level FC inverter, including the extreme 6-step operation. An increase in the linear modulation range has been achieved, resulting in improved dc bus utilization. Harmonic elimination is achieved by increasing switching frequency of the low-voltage capacitor connected H-bridge inverter; thus, switching frequency for the high-voltage dc supply-fed FC inverter is not increased. Using the proposed scheme, the instantaneous phase voltage never exceeds \frac23V\text{dc} (maximum phase voltage applied for hexagonal space vector structure) for which the machine windings are rated. Additionally, the proposed inverter has also been shown to operate for field oriented control of the open-end winding IM drive. [ABSTRACT FROM AUTHOR]

In this paper, a new inverter topology is proposed for generating a multilevel dodecagonal voltage space vector structure for open-end winding induction motor (IM) using a single dc source. Dodecagonal voltage space vector structure eliminates fifth- and seventh-order harmonic voltages from phase voltage output and hence eliminates the fifth- and seventh-order harmonic currents through the motor leading to removal of the dominant sixth-order torque ripple generation in the motor over the entire modulation range. Multilevel space vector structure generates output voltage with better THD and low dv/dt. In the proposed topology, two three-level inverters drive an open-end winding IM, one inverter from each side. DC-link of primary inverter is from a dc source which delivers the entire active power, whereas the secondary inverter dc-link is maintained by a capacitor, which is self balanced during the inverter operation. The PWM scheme implemented ensures low switching frequency for primary inverter. Secondary inverter operates at a small dc-link voltage. Hence, switching losses are small for both primary and secondary inverters. Experimental results show the elimination of fifth- and seventh-order harmonic voltages over the entire modulation range, validating effectiveness of the proposed multilevel inverter scheme. [ABSTRACT FROM PUBLISHER]

This paper proposes a technique to suppress low-order harmonics for an open-end winding induction motor drive for a full modulation range. One side of the machine is connected to a main inverter with a dc power supply, whereas the other inverter is connected to a capacitor from the other side. Harmonic suppression (with complete elimination of fifth- and seventh-order harmonics) is achieved by realizing dodecagonal space vectors using a combined pulsewidth modulation (PWM) control for the two inverters. The floating capacitor voltage is inherently controlled during the PWM operation. The proposed PWM technique is shown to be valid for the entire modulation range, including overmodulation and six-step mode of operation of the main inverter. Experimental results have been presented to validate the proposed technique. [ABSTRACT FROM PUBLISHER]

Dodecagonal (12-sided) space vector pulsewidth modulation (PWM) schemes are characterized by the complete absence of (6n ± 1)th-order harmonics (for odd n) in the phase voltages, within the linear modulation range and beyond, including overmodulation. This paper presents a new topology suitable for the realization of such multilevel inverter schemes for induction motor (IM) drives, by cascading two-level inverters with flying-capacitor-inverter fed floating H-bridge cells. Now, any standard IM may be used to get the dodecagonal operation which hitherto was possible only with open-end winding IM. To minimize the current total harmonic distortion (THD), a strategy for synchronous PWM is also proposed. It is shown that the proposed method is capable of obtaining better THD figures, compared to conventional dodecagonal schemes. The topology and the PWM strategy are validated through analysis and subsequently verified experimentally. [ABSTRACT FROM AUTHOR]

This paper presents a multilevel inverter topology suitable for the generation of dodecagonal space vectors instead of hexagonal space vectors as in the case of conventional schemes. This feature eliminates all the 6n ± 1 (n = odd ) harmonics from the phase voltages and currents in the entire modulation range with an increase in the linear modulation range. The topology is realized by flying capacitor-based three-level inverters feeding from two ends of an open-end winding induction motor with asymmetric dc links. The flying capacitor voltages are tightly controlled throughout the modulation range using redundant switching states for any load power factor. A simple and fast carrier-based space-vector pulsewidth modulation (PWM) scheme is also proposed for the topology which utilizes only the sampled amplitudes of the reference wave for the PWM timing computation. [ABSTRACT FROM AUTHOR]

In this paper, a new three-phase, five-level inverter topology with a single-dc source is presented. The proposed topology is obtained by cascading a three-level flying capacitor inverter with a flying H-bridge power cell in each phase. This topology has redundant switching states for generating different pole voltages. By selecting appropriate switching states, the capacitor voltages can be balanced instantaneously (as compared to the fundamental) in any direction of the current, irrespective of the load power factor. Another important feature of this topology is that if any H-bridge fails, it can be bypassed and the configuration can still operate as a three-level inverter at its full power rating. This feature improves the reliability of the circuit. A 3-kW induction motor is run with the proposed topology for the full modulation range. The effectiveness of the capacitor balancing algorithm is tested for the full range of speed and during the sudden acceleration of the motor. [ABSTRACT FROM AUTHOR]

A torque control scheme, based on a direct torque control (DTC) algorithm using a 12-sided polygonal voltage space vector, is proposed for a variable speed control of an open-end induction motor drive. The conventional DTC scheme uses a stator flux vector for the sector identification and then the switching vector to control stator flux and torque. However, the proposed DTC scheme selects switching vectors based on the sector information of the estimated fundamental stator voltage vector and its relative position with respect to the stator flux vector. The fundamental stator voltage estimation is based on the steady-state model of IM and the synchronous frequency of operation is derived from the computed stator flux using a low-pass filter technique. The proposed DTC scheme utilizes the exact positions of the fundamental stator voltage vector and stator flux vector to select the optimal switching vector for fast control of torque with small variation of stator flux within the hysteresis band. The present DTC scheme allows full load torque control with fast transient response to very low speeds of operation, with reduced switching frequency variation. Extensive experimental results are presented to show the fast torque control for speed of operation from zero to rated. [ABSTRACT FROM AUTHOR]

A multilevel inverter topology for seven-level space vector generation is proposed in this paper. In this topology, the seven-level structure is realized using two conventional two-level inverters and six capacitor-fed H-bridge cells. It needs only two isolated dc-voltage sources of voltage rating Vdc/2 where Vdc is the dc voltage magnitude required by the conventional neutral point clamped (NPC) seven-level topology. The proposed topology is capable of maintaining the H-bridge capacitor voltages at the required level of Vdc/6 under all operating conditions, covering the entire linear modulation and overmodulation regions, by making use of the switching state redundancies. In the event of any switch failure in H-bridges, this inverter can operate in three-level mode, a feature that enhances the reliability of the drive system. The two-level inverters, which operate at a higher voltage level of Vdc /2, switch less compared to the H-bridges, which operate at a lower voltage level of Vdc/6, resulting in switching loss reduction. The experimental verification of the proposed topology is carried out for the entire modulation range, under steady state as well as transient conditions. [ABSTRACT FROM AUTHOR]

In this paper, a new five-level inverter topology for open-end winding induction-motor (IM) drive is proposed. The open-end winding IM is fed from one end with a two-level inverter in series with a capacitor-fed H-bridge cell, while the other end is connected to a conventional two-level inverter. The combined inverter system produces voltage space-vector locations identical to that of a conventional five-level inverter. A total of 2744 space-vector combinations are distributed over 61 space-vector locations in the proposed scheme. With such a high number of switching state redundancies, it is possible to balance the H-bridge capacitor voltages under all operating conditions including overmodulation region. In addition to that, the proposed topology eliminates 18 clamping diodes having different voltage ratings compared with the neutral point clamped inverter. On the other hand, it requires only one capacitor bank per phase, whereas the flying-capacitor scheme for a five-level topology requires more than one capacitor bank per phase. The proposed inverter topology can be operated as a three-level inverter for full modulation range, in case of any switch failure in the capacitor-fed H-bridge cell. This will increase the reliability of the system. The proposed scheme is experimentally verified on a four-pole 5-hp IM drive. [ABSTRACT FROM PUBLISHER]