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© 2015 Springer Science+Business Media New York Many circuit design applications rely on an intermediate sequence to carry a decision to the next circuit stage. The decision may be carried by a weighted pattern of N bits, with the weights being selected in a way that optimizes the circuit implementation or some aspect of performance. For example, when the weights are consecutive powers of 2 beginning with 1 = 20, we have the standard binary representation. As another example, when all the weights are 1, we have the unary representation that encodes a value k by k asserted bits and N–k unasserted bits (a weight-k bit vector of length N). In this paper, we present the design of a circuit that screens a unary representation to verify that the represented value falls between preset lower and upper limits l and u, passing through any string that represents a value in the interval [l, u] and outputting the all-0 s bit pattern otherwise. Our mixed analog–digital circuit implementation, based on switched-capacitor arrays, provides a decision output within a clock cycle of 4 ns for 16-bit unary representation, when realized with 0.15 μm TSMC technology. The latter results were obtained with normal, per-bit capacitance of 200 fF and single-clock-cycle operation. As an added benefit, our filtering circuit can form the basis for designing a cost-effective Hamming decoder circuit.

We present a new comparator design featuring wide-range and high-speed operation using only conventional digital CMOS cells. Our comparator exploits a novel scalable parallel prefix structure that leverages the comparison outcome of the most significant bit, proceeding bitwise toward the least significant bit only when the compared bits are equal. This method reduces dynamic power dissipation by eliminating unnecessary transitions in a parallel prefix structure that generates the N-bit comparison result after [log 4N]+[log16N]4 CMOS gate delays. Our comparator is composed of locally interconnected CMOS gates with a maximum fan-in and fan-out of five and four, respectively, independent of the comparator bitwidth. The main advantages of our design are high speed and power efficiency, maintained over a wide range. Additionally, our design uses a regular reconfigurable VLSI topology, which allows analytical derivation of the input-output delay as a function of bitwidth. HSPICE simulation for a 64-b comparator shows a worst case input-output delay of 0.86 ns and a maximum power dissipation of 7.7 mW using 0.15-μ TSMC technology at 1 GHz. © 2012 IEEE.

A novel high-performance priority encoder design using standard CMOS library cell is proposed. The new encoder design implementation accommodates both high- and low-priority functionalities with scalable design structure through a special prefixing scheme. The prefixing scheme is applied to minimize the entire propagation delay and exploit the shared hardware between the high- and low-priority evaluation logics circuitry. The proposed encoder shows significant improvement in terms of speed, robustness for top-level floor plan routing, and modularity with pattern structure in compared to the existing encoder designs. Simulation results are conducted for different encoder inputs through 0.15-[micro]m TSMC CMOS technology, where 32-bit priority encoder is used as a test vehicle for comparison improvement measurements. The expected results show that the 32-bit encoder is operating at a maximum of 667-MHz operating frequency with total count of 1106 transistors and a maximum power consumption of total 13.8 mW. Index Terms--0.15-[micro]m TSMC CMOS technology, 32-bit encoder, 667 MHz, high- or low-priority encoder, modularity, prefixing scheme.