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1. FPGA-based Implementation of a New Data Frame Correction System for Merging Units

Author

Hashemi, Mohammad and Alizadeh, Bijan

Subjects
Electrical Engineering and Systems Science - Systems and Control
Abstract

With today's increasing demand for digital devices in Substation Automation Systems (SAS) based on the IEC61850 standard, the measured data error due to the synchronization problem should be considered as a significant problem in digitalized SAS. Although time tagging and mathematical methods have been proposed to alleviate this problem, they require a massive amount of calculations and elaborations. To develop a solution for both problems of the data error and the massive computation, in this paper, we propose a data frame correction (DFC) system with a new method of data shift computation as a data correction method implemented as a hardware accelerator on FPGA. Compared to the state-of-the-art DFC systems, the results show that the proposed DFC system can achieve data correction with up to 99.6% fewer hardware resources utilization and fulfills 9x calculation speed while maintaining IEC61850 required accuracy in 2.1ms.

Published
2021

5. Automated Formal Equivalence Verification of Pipelined Nested Loops in Datapath Designs

Author

Behnam, Payman, Alizadeh, Bijan, and Taheri, Sajjad

Subjects
Computer Science - Hardware Architecture
Abstract

In this paper, we present an efficient formal approach to check the equivalence of synthesized RTL against the high-level specification in the presence of pipelining transformations. To increase the scalability of our proposed method, we dynamically divide the designs into several smaller parts called segments by introducing cut-points. Then we employ Modular Horner Expansion Diagram (M-HED) to check whether the specification and implementation are equivalent or not. In an iterative manner, the equivalence checking for each segment is performed. At each step, the equivalent nodes and those nodes which have an impact on them are removed until the whole design is covered. Our proposed method enables us to deal with the equivalence checking problem for behaviorally synthesized designs even in the presence of pipelines for nested loops. The empirical results demonstrate the efficiency and scalability of our proposed method in terms of run-time and memory usage for several large designs synthesized by a commercial behavioral synthesis tool. Average improvements in terms of the memory usage and run time in comparison with SMT- and SAT-based equivalence checking are 16.7x and 111.9x, respectively., Comment: 14 pages, 20 figures

Published
2017

10. Systematic Trojan Detection in Crypto-Systems Using the Model Checker.

Author

Hosseintalaee, Hamed, Jahanian, Ali, and Alizadeh, Bijan

Subjects
SCALABILITY, MEMORY, HARDWARE, CRYPTOSYSTEMS
Abstract

Formal methods have been introduced as the efficient approach for Trojan detection using the model checking approach. However, systematic property generation for detecting a wide range of Trojans is the main challenge in these methods. In other words, the efficient property generation to pinpoint projected Trojan precisely in targeted hardware has been a bottleneck in this approach. This paper evaluated the feasibility of the systematic property generation methodology for Trojan detection in Cryptosystems by analyzing the vulnerable points of an implemented design respecting Trojans' covered class. The vulnerability analysis reduces the search space of formal methods and considerably improves the scalability of these methods. We have shown in this research that these properties can be generated systematically and prove that the generated properties can be used in conventional model-checking tools to find hard-to-detect Trojans efficiently. Experimental results show that the proposed method reduces Trojan detection time considerably. Also, the memory required to evaluate circuits is possible for several hundreds of clock cycles. [ABSTRACT FROM AUTHOR]

Published
2024
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11. Concealing Exposed Circuit Features Through a MaxSAT-Based Logic Locking Method

Author

Shahmiri, Mohammad Moradi and Alizadeh, Bijan

Abstract

Logic locking has emerged as an effective means of hardware intellectual property protection. Nevertheless, the success of machine learning-based attacks has necessitated the development of new countermeasures. In this brief, we propose a novel approach to multiplexer-based locking that conceals structural and functional features common to all learning-based attacks. By employing a constraint programming approach, we formulate those features as weights for Conjunctive Normal Form (CNF) clauses. We then use Maximum Satisfiability (MaxSAT) solvers to choose locked net pairs in a manner that effectively decreases the correlation between the key bits and the features exploited by attackers. The experimental results demonstrate an 44.19% average reduction in the number of correctly predicted key bits by the learning-based MuxLink attack when compared to the DMUX lock. Furthermore, the prediction accuracy for the constant propagation-based SCOPE attack was consistently below 50%, while the number of undecided bits rose by an average 29.04% in comparison with the DMUX lock.

Published
2024
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17. Pipelined Microprocessors Optimization and Debugging

Author

Alizadeh, Bijan, Gharehbaghi, Amir Masoud, Fujita, Masahiro, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Sirisuk, Phaophak, editor, Morgan, Fearghal, editor, El-Ghazawi, Tarek, editor, and Amano, Hideharu, editor

Published
2010
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19. Automatic Merge-Point Detection for Sequential Equivalence Checking of System-Level and RTL Descriptions

Author

Alizadeh, Bijan, Fujita, Masahiro, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Namjoshi, Kedar S., editor, Yoneda, Tomohiro, editor, Higashino, Teruo, editor, and Okamura, Yoshio, editor

Published
2007
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22. Mutual Lightweight PUF-Based Authentication Scheme Using Random Key Management Mechanism for Resource-Constrained IoT Devices.

Author

Ashtari, Amir, Shabani, Ahmad, and Alizadeh, Bijan

Subjects
INTERNET of things, TELECOMMUNICATION systems, PHYSICAL layer security, RADIO frequency identification systems, COMPUTER network security
Abstract

This paper presents a novel RF-PUF-based authentication scheme, called RKM-PUF which takes advantage of a dynamic random key generation that depends upon both communication parties in the network to detect intrusion attacks. Unlike the existing authentication schemes, our proposed approach takes the physical characteristics of both involved parties into account to generate the secret key, resulting in securely mutual authentication of both nodes in a wireless network. The experimental results of the proposed authentication scheme show that the RKM-PUF can reach up to 99% in identification accuracy. [ABSTRACT FROM AUTHOR]

Published
2022

25. A formal approach for debugging arithmetic circuits

Author

Sarbishei, Omid, Tabandeh, Mahmoud, Alizadeh, Bijan, and Fujita, Masahiro

Subjects
Debugging/testing software, Standard IC, Debugging software -- Evaluation, Integrated circuits -- Design and construction, Semiconductor chips -- Design and construction, Very-large-scale integration -- Usage
Published
2009

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