Search

We present an Rapid Single Flux Quantum (RSFQ) based high voltage driver (HVD) developed for the first amplification stage of a hybrid semiconductor-superconductor memory interface for the RSFQ digital signal processor. Implementation of the driver allows to eliminate the impedance mismatch between RSFQ and standard 50 Omega input of semiconductor electronics and increases the signal-to-noise ratio to reach reliable signal transmission with sufficiently low bit error rate. The driver design is based on the serial stack of 8 SQUIDs with specially configured ground-cuts that form a quasi-coplanar line with 50 Omega impedance. The impedance of the driver has been extracted using 3D EM simulators that accurately take into account multilayer structure and capacitance to the ground. The circuit has been designed for the Hypres 4.5 kA/cm2 process. The driver was simulated numerically in PSCAN. The driver can produce output signal at 1 Gbit/s speed and 2.4 mV signal level that is enough to be sensed by low-noise amplifier on the further amplification stage.

This paper describes a cryogenic multi-chip module (MCM) probe for testing of a superconducting hybrid digital signal processor (DSP) capable of 24 giga multiply accumulate operations per second. The probe has 39 data channels with 4 GHz bandwidth, a 30 GHz high speed clock input line, and 48 biasing lines. The MCM interface board features 164 spring finger contacts for a 30 times 30 mm2 MCM. The probe has low heatload (0.23 W) and provides good magnetic shielding with residual field equal to 250Phi0 over a 5 times 5 mm2 area. The measured time skew between 20 of the 1200 mm data coaxial lines is about 70 ps. The probe allows synchronous data word transmission at 2 Gbps.

We report an RSFQ digital signal processor design based on hybrid RSFQ-CMOS memory suitable for a general matrix-on-matrix multiplication algorithm. The DSP consists of an RSFQ multiply-accumulate unit, memory caches and synchronization block, partitioned into multiple chips, and a large CMOS memory. The parameters of the RSFQ DSP are a 10times10 bits multiplication with rounding to 14 bits, an 18-bit accumulator length and a 3.7 Kb memory cache. The maximum simulated clock frequency is equal to 24 GHz for HYPRES 4.5 kA/cm2 process and optimum communication bandwidth with the CMOS memory is 2 Gbps. The simplified version of the RSFQ DSP consisting of a 4times4 MAC with rounding to 5 bits and 17times6 memory caches has been designed for HYPRES 4.5 kA/cm2 process.

The balanced comparator is an essential part of RSFQ-based readout for superconducting qubits. In this paper we report measurements of the sensitivity of the balanced comparator fabricated in a specialized 30 A/cm2 process with 3.6 muA critical currents and measured at 30-500 mK. At sampling frequency of 3.5 GHz the measured gray zone is DeltaI = 104 nA. Due to electron overheating in the shunt resistors the effective noise temperature is 140 mK. The gray zone has a strong dependence on sampling frequency above 5 GHz due to over-clocking. Related measurements have been reported where cooling fins and reduced critical current density of 10 A/cm2 were used, and a quantum limited gray zone of 40 nA was achieved. This makes single shot readout possible for the phase, RF-SQUID and persistent current qubits. The readout speed is 30-50 ps, which is quite favorable for error correction schemes.

In this paper, issues related to the optimization of superconducting passive interconnects are discussed. Results of the microwave optimization of bends, via connections and crossings of superconducting microstrip lines (SMSLs) are reported. The optimum design of the SMSL cross gives more than 95% of transmission and can be well used in a two-bus cross design with up to 14 signal wires. The results have been confirmed by time-domain simulations and measurements.

RSFQ high performance digital signal processor capable to perform up to 13 13-bit fixed-point GMACS has been designed for use in successive interference canceller in W-CDMA wireless systems. The performance of the processor has been verified by numerical simulations and VHDL simulation using accurate modeling of the RSFQ gates. Components of the processor, 4 /spl times/ 4 and 5 /spl times/ 5 parallel multipliers, 4 /spl times/ 5, 20 /spl times/ 5 and 4 /spl times/ 15 parallel shift registers have been designed and experimentally tested.

Two effects of the bias supply line on the performance of RSFQ circuits have been studied: inductive coupling between the bias supply line and circuit inductances; effect of the mirrored current in the ground plane. The following results of the study are presented: 3D calculations and experimental measurements of inductive coupling between parallel and perpendicular microstrips in presence of one and two ground planes; calculated margins dependence on the external magnetic field in RSFQ cell. Bias current density extraction method has been developed and implemented in RSFQ circuit design flow.

This paper presents timing models for RSFQ cells, based on conventional finite-state machines description. Models have been integrated, validated and verified in physical simulations and are suitable for VHDL design. A complete design flow from physical simulation to VHDL simulation, delays optimization, layouting and back-annotation is presented. The correctness of the timing models has been verified in an experiment with 4 /spl times/ 15 shift register.