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This paper presents the industrial experience of applying an approach to Worst-Case Execution Time (WCET) Analysis that combines analysis and measurement to support a newly developed embedded microprocessor. It outlines an effective method that provides robust results to support certification requirements and offers additional business advantages. The approach outlined in this paper is shown to have been made possible through the use of a highly-structured software architecture, reuse of existing test cases, careful hardware design and use of a Commercial-Off-The-Shelf (COTS) toolset: RapiTime provided by Rapita Systems Ltd. [ABSTRACT FROM AUTHOR]

Static timing analysis is the state-of-the-art practice of ascertaining the timing behavior of currentgeneration real-time embedded systems. The adoption of more complex hardware to respond to the increasing demand for computing power in next-generation systems exacerbates some of the limitations of static timing analysis. In particular, the effort of acquiring (1) detailed information on the hardware to develop an accurate model of its execution latency as well as (2) knowledge of the timing behavior of the program in the presence of varying hardware conditions, such as those dependent on the history of previously executed instructions. We call these problems the timing analysis walls. In this vision-statement article, we present probabilistic timing analysis, a novel approach to the analysis of the timing behavior of next-generation real-time embedded systems. We show how probabilistic timing analysis attacks the timing analysis walls; we then illustrate the mathematical foundations on which this method is based and the challenges we face in the effort of efficiently implementing it. We also present experimental evidence that shows how probabilistic timing analysis reduces the extent of knowledge about the execution platform required to produce probabilistically accurate WCET estimations. [ABSTRACT FROM AUTHOR]

The determination of upper bounds on execution times, commonly called worst-case execution times (WCETs), is a necessary step in the development and validation process for hard real-time systems. This problem is hard if the underlying processor architecture has components, such as caches, pipelines, branch prediction, and other speculative components. This article describes different approaches to this problem and surveys several commercially available tools and research prototypes. [ABSTRACT FROM AUTHOR]

Timing analysis and scheduling for complex systems now requires tools to deal with the fact that systems behaviour is stochastic and contains dependencies which are difficult to determine analytically. This paper introduces copulas, a general statistical tool for constructing multivariate distributions and describing dependence structures of random variables. Copulas are used to solve the problem of determining the probability distribution of the worst-case execution time of a real-time program. The common assumption of statistical independence is generally incorrect for real-time systems and results in severe underestimation of the probability of the worst case. Copulas allow the description of the dependence structure between blocks of a program, and whenever that dependence can not be determined it is possible to provide lower bounds for the distribution of the worst case execution time for any possible dependence between them. The method is illustrated through a case study. [ABSTRACT FROM AUTHOR]

The Merasa project aims to achieve a breakthrough in hardware design, hard real-time support in system software, and worst-case execution time analysis tools for embedded multicore processors. The project focuses on developing multicore processor designs for hard real-time embedded systems and techniques to guarantee the analyzability and timing predictability of every feature provided by the processor. [ABSTRACT FROM PUBLISHER]