14 results on '"Chang, Jing-Yao"'
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2. Investigation of pre-bending substrate design in packaging assembly of an IGBT power module
- Author
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Lee, Chang-Chun, Kao, Kuo-Shu, Lin, Leon, Chang, Jing-Yao, Leu, Fang-Jun, Lu, Yu-Lan, and Chang, Tao-Chih
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- 2014
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3. An Investigation into the Package and Printed Circuit Board Assembly Solutions of an Ultrathin Coreless Flip-Chip Substrate
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Chang, Jing-Yao, Chaung, Tung-Han, and Chang, Tao-Chih
- Published
- 2015
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4. Electromigration induced spontaneous Ag whisker growth in fine Ag-alloy bonding interconnects: Novel polarity effect.
- Author
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Hsu, Tzu-Yu, Chang, Jing-Yao, Chang, Hsiao-Min, and Ouyang, Fan-Yi
- Subjects
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ELECTRODIFFUSION , *METALLIC whiskers , *CRYSTAL growth , *WIRE , *SILVER alloys , *METAL bonding , *POLARITY (Chemistry) - Abstract
Ag-alloy wire has been recognized to be a good candidate for interconnect in light-emitting diode (LED) technology. This study employed fine Ag-alloy wires bonded on Al-Si pad to investigate their failure mechanism under current stressing of 8×10 4 A/cm 2 at ambient temperature of 150 °C and 175 °C, respectively. We report a novel polarity effect that the spontaneous whisker growth of Ag near bonded area only happens when electrons flowed from Al to Ag, while surface of bond joints remains intact with electrons flowed from Ag to Al, suggesting that the nucleation and growth of Ag whisker is strongly affected by the direction of electron flow. We proposed that the different behaviors on the whisker growth is because compressive stress caused by current crowding effect only builds up with electrons flowed from Al to Ag. [ABSTRACT FROM AUTHOR]
- Published
- 2016
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5. Utilization of Zn alloy for the manufacture of automotive power device modules.
- Author
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Kao, Kuo-Shu, Chung, Su-Ching, Fan, Chia-Wen, Chang, Jing-Yao, and Chang, Tao-Chih
- Published
- 2015
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6. Characteristics of 600 V / 450 A IGBT module assembled by Ag sintering technology.
- Author
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Chang, Jing-Yao, Su-Yu Fun, Leu, Fang-Jun, Kao, Kuo-Shu, Chih-Ming Tzeng, Wei-Kuo Han, and Chang, Tao-Chih
- Published
- 2014
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7. The first MIT 600 V/450 a IGBT module for EV/HEV applications.
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Kao, Kuo-Shu, Leu, Fang-Jun, Chang, Jing-Yao, Fan, Su-Yu, Lu, Yu-Lan, and Chang, Tao-Chih
- Abstract
Nowadays, more than 180 countries including China, Japan, EU and others have signed the Kyoto Protocol, then “Energy-saving and Carbon reduction” becomes a popular slogan and an important mission to protect the environment and to pursue the national sustainability. Taiwan government is making many environmental policies as well for driving the people to purchase the eco-products like electric car, hybrid car and household appliances to reach the goal of Carbon reduction, and the industries are also actively involved in the mass production of the key components such as high power IGBT modules for EV/HEV, intelligent power module (IPM) for air-conditioner, and MOSFET SiP modules for the power management of consumer electronics and hand-held machine tools. The first 600 V/450 A IGBT module for EV/HEV application developed by ITRI was announced in this work. The module was composed of IGBTs and freewheel diodes (FWD), firstly 2 IGBTs and 2 FWDs were attached on one Al2O3 direct bonded copper (DBC) substrate by a Pb-free solder perform with a thickness of 100 μm in a vacuum reflow oven, and 3 DBCs were then soldered on a Cu baseplate by a solder perform as well. After cleaning, a heavy Al wire was used to connect the devices and DBCs, and subsequently the housing was adhered to the Cu baseplate by an adhesive. Finally, a Si gel with a dielectric strength higher than 10 kV/mm was poured for insulation and then agglutinated by heating. The process conditions were optimized in this study, a die shear strength higher than 20 MPa was acquired after optimizing the reflow profile, and a design of experiments (DoEs) plan was executed to obtain a pull strength higher than 800 g for the heavy Al wire bonding. After temperature cycling for 1000 times, the loss of the strengths was less than 20%, and the long-term reliability of the power module was verified [ABSTRACT FROM PUBLISHER]
- Published
- 2013
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8. Low temperature bonding using non-conductive adhesive for 3D chip stacking with 30μm-pitch micro solder bump interconnections.
- Author
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Lin, Yu-Min, Zhan, Chau-Jie, Kao, Kuo-Shu, Fan, Chia-Wen, Chung, Su-Ching, Huang, Yu-Wei, Huang, Shin-Yi, Chang, Jing-Yao, Yang, Tsung-Fu, Lau, John H., and Chen, Tai-Hung
- Abstract
Due to the raising requirements of functionality and performance in consumer electronics, high density package technology including high I/O interconnections and 3D chip-stacking technology have received a great number of attentions. Solder micro bumps are widely applied in high density interconnections packaging, but its bonding temperature is still high during process. During chip stacking process, high bonding temperature would lead chip damage and chip warpage induced by the mismatch of coefficient of thermal expansion among each structure within the chip. Also, warpage would cause stress concentration happened within the chip and damage the device and micro interconnections. In order to meet the purpose of low temperature bonding, we demonstrated the chip-to-chip stacking module with a bump pitch of 30um by using non-conductive film in this study. The reliability of the chip-stacking module produced by such low temperature bonding approach was also estimated. A chip-on-chip (COC) structure was used as the test vehicles. There were about 3000 bumps totally in this test vehicle. For evaluating the feasibility of adhesive bonding by NCF in fine pitch micro bumps, Cu/Ni/Au micro bumps joined with Cu/Sn solder micro bumps was conducted by using NCF in this study. After assembly process, thermal cycling test, thermal humidity storage test and high current test were carried out to evaluate the reliability performance of the micro interconnections by such low temperature bonding approach. In this investigation, the chip-on-chip stacking module with a bump pitch of 30μm by using non-conductive film was achieved. The bonding results revealed that the contact resistance of micro joints was about 100 ∼ 350 MΩ. The high deviation of contact resistance was due to the non-melting contact between joined micro bump by soft tin solder. The reliability results revealed that the chip-stacking module produced by NCF could pass the reliability test of 1000 cycles of TCT and 1000 hours of THST. The results of high current test also showed that the NCF joint had excellence endurance against high current density of 5×104 A/cm2 for more than 1300 hours with an increase of contact resistance less than 2%. This study displayed that the NCF material had great potential to be applied in fine-pitch 3D chip stacking. The multi-chip stacking module with a TSV pitch of 20μm produced by NCF will also be presented in this investigation. [ABSTRACT FROM PUBLISHER]
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- 2012
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9. Effects of UBM structure/material on the reliability performance of 3D chip stacking with 30μm-pitch solder micro bump interconnections.
- Author
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Huang, Shin-Yi, Zhan, Chau-Jie, Huang, Yu-Wei, Lin, Yu-Min, Fan, Chia-Wen, Chung, Su-Ching, Kao, Kuo-Shu, Chang, Jing-Yao, Wu, Mei-Lun, Yang, Tsung-Fu, Lau, John H., and Chen, Tai-Hung
- Abstract
With the increased demand of functionality in electronic device, three dimensional integration circuits technology together with downscaling of interconnection pitch present an important role for the development of next generation electronics. In the current types of interconnects, solder micro bumps have received much attention due to its low cost in material and process. For fine pitch solder micro bump interconnections, selection of under bump metallurgical material is a crucial issue because the UBM structure/material will show a significant influence on the reliability performances of the solder micro bump joints. However, which UBM structure/material for fine pitch solder micro bump joint presents the better reliability properties is not concluded yet until now. In this study, the effect of UBM structural/material on the reliability properties of lead-free solder micro interconnections with a pitch of 30μm was discussed. The chip-on-chip test vehicle with solder micro bump interconnections having a diameter of 18 μm was adopted to evaluate the effects of UBM structure/material. There were more than 3000 micro bumps with Sn2.5Ag solder material on both the silicon chip and carrier. In this study, three types of UBM were selected on the silicon carrier: they were single copper layer with a thickness of 8μm; the Cu/Ni layer with the thickness of 5μm/3μm and the Cu/Ni/Au layer with the thickness of 5μm/3μm/0.5μm. The UBM was electro-plated on the Al trace and then the Sn2.5Ag solder with a thickness of 5 μm was deposited. For the silicon carrier with the bump structure of Cu/Sn and Cu/Ni/Sn, the silicon test chip with solder micro bump of Cu/Sn was used for chip bonding. The test chip having the solder micro bump of Cu/Sn and Cu//Ni/Sn was used for bonding with the silicon carrier having the Cu/Ni/Au UBM. In chip stacking process, we adopted the fluxless thermocompression process for each type of micro joints. After chip bonding process, the fine gap between bonded chips was filled by capillary type of underfill. The influence of underfill on the reliability of solder micro bump interconnects with various combinations of UBM structures were estimated also. After the assembly process, temperature cycling test (TCT), high temperature storage (HTS) and electromigration test (EM) were performed on the chip-stacking module to assess the effect of UBM structure/material on the reliability of solder micro bump interconnections. The results of reliability test revealed that only Cu/Sn/Au/Ni/Cu micro joint could not pass the TCT and HTS of 1000 cycles. After reliability test, the Cu/Sn/Cu joints showed the evidently microstructural evolution while the Cu/Ni/Sn/Cu joints did not show apparent microstructure change among all the types of micro joints and still revealed the most contents of residual solder within the joint. On the other hand, the existence of Au layer upon the UBM caused the complicated interface reaction between solder and UBM, which presented a negative effect during long-term reliability performance. The reliability results also displayed that the introduction of underfill could apparently enhance the reliability of micro joint under mechanical evaluation. From the results of EM reliability test, all the types of the micro joints showed excellent electromigration resistance under current stress of 0.08A at an ambient temperature of 150°C irrespective of the types of UBM. This superior property was attributed to the microstructure change transformed from the solder joint to the IMC joint within the solder micro bump interconnections during electromigration test. All the results of reliability test illustrated that the selection of UBM structure/material well influenced the reliability performance of fine-pitch solder micro bump interconnections in 3D chip stacking. [ABSTRACT FROM PUBLISHER]
- Published
- 2012
- Full Text
- View/download PDF
10. Assembly process and reliability assessment of TSV/RDL/IPD interposer with multi-chip-stacking for 3D IC integration SiP.
- Author
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Zhan, Chau-Jie, Tzeng, Pei-Jer, Lau, John H., Dai, Ming-Ji, Chien, Heng-Chieh, Lee, Ching-Kuan, Wu, Shang-Tsai, Kao, Kuo-Shu, Huang, Shin-Yi, Fan, Chia-Wen, Chung, Su-Ching, Huang, Yu-Wei, Lin, Yu-Min, Chang, Jing-Yao, Yang, Tsung-Fu, Chen, Tai-Hung, Lo, Robert, and Kao, M. J.
- Abstract
In this study, a 3D IC integration system-in-package (SiP) with TSV/RDL/IPD interposer is designed and developed. Emphasis is placed on the Cu revealing, embedded stress sensors, non-destructive inspection, thermal modeling and measurement, and final assembly and reliability assessments. [ABSTRACT FROM PUBLISHER]
- Published
- 2012
- Full Text
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11. Assembly and reliability assessment of 50µm-thick chip stacking by wafer-level underfill film.
- Author
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Kuo-Shu Kao, Ren-Shin Cheng, Chau-Jie Zhan, Chang, Jing-Yao, Tsung-Fu Yang, Shin-Yi Huang, Chia-Wen Fan, Su-Mei Chen, Su-Ching Chung, Yu-Lan Lu, Mei-Lun Wu, and Tai-Hung Chen
- Abstract
In order to meet the demands of high-performance, high-speed, small form factor and multi-function integration in portable electronic products, the development of packaging technology now trends toward system-in-package (SiP) technology. Three-dimension (3D) integrated circuit technology provides a way to integrate complex micro systems through vertical interconnections among individual devices/chips. For the multi-chip stacking with fine gap and fine pitch solder micro bump interconnection, the dispensing of capillary underfill presents a major limitation in term of process time and process ability during assembly process. In this study, for realizing the multi-chip stacking, we developed a simplified assembly process by wafer-level underfill (WLUF). The WLUF film was laminated on 8” chip wafer with a thickness of 50µm. The chosen solder micro bump structure was Cu/Ni/Sn2.5Ag with a pitch of 30µm. After wafer dicing, the chip with WLUF was assembled on the substrate chip having the same micro bump structure. The optimized bonding parameters in such assembly process were also determined. The experimental results revealed that a robust joining and no voids formed between bonding interface could be achieved by this simplified assembly process. The results of reliability test showed that all samples could pass LV-3 pre-condition test. The failure percentage was about 10% under 1000 cycles of TCT where the failure mode was the cracks of micro joints and Al pad. The failure percentage was about 52% under 1000 hours of THST where the failure mode was crack of micro joints. All samples could pass the Un-biased HAST test. We also evaluated the feasibility of multi-thin-chip stacking by WLUF film. The experimental results showed that the first-layer micro joints raised 2% increase in contact resistance and the thickness of IMC layer increased 1µm thick only after four-layer chip stacking process. These experimental results displayed that the WLUF material exhibited a highly applied potential for multi-chip assembly process. [ABSTRACT FROM PUBLISHER]
- Published
- 2012
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12. Reliable Microjoints Formed by Solid–Liquid Interdiffusion (SLID) Bonding Within a Chip-Stacking Architecture.
- Author
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Chang, Jing-Yao, Cheng, Ren-Shin, Kao, Kuo-Shu, Chang, Tao-Chih, and Chuang, Tung-Han
- Subjects
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INTERMETALLIC compounds , *MATERIALS science , *METAL finishing , *RELIABILITY in engineering , *QUALITY control , *SYSTEMS engineering - Abstract
In this research, thousands of 20-\mum pitch microbumps with a diameter of 10 \mum and a structure of a pure Sn cap on a Cu pillar were electroplated on 8-inch wafers, and those wafers were then respectively singularized as a top chip and bottom Si interposer for stacking. Two methods, namely conventional reflow and solid–liquid interdiffusion (SLID) bonding, were adopted to interconnect the microbumps. In the former case, the as-plated Sn caps were fluxed, and the chip was then placed on the Si interposer. Afterward, the Sn caps on the chip and on the Si interposer were melted and interconnected at a peak temperature of 250^\circC. The flux residues were cleaned after reflow, and the microgap between the chip and the Si interposer was fully sealed by a capillary underfill. In the SLID bonding process, the oxides on the as-plated Sn caps were removed by a plasma etcher first, and then the chip was placed on the interposer with a bonder as well, subsequently, the Sn caps were heated to 260^\circC to react with the Cu pillar to form Cu6Sn5. In the final step, the intermetallic microjoints were protected by the same capillary underfill. After assembly, the Joint Electron Devices Engineering Council preconditioning test was used to screen the test vehicles for reliability assessment, and then a temperature cycling test was performed to predict the lifespan of the microjoints. The test results showed that the microjoints formed by SLID bonding provided a superior reliability performance to those assembled by reflow. The fracture of the microjoints was caused by the volume contraction induced by the growth of Cu6Sn5, but the failure mechanisms of those two microjoints were quite different. [ABSTRACT FROM AUTHOR]
- Published
- 2012
- Full Text
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13. Evaluation of Cu/SnAg microbump bonding processes for 3D integration using wafer-level underfill film.
- Author
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Yang, Tsung-Fu, Kao, Kuo-Shu, Cheng, Ren-Chin, Chang, Jing-Yao, and Zhan, Chau-Jie
- Subjects
THREE-dimensional integrated circuits ,SEMICONDUCTOR wafers ,MICROPROCESSORS ,SOLDER & soldering ,INTEGRATED circuits ,SEMICONDUCTORS - Abstract
Purpose – 3D chip stacking is a key technology for 3D integration in which two or more chips are stacked with vertical interconnections. In the case of multi chip stacking with fine pitch microbump connections, capillary dispensing presents big limitations in terms of cost and processability. The purpose of this paper is to describe the way in which wafer-level underfill (WLUF) process development was carried out with particular emphasis on microbump height coplanarity, bonding pressure distribution and the alignment of the microbumps. A three factorial design of experiment (DOE) was also conducted to enhance the understanding of the factors impacting the WLUF process such as bonding pressure, temperature and time on reliability test. Design/methodology/approach – B-staged WLUF was laminated on an 8' wafer with a 30 μm pitch bump structure of 8 μm Cu/5 μm Sn2.5Ag Pb-free solder. After wafer dicing, the chip with the WLUF was assembled on a substrate chip with the same bump structure using a high accuracy bonder. The substrate chip had metalisation (wiring) to enable evaluation of the electrical characteristics of the bonded daisy chain chips as they varied with material bonding process conditions and reliability testing. Findings – The WLUF bonding process development pertaining to the processability and reliability for the flip chip assembly using Cu/SnAg microbumps was successful in this work. Originality/value – The development of a WLUF bonding process that offers reliability for flip chip assembly using Cu/SnAg microbumps has been presented in this work. The critical steps, such as alignment of the WLUF coated chip with the substrate chip and void elimination, which enable this technology to work were optimised. [ABSTRACT FROM AUTHOR]
- Published
- 2012
- Full Text
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14. Development of Cu-Ag pastes for high temperature sustainable bonding.
- Author
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Hsiao, Ching-Huan, Kung, Wan-Ting, Song, Jenn-Ming, Chang, Jing-Yao, and Chang, Tao-Chih
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SILVER-copper alloys , *EFFECT of temperature on metals , *METAL bonding , *METAL nanoparticles , *OXIDATION , *ELECTRIC conductivity - Abstract
The combination of excellent electrical conductivity and low cost makes copper a good selection for interconnect materials. However, rapid oxidation of Cu nanoparticles especially at high temperatures is a fatal demerit. To improve the oxidation resistance and realized mass production, Cu@Ag core-shell submicron particles were prepared using commercial copper oxide particles through a low temperature reduction method and subsequent electroless-plating to form Ag shells. Thermal analytical results suggest that Ag coated Cu particles show improved anti-oxidation ability. Mixed with Ag submicron particles obtained from thermal spray pyrolysis, the electrical resistivity of the sintered Cu-Ag composite pastes reaches 10.4 μΩ cm under a reductive atmosphere. Under the bonding pressure of 10 MPa at 275 °C for 30 min, robust Cu to Cu bonding can be achieved with the Cu-Ag composite pastes, for which the shear strength of the joints reaches 32.7 MPa, and it remains 28.2 MPa as the bonding pressure is reduced to 5 MPa. It was also demonstrated that the joints thus formed have superior elevated temperature strength, and excellent reliability subjected to high temperature storage at 250 °C as well as thermal cycling ranged from −65 °C to 150 °C. [ABSTRACT FROM AUTHOR]
- Published
- 2017
- Full Text
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