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Currently, data traffic is growing rapidly, and ensuring optimal network performance and effective data flow management have become the most important tasks. In this context, the quality of network service plays a crucial role in achieving these goals. This article suggests an approach to solving the problem of efficient service in ISDN. Namely, optimization of resource distribution between channel switching and packet switching subnets in ISDN to calculate optimal quality of service characteristics. In the process of ISDN design analysis, an optimization problem is compiled, where the evaluation of the packet-switched subnet service is used as an objective function, and the evaluation of the circuit-switched subnet service is used as one of the constraints for this task. To calculate the main characteristics of a packetswitched subnet, the subnet is considered as a service system with a delay. During the study, the methods of optimal movement of the generalized channel boundary between the subnets of channel switching and packet switching were identified, depending on the data parameters and the state of the integrated network, which made it possible to develop an optimal mathematical model of optimal control of the generalized boundary. To calculate the bandwidth for channel switching and packet switching subnets, an algorithm has been compiled to implement the resulting model and a program in C++ has been compiled. The study of the generalized boundary and the dynamic redistribution of bandwidth between subnets represents a new approach to network optimization. The results are based on the use of the classical Erlang formula for systems with service failures and on load distribution plans, which makes it possible to effectively manage the maintenance process in the network. [ABSTRACT FROM AUTHOR]

Communication specialists all around the world are facing the same problem: shifting from circuit switching (CS) to packet switching (PS). Communication service providers are favoring “All-over-IP” technologies hoping to boost their profits by providing multimedia services. The main stakeholder in this field of the paradigm shift is the industry itself: packet switching hardware manufacturers are going to earn billions of dollars and thus pay engineers and journalists many millions for the promotion of the new paradigm. However, this drive for profit is tempered by life itself. This article is devoted to the discussion of the telecommunications development strategy. We will provide examples to illustrate the difficulties that complicate the transition from CS to PS and the move to hybrid CS+PS solutions. We are considering three areas: (1) network-on-a-chip (NoC), (2) the telecom strategy: how to build the core of the network, (3) the transition of the U.S. Defense Information System Network from SS7 signaling to IP protocol.

• Much refrigerant in the F-evaporator causes the starvation of R-evaporator at RC. • Liquefied refrigerant held-up in the bottom of F-evaporator affect FC performance. • The multi-parameters optimization experimental methods are performed. • R-cabinet temperature drop rate decreased with the increase of ambient temperature. • F-cabinet temperature drop rate was almost unaffected by the ambient temperature. This paper presents an experimental research on configuration optimization of a frost-free refrigerator-freezer with the parallel circuit cycle based on the analysis of circuit switching characteristics. Through combination optimization of R-fan voltage, F-fan voltage, R-capillary tube flow capacity, refrigerant charge, structure of suction pipe, F-compressor speed and R-compressor speed, the system could save 9.27% energy consumption compared with the initial condition. The experimental results also showed that the larger the R-capillary tube flow capacity, the larger the flow rate of the RC, resulting in the quickly temperature drop in R-cabinet and slowly temperature drop in R-cabinet based on "R-cabinet temperature priority" control strategy. Additionally, the R-cabinet temperature drop rate decreased with the increase of ambient temperature but the F-cabinet temperature drop rate was almost unaffected by the ambient temperature. [ABSTRACT FROM AUTHOR]

Internet traffic continues to grow relentlessly, driven largely by increasingly high resolution video content. Although studies have shown that the majority of packets processed by Internet routers are pass-through traffic, they nonetheless have to be queued and routed at every hop in current networks, which unnecessarily adds substantial delays and processing costs. Such pass-through traffic can be better circuit-switched through the underlying optical transport network by means of pre-established circuits, which is possible in a unified packet and circuit switched network. In this paper, we propose a novel convex optimization framework based on a new destination-based multicommodity flow formulation for the allocation of circuits in such unified networks. In particular, we consider two deployment settings, one based on real-time traffic monitoring, and the other relying upon history-based traffic predictions. In both cases, we formulate global network optimization objectives as concave functions that capture the fair sharing of network capacity among competing traffic flows. The convexity of our problem formulations ensures globally optimal solutions. [ABSTRACT FROM AUTHOR]

Optical networks are well suited to enable massive data exchanges between datacenters. Elephant data flows can be routed over custom provisioned and dedicated lightpaths (optical flows) while other (mice) flows, which are routed by electronic switches, are unaffected. In some solutions, wavelength-selective switch (WSS) devices are employed in the optical nodes to physically and individually route each lightpath toward its destination. WSS devices take time to be switched and consequently delay the lightpath setup completion time. In this paper, the authors present three approximate Markov chain models to account for three different WSS service policies. These models estimate the expected lightpath setup and teardown time across an optical node that makes use of WSS devices. The first and more conventional policy (model) assumes that each setup and teardown request is handled individually, while the other two policies (models) assume that groups of setup and/or teardown requests are handled together by the WSS. The models' estimates are compared against the results obtained from a computer-based simulator, where both analytical models and simulator account for experimentally measured WSS response times. The simulator is also used to investigate the end-to-end lightpath setup time across an arbitrary mesh network. Results obtained from the models and simulator show that the group-based service policies outperform the conventional policy at high loads. The group-based policies are especially useful in the presence of lightpaths that are frequently set up and have relatively short holding time (i.e., short duration of elephant-optical flows). [ABSTRACT FROM AUTHOR]

Server workloads operate on large volumes of data. As a result, processors executing these workloads encounter frequent L1-D misses. In a many-core processor, an L1-D miss causes a request packet to be sent to an LLC slice and a response packet to be sent back to the L1-D, which results in high overhead. While prior work targeted response packets, this work focuses on accelerating the request packets. Unlike aggressive OoO cores, simpler cores used in many-core processors cannot hide the latency of L1-D request packets. We observe that LLC slices that serve L1-D misses are strongly temporally correlated. Taking advantage of this observation, we design a simple and accurate predictor. Upon the occurrence of an L1-D miss, the predictor identifies the LLC slice that will serve the next L1-D miss and a circuit will be set up for the upcoming miss request to accelerate its transmission. When the upcoming miss occurs, the resulting request can use the already established circuit for transmission to the LLC slice. We show that our proposal outperforms data prefetching mechanisms in a many-core processor due to (1) higher prediction accuracy and (2) not wasting valuable off-chip bandwidth, while requiring significantly less overhead. Using full-system simulation, we show that our proposal accelerates serving data misses by 22 percent and leads to 10 percent performance improvement over the state-of-the-art network-on-chip. [ABSTRACT FROM AUTHOR]

We present a large-scale optical circuit switch architecture using wavelength-tunable and bandwidth-variable silicon photonic filters. The attainable switch port count is quantitatively evaluated through extensive computer simulations. The requirements for constructing a 1, $024\times1$ ,024 optical circuit switch are analyzed on 10-, 28-, and 56-Gb/s signals. The simulation results are verified through transmission experiments. [ABSTRACT FROM AUTHOR]

Continuous development of Network-on-Chip (NoC) enables different types of applications to run efficiently in a Multiprocessor System-on-Chip (MP-SoC). Guaranteed service (GS) can be provided by circuit switching NoC and Best effort service (BES) can be provided by packet switching NoC. A hybrid NoC containing both packet and circuit switching, can provide both types of services to these different applications. But these different applications can be of different security levels and one application can interfere another application’s timing characteristics during network transmission. Using this interference, a malicious application can extract secret information from higher security level flows (timing side channel) or two applications can communicate covertly violating the system’s security policy (covert timing channel). We propose different mechanisms to protect hybrid routers from timing channel attacks. For design space exploration, we propose three timing channel secure hybrid routers viz. Separate Hybrid (SH), Combined with Separate interface Hybrid (CSH), and Combined Hybrid (CH) routers. Simulation results show that all three routers are secure from timing channel when compared to a conventional hybrid router. Synthesis results show that the area increments compared to a conventional hybrid router are only 7.63, 11.8, and 19.69 percent for SH, CSH, and CH routers respectively. Thus simulation and synthesis results prove the effectiveness of our proposed mechanisms with acceptable area overheads. [ABSTRACT FROM AUTHOR]

With the development of technology of integrated circuit (IC), there will be several hundred million or even several billion transistors in one chip. Optical network on chip (ONoC) has been identified as an effective communication architecture to achieve better performance in delay and energy consumption. However, in circuit switched ONoC, the blocking situation degrades the performance severely. In this paper, a method that converge intellectual property (IP) cores with the same destination address or the same source address is proposed to reduce the blocking probability in circuit switched ONoC. We compare the proposed converged circuit switched ONoC with non-converged circuit switched ONoC in terms of end-to-end (ETE) delay and energy dissipation under various applications. The simulation results show that the converged ONoC improves the ETE delay with small change in energy efficiency. [ABSTRACT FROM AUTHOR]

Optički multipleks zasnovan na talasnoj dužini nosioca OWDM1 je tehnologija mreža identifikovana kao odgovarajuća buduća širokopojasna mrežna okruženja sa dokazanim mogućnostima u pogledu odgovora na povećane zahteve navedenih mreža i kratkom vremenu za uspostavljanje komunikacija. Buduće optičke širokopojasne mreže OWAN2 zahtevaju stvaranje odgovarajućih mrežnih protokola i algoritama koji treba da odgovore na promenljive operativne zahteve. / Optical wavelength division multiplexing (WDM3) networking technology has been identified as a suitable candidate for future wide area network (WAN4) environments, due to its potential ability to meet rising demands of high bandwidth and low latency communication. Networking protocols and algorithms are being developed to meet the changing operational requirements in future optical WANs (OWAN).

Chip multiprocessors (CMPs) require a low-latency interconnect fabric network-on-chip (NoC) to minimize processor stall time on instruction and data accesses that are serviced by the last-level cache (LLC). While packet-switched mesh interconnects sacrifice performance of many-core processors due to NoC-induced delays, existing circuit-switched interconnects do not offer lower network delays as they cannot hide the time it takes to set up a circuit. To address this problem, this work introduces CIMA—a hybrid circuit-switched and packet-switched mesh-based interconnection network that affords low LLC access delays at a small area cost. CIMA uses virtual cut-through (VCT) switching for short request packets, and benefits from circuit switching for longer, delay sensitive response packets. While a request is being served by the LLC, CIMA attempts to set up a circuit for the corresponding response packet. By the time the request packet is served and the response gets ready, a circuit has already been prepared, and as a result, the response packet experiences short delay in the network. A detailed evaluation targeting a 64-core CMP running scale-out workloads reveals that CIMA improves system performance by 21 percent over the state-of-the-art hybrid circuit-packet-switched network. [ABSTRACT FROM AUTHOR]

This paper introduces a new approach for the implementation of randomly interconnected neural networks on hardware taking into account the length of the synapses. We divide the synapses into Long and Short according to the distance between the source and target neurons in a 2D mesh, and we demonstrate that it is possible to guarantee the latency of the Long synapses when they are routed through an additional layer which is based on hierarchical structures of Networks on Chip (NoC). The connection scheme consists in grouping neurons into four regions and communicating their sets of synapses between a pair of them, using circuit switching. In order to validate the interconnection scheme, we simulated the operation of this additional layer for two regions in a neuronal network with grid structure arrangement comprising 1.03 × 10 6 neurons, with a firing rate of 100 Hz and an average of 10 4 synapses per neuron. This pair of regions can support an average of 562 Long synapses per neuron, which is equivalent to managing 5% of the traffic generated by the grouped neurons, with the advantage of having the latency of the synapses guaranteed. A node of the one region has 30,528 neurons and operates with a throughput of 2.95 Millions of spikes per second (Mspk/s) approximately. In a complete operation, the additional layer has four regions and it would support 58 Mspk/s and 520,672 neurons of the network. [ABSTRACT FROM AUTHOR]

Contemporary flow control mechanisms, especially virtual channels, are employed by modern on-chip networks to allow better utilization of the link bandwidth through buffering and packet switching. Despite of being the de facto option in designs, they are also the sources of large energy footprint and long per-hop latency. On the other hand, dated and simpler flow controls such as circuit switching can draw far less power while offering an end-to-end latency analogous to wire delay. In this paper, we therefore take a further step from utilizing a single flow control mechanism within the network to allowing circuit-switching to work alongside virtual channels, which provides latency-competitive and energy-efficient on-chip network designs. Furthermore, to enable circuit switching in modern networks-on-chip, we present two independent proposals so that circuits can be formed in a network either temporally or spatially. In our evaluations, we find that both of our proposals can help achieve a very competitive latency per flit, for up to 30% lower with the temporal approach and for up to 10% lower with the spatial approach, while also dramatically suppressing the energy footprint with either approach by up to 27% and 25%, respectively. [ABSTRACT FROM AUTHOR]

A 16 × 16 mesh network-on-chip (NoC) is fabricated in 22 nm tri-gate CMOS for high-throughput, energy-efficient on-chip interconnect in multi-core processors and systems-on-chip. The NoC connects 256 nodes that are each in their own voltage and clock domain using 5-port routers and 112 b, 855 µm data links. Source-synchronous operation eliminates global clock distribution power and adapts to process, voltage, and temperature variations. Hybrid packet/circuit switching improves energy efficiency by removing intra-route data storage and increases throughput with parallel packet-switched channel setup and circuit-switched data transfer. The NoC achieves: i) 20.2 Tb/s total throughput at 0.9 V, 25 °C; ii) source-synchronous operation for a 2.7× increase in bisection bandwidth to 2.8 Tb/s and 93% reduction in circuit-switched latency at 407 ps/hop, compared to synchronous design; iii) hybrid packet/circuit switching for a 62% latency improvement and 55% increase in energy efficiency to 7.0 Tb/s/W, compared to packet switching; iv) a peak energy efficiency of 18.3 Tb/s/W for near-threshold operation at 430 mV, 25 °C; v) ultra-low-voltage operation down to 340 mV, 25 °C, with router power scaling to 363 µW. [ABSTRACT FROM PUBLISHER]

Communication specialists around the world are facing the same problem: shifting from circuit switching (CS) to packet switching (CS). Communication service providers are favoring 'Allover-IP' technologies hoping to boost their profits by providing multimedia services. The main stakeholder in this field of the paradigm shift is the industry itself: packet switching hardware manufacturers are going to earn billions of dollars and thus pay engineers and journalists many millions for the promotion of the new paradigm. However, this drive for profit is tempered by life itself. This article is devoted to the discussion of the telecommunications development strategy. We will provide examples to illustrate the difficulties that complicate the transition from CS to PS and make us question the feasibility of shifting the telecommunications paradigm. We will consider two examples: [ABSTRACT FROM AUTHOR]

An optical packet and circuit integrated network (OPCInet) provides both high-speed, inexpensive services and deterministic-delay, low-data-loss services according to the users' usage scenarios, from the viewpoint of end users. From the viewpoint of network service providers, this network provides large switching capacity with low energy consumption, high flexibility, and efficient resource utilization with a simple control mechanism. This paper presents the recent progress made in the development of OPCInet and its extension to software-defined networking (SDN). We have developed OPCI nodes, which are capable of layer 3 switching from/to an Ethernet frame to/from an optical packet in the optical packet edge part and a burst-tolerant optical amplifier and an optical buffer with optical fiber delays in 100 Gbps optical packet switching part. The OPCI node achieves a packet error rate less than 10-4 and is used as a node in a lab-network that has access to the Internet. A distributed automatic control works in a control plane for the circuit switching part and in a moving boundary control between optical packet resources and circuit resources. Our optical system for packet and circuit switching works with a centralized control mechanism as well as a distributed control mechanism. We have shown a packet-based SDN system that configures mapping between IP addresses and OPCI node identifiers and switching tables according to the requests from multiple service providers via a web interface. [ABSTRACT FROM PUBLISHER]

We consider a circuit-switched multiservice network with non-hierarchical alternative routing and trunk reservation. Based on the fundamental concept of overflow priority classification approximation (OPCA), we develop two approximations for the estimation of the blocking probability: OPCA and service-based OPCA. We also apply the classical Erlang fixed-point approximation (EFPA) for the estimation of the blocking probability in the network and propose the more conservative max (EFPA, service-based OPCA) as a reasonably accurate evaluation. We compare the approximations with simulation results and discuss the accuracy of the blocking probabilities for the various traffic classes under different system parameter values such as service rates, bandwidth requirements, number of channels per trunk, maximum allowable number of alternative paths and trunk reservation. We also discuss the robustness of the approximations to the shape of the holding time distribution and their performances under asymmetrical cases. We illustrate that when the approximations are used for network dimensioning, their error is acceptable. We further demonstrate that the approximations can be applied in large networks such as the CORONET. [ABSTRACT FROM PUBLISHER]

Previous studies of search in channel graphs have assumed global search, for which the status of any link can be probed by the search algorithm at any time. We consider for the first time local search, for which only links to which an idle path from the source has already been established may be probed. We show that some well-known channel graphs may require exponentially more probes, on average, when search must be local than when it may be global. © 2013 Wiley Periodicals, Inc. Numer Methods Partial Differential Eq 2013 [ABSTRACT FROM AUTHOR]

We consider a circuit-switched network with nonhierarchical alternate routing and trunk reservation involving two types of connections that are modeled as long-lived and short-lived calls. The long-lived calls can be reserved well in advance, and the short-lived calls are provided on demand. Therefore, we assume that the long-lived calls have strict priority over the short-lived ones. We develop approximations for the estimation of the blocking probability based on the quasi-stationary approach in two ways. One uses the Erlang fixed-point approximation (EFPA), and the other uses the overflow priority classification approximation (OPCA). We compare the results of the approximations with simulation results and discuss the accuracy of the approximations under different system parameters, such as ratio of offered load, number of links per trunk, maximum allowable number of deflections, and trunk reservation. We also discuss the robustness of the quasi-stationary approximation to the ratio of the mean holding times of the long-lived and short-lived calls as well as that of EFPA and OPCA to the shape of the holding time distribution. Finally, we demonstrate that OPCA can be applied to a large network such as the Coronet. [ABSTRACT FROM PUBLISHER]

More and more applications are hungry for more and more computation power and performance. This need plus the technology advancements in the field of electronics are resulting in more and more cores and processors being put on the smaller and smaller System-on-Chip (SoC). In spite of such growth in SoC, due to limitations of current On-chip interconnections solution, the power of SoC remains un-utilized. In this column "Pushing Frontiers with the First Lady of Emerging Technologies", Dr. Satwant Kaur explains how her vision of Networks-on-Chip (NoC) also known as On-chip Networks will fulfill the potential and promise of On-chip systems. She discusses some key emerging technologies used for NoC in areas of topologies, switching, congestion, deadlock recovery, 3D SoC, flow control, and interference control to bring about improvements in data quality, communication, performance, connectivity, power consumption, and scalability of today's SoC. [ABSTRACT FROM AUTHOR]

Demands on future data centers and high-performance computing systems will require processor-memory interconnects with greater performance and flexibility than can be provided by existing electronic interconnects. The bandwidth density and bit-rate transparency offered by optical systems are uniquely suited to address these challenges facing memory interconnects. We, thus, investigate a hybrid packet- and circuit-switched optical interconnection network linking microprocessors with their associated main memory, which can simultaneously reduce memory access latency and improve energy efficiency performance. This novel hybrid approach allows low-bandwidth memory control data and small memory transactions to be efficiently transmitted as wavelength-striped optical packets, while long bursts of memory accesses are optically circuit switched. In this study, we experimentally demonstrate an optically connected memory system in which a microprocessor accesses multiple 80-Gb/s memory modules all-optically across a hybrid packet- and circuit- switched optical network. Error-free communication between the microprocessor and main memory is confirmed (bit-error rates less than 10^-12) with the optical network providing low-memory access latencies. The overall memory system reduces energy consumption by 28%. [ABSTRACT FROM PUBLISHER]

In optical burst switching (OBS) networks, bursts may be dumped before they reach their destinations due to contention. Accordingly, we classify trunk utilization into effective and ineffective utilizations used for bursts that reach and do not reach their destinations, respectively. As a benchmark for OBS, we consider an idealized version of optical circuit switching (OCS), designated I-OCS, that does not incur ineffective utilization. In this paper, we study the efficiency of OBS versus I-OCS networks for selected scenarios to facilitate the understanding of performance implications of effective and ineffective utilizations. [ABSTRACT FROM PUBLISHER]

Data access latency, a limiting factor in the performance of chip multiprocessors, grows significantly with the number of cores in nonuniform cache architectures with distributed cache banks. To mitigate this effect, we use a compiler-based approach to leverage data access locality, choose an optimized data placement and efficiently configure the on-chip network. The proposed experimental compiler framework employs novel compilation techniques to discover and represent multithreaded memory access patterns (MMAPs). At runtime, symbolic MMAPs are resolved and used by a partitioning algorithm to choose a partition of allocated memory blocks among the forked threads in the analyzed application. This partition is used to enforce data ownership by associating the data with the core that executes the thread owning the data. Based on the partition, the communication pattern of the application can be extracted. We demonstrate how this information can be used in an experimental architecture to accelerate applications. In particular, our compiler assisted data partitioning approach shows a 20 percent speedup over shared caching and 5 percent speedup over the closest runtime approximation, first touch. By leveraging the communication pattern we can achieve a comparable performance to a system that uses a complex centralized network configuration system at runtime. Thus, our final system saves significant runtime complexity and achieves an 5.1 percent additional speedup through the addition of the reconfigurable network. [ABSTRACT FROM AUTHOR]

In many environments, rather than minimizing message latency or maximizing network performance, the ability to survive beyond the failure of individual network components is the main issue of interests. The nature of Wormhole Switching (WS) leads to high network throughput and low message latencies. However, in the vicinity of faulty regions, these behaviors cause rapid congestion, provoking the network becomes deadlocked. While techniques such as adaptive routing can alleviate the problem, they cannot completely solve the problem. Thus, there have been extreme studies on other types of switching mechanisms in networking and multicomputers communities. In this paper, we present a general mathematical model to assess the relative performance merits of three well-known fault-tolerant switching methods in tori, namely Scouting Switching (SS), Pipelined Circuit Switching (PCS), and Circuit Switching (CS). We have carried out extensive simulation experiments, the results of which are used to validate the proposed analytical models. We have also conducted an extensive comparative performance analysis, by means of analytical modeling, of SS, PCS, and CS under various working conditions. The analytical results reveal that SS shows substantial performance improvements for low to moderate failure rates over PCS and CS, which achieves close to WS performance. PCS can provide superior performance over CS and behaves the same or in some occasions worse than SS, under light and moderate traffic, especially with the same hardware requirements. [ABSTRACT FROM AUTHOR]

In this paper, we propose to apply a novel paradigm called labeled optical burst switching with home circuit (LOBS-HC) for intradatacenter networking to provide a high bisection bandwidth and significantly reduce the cost and energy consumption associated with electronic packet switching. The unique features of LOBS-HC that make it more suitable than either optical circuit switching (OCS) or optical packet/burst switching are exploited to enable all-to-all communications with a guaranteed lossless transmission bandwidth between any given pair of pods, while also supporting bursty transmissions through wavelength-sharing among home circuits (HCs) and statistical multiplexing. As a case study, hypercube-like topologies are considered for the interconnection among the pods within a datacenter. In particular, we first propose a simple but efficient HC assignment scheme called complementary HC for 2-D cube or ring, and then extend our works to n-cube and generalized hypercube by applying the concept of spanning balanced tree (SBT) for their HC assignment. Our analysis results show that with such datacenters, the minimum number of wavelengths needed in each case is significantly reduced from that needed with OCS and also, the network cost in terms of wires and transceivers needed is considerably reduced from that incurs with datacenters using electronic packet switching. We then evaluate the traffic performance of such hypercube-based datacenters using LOBS-HC through simulation experiments via the OPNET simulator. The performance results obtained for a variety of communication patterns and traffic models within a datacenter demonstrate the feasibility of the proposed approach. [ABSTRACT FROM PUBLISHER]

Emerging elastic applications generate voluminous datasets, which are often required to be transferred across the network irrespective of flow level bandwidth guarantees. The primary concern in efficient transfers of such bulk data is to minimize the net transfer time. Variable bandwidth advance reservation (VBAR) can efficiently support such applications by reserving time variant bandwidth over the duration of a connection in advance. In this work, we address the routing and bandwidth scheduling problem in VBAR with the objective of minimizing the data transfer time. We propose three heuristic algorithms, and evaluate their performance for a single request under a given network state. We also evaluate the performance of the heuristics in a network under a dynamic traffic scenario. We demonstrate that VBAR outperforms conventional standard advance reservation and immediate reservation approaches in terms of delay, blocking probability, and network throughput. Furthermore, the performance of the proposed heuristic outperforms existing solutions in the dynamic traffic scenario with significantly lower time and storage complexities. [ABSTRACT FROM PUBLISHER]