Search

New energy concepts such as distributed power generation systems (DPGSs) are changing the face of electric distribution and transmission. Power electronics researchers try to apply new electronic controller solutions with the capacity of implementing new and more complex control algorithms combined with internal high-speed communication interfaces. Thus, it is possible to monitor, store, and transfer a large number of internal variables that can be sent online to local or remote hosts in order to take new set points of different generation units. With this objective, this paper presents the design, implementation, and test of an industrial multiprocessor controller based on a floating-point digital signal processor (DSP) and a field-programmable gate array, which operate cooperatively. The communication architecture, which has been added to the proposed electronic solution, consists of a universal serial bus (USB), implemented with a minimum use of the DSP core, and a controller area network (CAN) bus that permits distributed control. Although the proposed system can be readily applied to any DPGS, in this paper, it is focused on a 150-kVA back-to-back three-level neutral-point-clamped voltage source converter for wind turbine applications. Index Terms--Digital signal processors (DSPs), field-programmable gate arrays (FPGAs), power distribution control, power system communication.

Stator winding vibration is the most common cause of unexpected failure of high-voltage (HV) generators. Stator bars are generally fixed in slots by using slot wedges and a side packing system. Loose slot wedges could result in excessive vibration of the stator bars, which would accelerate the deterioration of the ground wall insulation. Loose slot wedge testing is consequently one of the most important general examination procedures to make sure the condition of HV generators. The common method used for slot wedge testing is manual measurement, whereby the slot wedge is tapped by hand using a small hammer. A judgment on looseness is made based on the sound from it. A digital signal processor (DSP)-based loose slot wedge tester is described in detail in this paper, including both hardware and software design. It was developed in our laboratory based on the study of slot wedge vibration characteristics in its loosening process. Since embedded software system of the DSP is oriented to a specific industrial field while PC system is of a general purpose, the device has many advantages compared to traditional manual measurement or other slot wedge testing equipment, such as portability, high intelligence, low power consumption, etc. The tester was applied for laboratory loose slot wedge testing of a slot model. The test results soundly verified the good performance of the device. Index Terms--Digital signal processor (DSP), ground wall insulation, high-voltage (HV) generators, slot wedge, stator bar, tightness testing, winding vibration.

This paper considers trellis coded quantization (TCQ) and low-density parity-check (LDPC) codes for the quadratic Gaussian Wyner-Ziv coding problem. After TCQ of the source X, LDPC codes are used to implement Slepian-Wolf coding of the quantized source Q(X) with side information Y at the decoder. Assuming 256-state TCQ and ideal Slepian-Wolf coding in the sense of achieving the theoretical limit H(Q(X)|Y), we experimentally show that Slepian-Wolf coded TCQ performs 0.2 dB away from the Wyner-Ziv distortionrate function [D.sub.wz] (R) at high rate. This result mirrors that of entropy-constrained TCQ in classic source coding of Gaussian sources. Furthermore, using 8,192-state TCQ and assuming ideal Slepian-Wolf coding, our simulations show that Slepian-Wolf coded TCQ performs only 0.1 dB away from [D.sub.wz](R) at high rate. These results establish the practical performance limit of Slepian-Wolf coded TCQ for quadratic Gaussian Wyner-Ziv coding. Practical designs give performance very close to the theoretical limit. For example, with 8,192-state TCQ, irregular LDPC codes for Slepian-Wolf coding and optimal non-linear estimation at the decoder, our performance gap to [D.sub.wz](R) is 0.20 dB, 0.22 dB, 0.30 dB, and 0.93 dB at 3.83 bit per sample (b/s), 1.83 b/s, 1.53 b/s, and 1.05 b/s, respectively. When 256-state 4-D trellis-coded vector quantization instead of TCQ is employed, the performance gap to [D.sub.wz](R) is 0.51 dB, 0.51 dB, 0.54 dB, and 0.80 dB at 2.04 b/s, 1.38 b/s, 1.0 b/s, and 0.5 b/s, respectively. Index Terms--Wyner-Ziv coding, Slepian-Wolf coding, nested lattices, TCQ, syndrome-based compression, and LDPC codes.

Cyclostationarity is an inherent characteristic of many communication signals, which can be exploited for performing various signal processing tasks. Imperfections in the signal generation that affect the cyclic statistics of a signal may lead to a degradation in the performance of signal processing algorithms which make use of this cyclostationary behaviour. One typical source of imperfection encountered in digital signalling techniques is random jitter in the pulse timing. In this work, we systematically derive analytical expressions for the cyclic statistics of digital baseband signalling schemes in the presence of timing jitter, under the assumption that the generating wide sense cyclostationary data sequence and the stationary jitter process are statistically independent. Index Terms--Timing jitter, digital signalling, cyclostationarity, spectral correlation.

This paper presents the practical implementation of a novel fault diagnostic and protection scheme for the interior permanent-magnet (IPM) synchronous motors using wavelet packet transform (WPT) and artificial neural network. In the proposed technique, the line currents of different faulted and normal conditions of the IPM motor are preprocessed by the WPT. The second level WPT coefficients of line currents are used as inputs of a three-layer feedforward neural network. The proposed protection technique is successfully simulated and experimentally tested on the line-fed and inverter-fed IPM motors. The Texas Instrument 32-bit floating-point digital signal processor TMS320C31 is used for the real-time implementation of the proposed protection algorithm. The offline and online test results of both line-fed and inverter-fed IPM motors are given. These test results showed satisfactory performances of the proposed diagnostic and protection technique in terms of speed, accuracy, and reliability. Index Terms--Digital signal processors, fault diagnosis, interior permanent-magnet (IPM) motor, neural networks, wavelet packet transform (WPT).

A comparison between an algebraic parameter identification algorithm for the load of a boost converter and classical asymptotic observers for the same purpose is provided. Two asymptotic observers are presented, and an algebraic identification algorithm is derived. For the latter, two implementations in the software for a digital signal processor are discussed, and experimental results are given which highlight the properties of both approaches. Index Terms--Algebraic identification, boost converter, nonlinear observers.

In this paper, a general definition of circulating currents for each phase of each paralleled converter with different load sharing is first proposed. Then, based on this definition, the corresponding circulating current index [[gamma].sub.kj] and unbalance rate [[beta].sub.j] for paralleled converter j are proposed to provide one with a quantitative measure about the serious status of power quality. Third, the corresponding general model of circulating currents is also derived for understanding the governing dynamic behavior of circulating currents. Fourth, based on the derived model, the proposed coordinate control strategy is then proposed for different load sharing controls, as well as elimination of circulating currents. Furthermore, a prototype system is also constructed, and the proposed coordinate control is implemented using TMS320F2812 digital signal processor. Both simulation and experimental results indeed show the effectiveness of the proposed coordinate control. Index Terms--Circulating currents, parallel system, three-phase boost rectifiers.

This article presents an event and pulse node hardware module (EPN) developed for use in control and data acquisition (CODAC) in current and upcoming long discharges nuclear fusion experiments. Its purpose is to allow real time event management and trigger distribution. The use of a mixture of digital signal processing and field programmable gate arrays, with fiber optic channels for event broadcast between CODAC nodes, and short length paths between the EPN and CODAC hardware, allows an effective and low latency communication path. This hardware will be integrated in the ISTTOK CODAC to allow long AC plasma discharges. Index Terms--Event distribution, real-time, synchronism, trigger distribution.

TileCal is the hadronic tile calorimeter of the ATLAS experiment at LHC/CERN. The central element of the back-end system of the TileCal detector is the Read-Out Driver (ROD).The main components of the TileCal ROD are the Digital Signal Processors (DSPs) placed on the Processing Unit (PU) daughterboards. This paper presents a detailed description of the code developed for the DSPs. The code is divided into two different parts: the first part contains the core functionalities and the second part the reconstruction algorithms. The core acts as an operating system and controls configuration, data reception and transmission and synchronization between front-end data and the Timing, Trigger and Control (TTC) information. The reconstruction algorithms implemented on the DSP are the Optimal Filtering (OF), Muon Tagging (MTag) and Missing ET calculation. The OF algorithm reconstructs the deposited energy and the phase of the signal for every calorimeter channel within a front-end module. This reconstructed energy is used by the MTag algorithm to tag low transverse momentum muons that may escape the ATLAS muon spectrometer Level 1 trigger whereas the Missing [E.sub.T] algorithm computes the total transverse energy and the projection on X and Y axis for the entire module that will be used by the Level 2 trigger system. Index Terms--ATLAS, digital signal processors, optimal filtering, read-out driver.

This paper presents the design of an intelligent front-end signal conditioning system for IR sensors. The system has been developed as an interface between a PbSe IR sensor matrix and a TMS320C67x digital signal processor. The system architecture ensures its scalability so it can be used for sensors with different matrix sizes. it includes an integrator based signal conditioning circuit, a data acquisition converter block, and a FPGA based advanced control block that permits including high level image preprocessing routines such as faulty pixel detection and sensor calibration in the signal conditioning front-end. During the design phase virtual instrumentation technologies proved to be a very valuable tool for prototyping when choosing the best A/D converter type for the application. Development time was significantly reduced due to the use of this technology. Index Terms--Data acquisition, digital signal processors, FPGA, signal conditioning, virtual instrumentation.

In this brief, the design of residue number system (RNS) to binary converters for a new powers-of-two related three-moduli set {[2.sup.n+1] - 1, [2.sup.n], [2.sup.n] - 1} is considered. This moduli set uses moduli of uniform word length (n to n + 1 bits). It is derived from a previously investigated four-moduli set {[2.sup.n] - 1, [2.sup.n], [2.sup.n] + 1, [2.sup.n+1] - 1}. Three RNS-to-binary converters are proposed for this moduli set: one using mixed radix conversion and the other two using Chinese Remainder Theorem. Detailed architectures of the three converters as; well as comparison with some earlier proposed converters for three-moduli sets with uniform word length and the four-moduli set {[2.sup.n] - 1, [2.sup.n], [2.sup.n] + 1, [2.sup.n+1] - 1} are presented. Index Terms--Digital signal processor (DSP), residue number system (RNS), reverse converters, three-moduli sets.

The article examines reconstruction of discrete-valued signals based on robust control ideas. There is perfect reconstruction of strategies.

This paper introduces detail design of semi-custom CMOS Fast Fourier Transform (FFT) architecture for computing 16-point radix-4 FFT. FFT is one of the most widely used algorithms in digital signal processing. It is used in many signal processing and communication application as an important block for various multi-carrier systems such as for WLAN (Wireless local area network). This paper describes the design of an ASIC (Application Specific Integrated Circuit) CMOS FFT processor for 16-point radix-4 complex FFT computation, realized utilizing 0.18[micro]m standard CMOS technology. Fixed point data format is preferred in comparison of floating point data format for a shorter dynamic range and reduced hardware utilization; thus, catering to the needs of portability. Furthermore, computations results at particular stage are rounded to avoid overflow issue and to be stored in register. The computation speed of the design is observed to be 50MHz after the synthesis process. Compared to traditional radix-4 algorithm the architecture proposed for 16-point FFT results in 1.73% of power saving and 5.5% of area reduction. Key words: ASIC, Digital Signal Processing (DSP), FFT, INTRODUCTION The Discrete Fourier Transform (DFT) plays a significantly important role in many applications of digital signal processing. Basically, it has been applied in a wide range of fields such [...]

This paper presents real-time verification of an artificial neural network (ANN) and adaptive neuro-fuzzy inference system (ANFIS) based rotor position estimation techniques for a 6/4 pole switched reluctance motor (SRM) drive system. The techniques estimate rotor position by measuring the three-phase voltages and currents and using magnetic characteristics of the SRM, with the aid of an ANN and ANFIS, in real-time environments. The rotor position estimating techniques are used in a high-performance sensorless variable speed SRM drive. A digital signal processor, TMS320F2812, executes the rotor position estimation. To verify the performance of the ANN and ANFIS based rotor position estimation techniques, a rotor position sensor is mounted with the drive system. The experimental results show that the ANN and ANFIS based rotor position estimation techniques provide good performance at different operating conditions. Index Terms--Adaptive neuro-fuzzy inference system (ANFIS), artificial neural network (ANN) based rotor position estimation, digital signal processor, sensorless operation, switched reluctance motor (SRM).

What is believed to be a new approach for the design and analysis of a reconfigurable optical square pulse generator using the concept of temporal optical integration and the digital signal processing method is presented. The reconfigurable square pulse generator is synthesized using compact active semiconductor-based waveguide technology, and it consists simply of the cascade of a tunable microring resonator (or a tunable all-pole filter) and a tunable asymmetrical Mach-Zehnder interferometer (or a tunable all-zero filter). The reconfigurable generator can convert an input picosecond pulse (i.e., soliton or Gaussian pulse) into an optical square pulse. The pulse width of the generated square pulse can be adjusted by controlling the time delay of a variable delay element in the tunable all-zero filter. The reconfigurable generator can convert an input picosecond pulse train into return-to-zero (RZ) and non-return-to-zero (NRZ) signals with square pulse shapes. The repetition rates of the generated RZ and NRZ signals can be varied by adjusting the bit period of the input picosecond pulse train, the input pulse width, and the time delay of the variable delay element. The effect of the deviation of the parameter values on the generator performance is also studied. OCIS codes: 070.1170, 130.0130, 230.0230.