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We present a fully integrated cryogenic controller for electrostatically controlled quantum dots (QDs) implemented in a commercial 22-nm fully depleted silicon-on-insulator CMOS process and operating in a quantum regime. The QDs are realized in local well areas of transistors separated by tunnel barriers controlled by voltages applied to gate terminals. The QD arrays (QDA) are co-located with the control circuitry inside each quantum experiment cell, with a total of 28 of such cells comprising this system-on-chip (SoC). The QDA structure is controlled by small capacitive digital-to-analog converters (CDACs) and its quantum state is measured by a single-electron detector. The SoC operates at a cryogenic temperature of 3.4K. The occupied area of each QDA is $0.7 \times 0.4\mu \text{m}^2$ , while each QD occupies only $20 \times 80 \text{nm}^2$ . The low power and miniaturized area of these circuits are an important step on the way for integration of a large quantum core with millions of QDs, required for practical quantum computers. The performance and functionality of the CDAC are validated in a loop-back mode with the detector sensing the CDAC-compelled electron tunneling from the quantum point contact (QPC) node into the quantum structure. The position of the injected charge inside the QDA is intended to be controlled through the CDAC codes and programmable pulse width. Quantum effects are shown by an experimental characterization of charge injection and quantization into the QDA consisting of three coupled QDs. The charge can be transferred to a QD and sensed at the QPC, and this process is controlled by the relevant voltages and CDACs.

In this paper, we introduce a reconfigurable oscillatory network that generates a synchronous and distributed clocking signal. We propose an accurate model of the network to facilitate the study of its design space and ensure that it operates in its optimal, synchronous mode. The network is designed and implemented in a fully integrated 65-nm CMOS system-on-chip that utilizes coupled all digital phase locked loops interconnected as a Cartesian grid. The model and measurements demonstrate frequency and phase synchronization even in the presence of noise and random initial conditions. This network is proposed for small-scale multiple input multiple-output systems that require complete synchronization both in frequency and in phase.