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So-called “tagless” caches have become common as a means to deal with the vast L4 last-level caches (LLCs) enabled by increasing device density, emerging memory technologies, and advanced integration capabilities (e.g., 3-D). Tagless schemes often result in intercache entanglement between tagless cache (L4) and the cache (L3) stewarding its metadata. We explore new cache organization policies that mitigate overheads stemming from the intercache-level replacement entanglement. We incorporate support for explicit tiling shapes that can better match software access patterns to improve the spatial and temporal locality of large block allocations in many essential computational kernels. To address entanglement overheads and pathologies, we propose new replacement policies and energy-friendly mechanisms for tagless LLCs, such as restricted block caching (RBC) and victim tag buffer caching (VBC) to incorporate L4 eviction costs into L3 replacement decisions efficiently. We evaluate our schemes on a range of linear algebra kernels that are software tiled. RBC and VBC demonstrate a reduction in memory traffic of 83/4.4/67% and 69/35.5/76% for 8/32/64 MB L4s, respectively. Besides, RBC and VBC provide speedups of 16/0.3/0.6% and 15.7/1.8/0.8%, respectively, for systems with 8/32/64 MB L4, over a tagless cache with an LRU policy in the L3. We also show that matching the shape of the hardware allocation for each tagless region superblocks to the access order of the software tile improves latency by 13.4% over the baseline tagless cache with reductions in memory traffic of 51% over linear superblocks. [ABSTRACT FROM AUTHOR]

Negative capacitance FET (NCFET) has become a research topic of interest in recent years due to its interesting properties. It has the ability to retain the polarization state even in the absence of electric field. By virtue of this ability, it can be designed as a nonvolatile memory. NCFET can also be configured as a steep-slope switch and thereby providing energy efficiency while used in digital designs. However, the benefits offered by NCFETs for analog circuit domain has not well reported. In this paper, we analyze the impact of body effect on an NCFET-based bootstrapped switch and illustrate that the linearity of NCFET-based switch can be improved resulting from the internal amplification of the employed NCFET. When designed at 0.6-V supply (${V}_{\text {dd}}$), results show that the variation of the on resistance of the bootstrapped switch is about $67~\Omega $ during the sampling period, which is one-third smaller than the MOSFET-based switch. As a result, the sampling linearity is improved and the distortion at the output can be decreased. On condition that the Nyquist input frequency is 10 MHz, the proposed NCFET-based bootstrapped switch succeeds in improving the total harmonic distortion performance by 16.7 dB, compared with that of a conventional MOSFET-based bootstrapped switch. [ABSTRACT FROM AUTHOR]

This brief exploits the fusion of low-power logic and nonvolatile memory inside the emerging ferroelectric FETs (FeFETs) and proposes a new nonvolatile D flip-flop (nvDFF) through the device-circuit co-design. Compared with existing FeFET-based nvDFFs with on-demand control of backup and restore (B&R), the area overhead is lowered by half, and the routing cost is reduced with embedded backup control into the supply voltage. Circuit simulations show below 5% energy-delay overhead in the normal mode and femtojoule B&R energy. This new nvDFF promises area- and energy-efficient nonvolatile computing for power-gating and energy-harvesting applications. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel memory architecture with the capability of single-cycle row-wise/column-wise accesses. Such an architecture is highly suitable for workloads featuring spatial locality in multiple dimensions, which is a characteristic of many matrix and array operations. We describe in detail the circuit design techniques enabling the proposed architectures, as well as the viability of emerging memory technologies based on ferroelectric transistors (FEFETs) for our design. Compared to FEFET memory with standard 1-D access, we achieve 5% energy savings for the proposed memory featuring 2-D read and 93% energy savings for memory with 2-D read and write, for 32 bit column read and write. In addition, we get around 11% and 95% delay savings for 2-D read-enabled memory and 2-D read-write memory, respectively. The application analysis shows that 2-D read-enabled memory achieves around 86% average decrease in row-buffer transactions in $256\times 256$ size matrix operations without any array area increase. The 2-D read write memory offers 87% decrease in row-buffer transactions with 28.5% increase in array area compared to the 1-D FEFET memory. [ABSTRACT FROM AUTHOR]

Negative capacitance FETs (NCFETs) have attracted significant interest due to their steep-switching capability at a low voltage and the associated benefits for implementing energy-efficient Boolean logic. While most existing works aim to avoid the ID – VG hysteresis in NCFETs, this paper exploits this hysteresis feature for logic-memory synergy and presents a custom-designed nonvolatile NCFET D flip-flop (DFF) that maintains its state during power outages. This paper also presents an NCFET fabricated for this purpose, showing <10 mV/decade steep hysteresisedges and high, up to seven orders inmagnitude, R\text {DS} ratio between the two polarization states. With a device-circuit codesign that takes advantage of the embedded nonvolatility and the high R\text {DS} ratio, the proposed DFF consumes negligible static current in backup and restore operations, and remains robust even with significant global and local ferroelectric material variations across a wide 0.3–0.8 V supply voltage range. Therefore, the proposed DFF achieves energy-efficient and low-latency backup and restore operations. Furthermore, it has an ultralow energy-delay overhead, below 2.1% in normal operations, and operates using the same voltage supply as the Boolean logic elements with which it connects. This promises energy-efficient nonvolatile computing in energy-harvesting and power-gating applications. [ABSTRACT FROM PUBLISHER]

Nonvolatile SRAM (nvSRAM) has emerged as a promising approach to reducing the standby energy consumption by storing the state into an in situ nonvolatile memory element and shutting down the power supply. Existing nvSRAM solutions based on a nonvolatile backup in magnetic tunnel junction and ReRAM, however, are costly in backup and restore energy due to static current. This cost results in a long break-even time (BET) when compared with a lowered voltage standby volatile SRAM. This brief proposes an nvSRAM based on ferroelectric FETs (FeFETs) that are capable of fully avoiding such static current. A simple differential backup and restore circuitry is proposed, achieving sub-fJ/cell total energy per backup and restore operation at the 10-nm node. This leads to hundreds of times BET improvement over existing ReRAM nvSRAM solutions. This nvSRAM also indicates the future FeFET design trends for such memory-logic synergy. [ABSTRACT FROM PUBLISHER]

Field programmable gate array (FPGA) is widely used in the acceleration of deep learning applications because of its reconfigurability, flexibility, and fast time-to-market. However, conventional FPGA suffers from the trade-off between chip area and reconfiguration latency, making efficient FPGA accelerations that require switching between multiple configurations still elusive. Here, we propose a ferroelectric field-effect transistor (FeFET)-based context-switching FPGA supporting dynamic reconfiguration to break this trade-off, enabling loading of arbitrary configuration without interrupting the active configuration execution. Leveraging the intrinsic structure and nonvolatility of FeFETs, compact FPGA primitives are proposed and experimentally verified. The evaluation results show our design shows a 63.0%/74.7% reduction in a look-up table (LUT)/connection block (CB) area and 82.7%/53.6% reduction in CB/switch box power consumption with a minimal penalty in the critical path delay (9.6%). Besides, our design yields significant time savings by 78.7 and 20.3% on average for context-switching and dynamic reconfiguration applications, respectively. [ABSTRACT FROM AUTHOR]