Search

Event cameras have been successfully applied to visual place recognition (VPR) tasks by using deep artificial neural networks (ANNs) in recent years. However, previously proposed deep ANN architectures are often unable to harness the abundant temporal information presented in event streams. In contrast, deep spiking networks exhibit more intricate spatiotemporal dynamics and are inherently well-suited to process sparse asynchronous event streams. Unfortunately, directly inputting temporal-dense event volumes into the spiking network introduces excessive time steps, resulting in prohibitively high training costs for large-scale VPR tasks. To address the aforementioned issues, we propose a novel deep spiking network architecture called Spike-EVPR for event-based VPR tasks. First, we introduce two novel event representations tailored for SNN to fully exploit the spatio-temporal information from the event streams, and reduce the video memory occupation during training as much as possible. Then, to exploit the full potential of these two representations, we construct a Bifurcated Spike Residual Encoder (BSR-Encoder) with powerful representational capabilities to better extract the high-level features from the two event representations. Next, we introduce a Shared & Specific Descriptor Extractor (SSD-Extractor). This module is designed to extract features shared between the two representations and features specific to each. Finally, we propose a Cross-Descriptor Aggregation Module (CDA-Module) that fuses the above three features to generate a refined, robust global descriptor of the scene. Our experimental results indicate the superior performance of our Spike-EVPR compared to several existing EVPR pipelines on Brisbane-Event-VPR and DDD20 datasets, with the average Recall@1 increased by 7.61% on Brisbane and 13.20% on DDD20., Comment: 14 pages, 10 figures

Event cameras offer promising properties, such as high temporal resolution and high dynamic range. These benefits have been utilized into many machine vision tasks, especially optical flow estimation. Currently, most existing event-based works use deep learning to estimate optical flow. However, their networks have not fully exploited prior hidden states and motion flows. Additionally, their supervision strategy has not fully leveraged the geometric constraints of event data to unlock the potential of networks. In this paper, we propose EV-MGRFlowNet, an unsupervised event-based optical flow estimation pipeline with motion-guided recurrent networks using a hybrid motion-compensation loss. First, we propose a feature-enhanced recurrent encoder network (FERE-Net) which fully utilizes prior hidden states to obtain multi-level motion features. Then, we propose a flow-guided decoder network (FGD-Net) to integrate prior motion flows. Finally, we design a hybrid motion-compensation loss (HMC-Loss) to strengthen geometric constraints for the more accurate alignment of events. Experimental results show that our method outperforms the current state-of-the-art (SOTA) method on the MVSEC dataset, with an average reduction of approximately 22.71% in average endpoint error (AEE). To our knowledge, our method ranks first among unsupervised learning-based methods., Comment: 11 pages, 7 figures

We demonstrate ferroelectric (FE) memory transistors on a crystalline silicon channel with endurance exceeding $10^{10}$ cycles. The ferroelectric transistors (FeFETs) incorporate a high-$\kappa$ interfacial layer (IL) of thermally grown silicon nitride (SiN$_x$) and a thin 4.5 nm layer of Zr-doped FE-HfO$_2$ on a $\sim$30 nm SOI channel. The device shows a $\sim$ 1V memory window in a DC sweep of just $\pm$ 2.5V, and can be programmed and erased with voltage pulses of $V_G= \pm$ 3V at a pulse width of 250 ns. The device also shows very good retention behavior. These results indicate that appropriate engineering of the IL layer could substantially improve FeFET device performance and reliability.

A comprehensive study of the scaling of negative capacitance FinFET (NC-FinFET) is conducted with TCAD. We show that the NC-FinFET can be scaled to "2.1nm node" and almost "1.5nm node" that comes two nodes after the industry "3nm node," which has 16nm Lg and is the last FinFET node according to the International Roadmap for Devices and Systems (IRDS). In addition, for the intervening nodes, NC-FinFET can meet IRDS Ion and Ioff target at target-beating VDD. The benefits of negative capacitance (NC) include improved subthreshold slope (SS), drain-induced barrier lowering (DIBL), Vt roll-off, transconductance over Id (Gm/Id), output conductance over Id (Gd/Id), and lower VDD. Further scaling may be achieved by improving capacitance matching between ferroelectric (FE) and dielectric (DE).

Recent measurements on ultra-thin body Negative Capacitance Field Effect Transistors have shown subthreshold behaviors that are not expected in a classical MOSFET. Specifically, subthreshold swing was found to decrease with increased gate bias in the subthreshold region for devices measured over multiple gate lengths down to 30 nm. In addition, improvement in the subthreshold swing relative to control devices showed a non-monotonic dependence on the gate length. In this paper, using a Landau-Khanatnikov ferroelectric gate stack model calibrated with measured Capacitance-Voltage, we show that both these anomalous behaviors can be quantitatively reproduced with TCAD simulations., Comment: Submitted to IEEE Electron Device Letter and is currently under review

Compact device models play a significant role in connecting device technology and circuit design. BSIM-CMG and BSIM-IMG are industry standard compact models suited for the FinFET and UTBB technologies, respectively. Its surface potential based modeling framework and symmetry preserving properties make them suitable for both analog/RF and digital design. In the era of artificial intelligence / deep learning, compact models further enhanced our ability to explore RRAM and other NVM-based neuromorphic circuits. We have demonstrated simulation of RRAM neuromorphic circuits with Verilog-A based compact model at NCKU. Further abstraction with macromodels is performed to enable larger scale machine learning simulation., Comment: Invited talk at the Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD), Kitakyushu, Japan, July 2018

It is well known that one needs an external source of energy to provide voltage amplification. Because of this, conventional circuit elements such as resistors, inductors or capacitors cannot provide amplification all by themselves. Here, we demonstrate that a ferroelectric can cause a differential amplification without needing such an external energy source. As the ferroelectric switches from one polarization state to the other, a transfer of energy takes place from the ferroelectric to the dielectric, determined by the ratio of their capacitances, which, in turn, leads to the differential amplification. {This amplification is very different in nature from conventional inductor-capacitor based circuits where an oscillatory amplification can be observed. The demonstration of differential voltage amplification from completely passive capacitor elements only, has fundamental ramifications for next generation electronics.