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Metal oxide thin‐film transistors (TFTs) offer remarkable opportunities for applications in emerging transparent and flexible microelectronics. Unfortunately, their performance is hindered by limitations associated with parasitic effects, such as parasitic electrode overlap capacitances and high contact resistance, which can severely limit their dynamic behavior. Here, an innovative method is reported to fabricate coplanar self‐aligned‐gate (SAG) indium‐gallium‐zinc‐oxide (IGZO) transistors with engineered source/drain contacts. The manufacturing process starts with the deposition and patterning of a gate electrode/dielectric stack and its functionalization with an organic self‐assembled monolayer (SAM) as the surface energy modifier. A second gold (Au) electrode is subsequently deposited over the gate electrode stack. The overlapping region between the two electrodes is removed via self‐delamination under mild sonication, forming perfectly aligned coplanar Au‐Gate‐Au electrodes. Device fabrication is completed with the spin coating of the IGZO precursor, followed by rapid photonic curing. Replacing the gold source/drain contact with bimetallic electrodes such as Au/In and Au/ITO enables a reduction in contact resistance and improves the transistor performance remarkably without increasing manufacturing complexity. The method is highly scalable, robust, and applicable to other semiconductor materials. [ABSTRACT FROM AUTHOR]

We demonstrate the compensation of device‐to‐device variation in threshold voltage using programmable ferroelectric indium‐gallium‐zinc‐oxide thin‐film transistors. Furthermore, degradationinduced threshold voltage shift can be mitigated by programming, setting the characteristics back to their pristine state. This can be a promising alternative for the replacement of complex VT compensation circuits in display applications. [ABSTRACT FROM AUTHOR]

Brain‐inspired neuromorphic computing has drawn significant attraction as a promising technology beyond von Neumann architecture by using the parallel structure of synapses and neurons. Various artificial synapse configurations and materials have been proposed to emulate synaptic behaviors for human brain functions such as memorizing, learning, and visual processing. Especially, the memory type indium‐gallium‐zinc‐oxide (IGZO) synaptic transistor adopting a charge trapping layer (CTL) has the advantages of high stability and a low leakage current of the IGZO channel. However, the CTL material should be carefully selected and optimized to overcome the low de‐trapping efficiency, resulting from difficulty in inducing holes in the IGZO channel. In this paper, IGZO is adopted as a CTL and found out that making it degenerated is crucial to improving de‐trapping efficiency. The degenerate CTL, where electrons remain as free electrons, induces Fowler‐Nordheim tunneling by increasing the electric field across the tunneling layer. As a result, the synaptic transistor represents a high linearity of potentiation (αp: −0.03) and depression (αd: −0.47) with 64 conductance levels, which enables the spiking neural network simulation to achieve high accuracy of 98.08%. These experimental results indicate that the synapse transistor can be one of the promising candidates for neuromorphic applications. [ABSTRACT FROM AUTHOR]

Abstract Brain‐inspired neuromorphic computing has drawn significant attraction as a promising technology beyond von Neumann architecture by using the parallel structure of synapses and neurons. Various artificial synapse configurations and materials have been proposed to emulate synaptic behaviors for human brain functions such as memorizing, learning, and visual processing. Especially, the memory type indium‐gallium‐zinc‐oxide (IGZO) synaptic transistor adopting a charge trapping layer (CTL) has the advantages of high stability and a low leakage current of the IGZO channel. However, the CTL material should be carefully selected and optimized to overcome the low de‐trapping efficiency, resulting from difficulty in inducing holes in the IGZO channel. In this paper, IGZO is adopted as a CTL and found out that making it degenerated is crucial to improving de‐trapping efficiency. The degenerate CTL, where electrons remain as free electrons, induces Fowler‐Nordheim tunneling by increasing the electric field across the tunneling layer. As a result, the synaptic transistor represents a high linearity of potentiation (αp: −0.03) and depression (αd: −0.47) with 64 conductance levels, which enables the spiking neural network simulation to achieve high accuracy of 98.08%. These experimental results indicate that the synapse transistor can be one of the promising candidates for neuromorphic applications.

Atomic layer deposition (ALD) has been studied extensively to employ oxide semiconductor thin film transistor (TFT) including both active layer and gate insulator (GI). Herein, we developed an ALD sandwich structure, which deposits both semiconductor and GI by ALD. In contrast to the previous results using sputter In-Ga-Zn-O (IGZO), ALD sandwich structure IGZO TFT exhibited severe deterioration in its electrical performance when the Al2O3 was adopted for both buffer layer and GI application. Through measurement of hydrogen permeability of ALD insulators and secondary ion mass spectroscopy of each sandwich structure after annealing, we found a hydrogen accumulation effect between Al2O3 and ALD IGZO interface layer, which caused deterioration of electrical performance. In contrast, TFTs with ALD SiO2, which has proper hydrogen diffusivity, chosen as the buffer and GI had favorable electric properties of 28.17 cm2/ $\text{V}\cdot \text{s}$ , 0.20 V/dec, 0.96, and 0.12 V for the mobility, ${V}_{\text {th}}$ , subthreshold swing (SS), and hysteresis. In this regard, an optimized GI structure via the ALD SiO2 and Al2O3 in situ process based on excellent interface formation with the semiconductor and hydrogen barrier performance, respectively, was developed. This functional GI structure consisting of SiO2 and Al2O3 exhibited excellent TFT characteristics (27.52 cm2/ $\text{V}\cdot \text{s}$ , 0.24 V/dec, and 1.07 V for the mobility, SS, and ${V}_{\text {th}}$ , respectively) with improved stability even after hydrogen annealing, which was used to examine the resistance to external hydrogen, showing a threshold voltage shift of −0.15 V and a SS shift of 0.01 V/dec. [ABSTRACT FROM AUTHOR]

Sputtered amorphous indium-gallium-zinc-oxide (a-IGZO) Schottky barrier diodes (SBDs) were comparatively investigated without and with a passivation layer (PL). The a-IGZO SBDs without PLs were found to be highly unstable in the atmosphere and under electrical stress. During the implementation of silicon dioxide (SiO2) PL, the associated thermal oxidization and hydrogen doping resulted in high-performance metrics, including an ideality factor close to the unity, a high Schottky barrier of 0.82 eV, and a large current rectification ratio of over 108. Benefited from the PL protection and ideal Schottky contact, the environmental and electrical stabilities of SBDs were significantly enhanced. [ABSTRACT FROM AUTHOR]

Herein, high-performance solution-processed amorphous indium–gallium–zinc– oxide (a-IGZO) thin-film transistors (TFTs) with low trap densities due to postdeposition annealing (PDA) are processed with a low-thermal-budget microwave (MW) heat treatment. To verify the MW effectiveness, the composition ratio of a-IGZO thin films and the electrical characteristics of TFTs prepared by conventional thermal annealing (CTA) are compared. An X-ray photoelectron spectroscopy (XPS) analysis reveals that MW annealing (MWA) improves the film quality more effectively than CTA. a-IGZO TFTs treated by MWA or CTA are fabricated to evaluate their electrical characteristics. MWA is more effective than CTA in improving the performance, such as hysteresis, subthreshold swing (SS), field effect mobility (μFE), and on/off current ratio (Ion/Ioff ). MWA provides lower interfacial trap density (Dit) and volume trap density (Nt) than CTA. To evaluate instability, the threshold voltage (VTH) shift is monitored using positive and negative gate-bias stress tests. MWA demonstrates better reliability than CTA. In conclusion, high-performance solution-based a-IGZO TFTs can be implemented by lowering the charge traps in the a-IGZO channel using MWA. [ABSTRACT FROM AUTHOR]

Although insertion of a thin insulating layer between metal electrodes and a semiconducting channel is an effective way to improve device performance, the exact reason for improvement in performance is not elucidated. Herein, the role of an Al2O3 interlayer sandwiched between Al metal electrodes and an amorphous indium–gallium–zinc–oxide semiconducting channel is systematically investigated. The Al2O3 interlayer results in not only a good transistor performance with increased on current but also improved gate bias stress stability. The improvement is primarily attributed to a doping effect and mitigation of interface defects. Energy‐band diagrams, experimentally obtained from temperature‐variable electrical characterization and electrostatic force microscopy, validate the channel doping effect, which increase the tunneling probability of the electron charge carriers via a reduction of the Schottky barrier width. A comprehensive study on the influence of various processing parameters, including Al2O3 thickness, post‐annealing treatment conditions, and types of electrodes, on the transistor device is also performed. This approach guides the practical implementation of stable sol–gel oxide‐based thin‐film transistors and promotes integrated circuitry applications. [ABSTRACT FROM AUTHOR]

Solution‐processed indium‐gallium‐zinc oxide (IGZO) thin film transistors (TFTs) have become well known in recent decades for their promising commercial potential. However, the unsatisfactory performance of small‐sized IGZO TFTs is limiting their applicability. To address this issue, this work introduces an interface engineering method of bi‐functional acid modification to regulate the interfaces between electrodes and the channels of IGZO TFTs. This method increases the interface oxygen vacancy concentration and reduces the surface roughness, resulting in higher mobility and enhanced contact at the interfaces. The TFT devices thus treated display contact resistance reduction from 9.1 to 2.3 kΩmm, as measured by the gated four‐probe method, as well as field‐effect mobility increase from 1.5 to 4.5 cm2 (V s)−1. Additionally, a 12 × 12 organic light emitting diode display constructed using the acid modified IGZO TFTs as switching and driving elements demonstrate the applicability of these devices. [ABSTRACT FROM AUTHOR]

The rapid development of mobile and internet‐of‐thing devices demands continuous scaling of metal–insulator–semiconductor field‐effect transistors for high‐resolution and low‐power displays. However, such technology is limited by inadequate scaling of supply voltage and sophisticated dielectric engineering. Here, to enable continued scaling, indium–gallium–zinc‐oxide (InGaZnO) tunnel field‐effect transistor (TFET) and junction field‐effect transistor (JFET) are designed and fabricated based on vertically stacked black phosphorus (BP)/InGaZnO van der Waals heterojunctions. By varying BP thickness, BP/InGaZnO heterojunctions can be operated as forward rectifying diode, Zener diode, and backward rectifying diode, respectively. Room‐temperature negative‐differential‐resistance behavior with large peak‐to‐valley ratio of 2.1 and high tunneling current density of 160 mA mm−2 is obtained in thick‐BP/InGaZnO heterojunction. On this basis, sub‐thermionic subthreshold swing (SS) of 11 mV dec−1 is achieved in InGaZnO TFET. Meanwhile, the InGaZnO JFET based on thin‐BP/InGaZnO heterostructure exhibits good transistor performance of on/off ratio exceeding 105, high field‐effect mobility of 23.5 cm2 V s−1, negligible hysteresis, and improved SS of 83 mV dec−1. The BP/InGaZnO heterojunction is possibly the only device architecture so far to realize the amorphous metal‐oxide‐semiconductors TFET and JFET, thus providing promising pathways for further thin‐film transistor technology. [ABSTRACT FROM AUTHOR]

Indium–gallium–zinc-oxide thin-film transistors gated with solution-processed, ultra-thin AlxOy have been fabricated on a plastic substrate. The effects of bending on the gate dielectric in terms of leakage current density and capacitance density have been studied. The devices show a low operating voltage of less than 1 V, a high current on/off ratio >105, and a low subthreshold swing <90 mV/decade. The devices maintain their high performance even when flexed to a curvature radius of 11 mm. As a result, such devices possess a great potential for low-power, flexible electronics. [ABSTRACT FROM AUTHOR]

Metal-oxide high- k dielectric films have received considerable attention in lowering the driving voltage and power consumption in semiconductor devices. Here, we demonstrate sub-volt operating metal-oxide thin-film transistors (TFTs) using solution-processed high- k gadolinium-doped hafnium oxide (HGO) dielectric films. Particularly, the HGO dielectric films were fabricated using a solution combustion synthesis (SCS) method using acetylacetone and 1,1,1-trifluoroacetylacetone as cofuels. The HGO dielectric films exhibited low leakage current of 2.7 × 10−6 A/cm2 at 1 MV/cm and dielectric constant of ∼17. It was found that the Gd doping had a significant impact on improving the leakage current characteristics compared to the undoped HfO 2 films (leakage current of ∼10−2 A/cm2 at 1 MV/cm). By employing the high- k HGO gate dielectric layer, we demonstrated 0.5 V-operating indium-gallium-zinc-oxide TFTs exhibiting field-effect mobility of 3.55 cm2/Vs, on/off ratio of 5.9 × 105, and subthreshold slope of 75 mV/decade. We investigated the effects of cofuel concentration on the film morphology and dielectric properties of HGO films to determine the optimal cofuel concentration for SCS. Furthermore, X-ray photoelectron spectroscopy was performed to reveal the role of Gd doping in improving the dielectric properties in correlation with the oxygen vacancy formation. Based on these results, we claim that the high- k HGO film fabricated through the SCS route can be a promising candidate for realizing sub-volt operating TFTs for low-power consumption. [Display omitted] • High- k Gd-doped HfO 2 dielectric films are fabricated using a solution process. • Influences of Gd doping and cofuel concentrations on the dielectric properties are investigated. • The effects of annealing time on oxygen binding states, crystalline structure, and dielectric properties are investigated. • Sub-volt IGZO TFTs are demonstrated using Gd-doped HfO 2 gate dielectric layer. [ABSTRACT FROM AUTHOR]

Abstract We demonstrate the characteristics of a conductive-bridging random access memory (CBRAM) with Cu/TiW/InGaZnO/Ga 2 O 3 /Pt stack structure. The addition of a thin metal-oxide layer (4.5 nm-thick Ga 2 O 3) in the bottom of the CBRAM device significantly increases the off-state resistance (R OFF) and the memory window. The IGZO bi-layer CBRAM shows the excellent memory performances, such as low operation current (down to 50 μA), high on/off resistance ratio (>103), high switching endurance (up to 103 cycles) and the capability of multi-level tuning. Meanwhile, high thermal stability was also achieved. Three decades of resistance window is constantly maintained beyond 104 s at 85 °C. The resistive switching stability and electrical uniformity of bi-layer IGZO/Ga 2 O 3 CBRAM device are obviously enhanced as compared with the one only with a single layer of IGZO film. These results have given a great potential for the transparent amorphous oxide semiconductor (TAOS)-based material utilizing in CBRAM stacks and integrating into the display circuits for future memory-in-pixel applications. Highlights • The IGZO/Ga 2 O 3 bilayer conductive-bridging random access memory (CBRAM) device was fabricated. • The high on/off resistance ratio (>103) and high switching endurance (>103 cycles) were obtained. • The Cu/TiW/IGZO/Ga 2 O 3 /Pt CBRAM device has a great potential for the future memory applications. [ABSTRACT FROM AUTHOR]

The amorphous indium gallium zinc oxide thin-film transistors (TFTs) with a multilayer high-k gate stack are investigated in this research. In order to achieve a high quality gate insulator for plastic flexible display application, the multilayer high-k gate stacks (SiO 2 /TiO 2 /HfO 2 ) are deposited by a low-temperature physical vapor deposition (PVD) process. On the other hands, an interfacial layer between the high-k stack and metal oxide channel is important for the device performance. The effects of interfacial layer material (SiO 2 or Ga 2 O 3 ) are also discussed in this report. The devices with SiO 2 interfacial layer show a high on/off current ratio of ~7 × 10 7 for its low gate leakage current, a small sub-threshold swing of 0.093 V/decade and a high field-effect mobility of ∼37.8 cm 2 /Vs for its good interface condition and low interface defeats. This research shows that the interface engineering of multilayer PVD gate stacks is necessary for oxide TFT fabrication. [ABSTRACT FROM AUTHOR]

Inspired by the neocortex of the human brain, neuromorphic systems are favorable for processing a variety of complex tasks, such as recognition, prediction, and optimization. To build such an intelligent system, neuromorphic devices are in high demand. Here, photoelectric neuromorphic devices based on pulse light-stimulated low-voltage indium?gallium?zinc-oxide electric-double-layer transistors were investigated. Such devices can mimic some important synaptic behaviors, such as excitatory post-synaptic potentials, paired-pulse facilitation, and long-term plasticity in the form of photonic excitatory post-synaptic potentials. At last, depression mode to potentiation mode transition was also demonstrated by gate voltage modulation. Our photoelectric neuromorphic devices are interesting for photonic neuromorphic systems. [ABSTRACT FROM PUBLISHER]

Flexible electronics are attracting great interest in healthcare, where devices such as thin-film transistors (TFTs) on polymer substrates facilitate biomedical applications requiring complex circuits in soft packages. Consequently, a repeatable process to fabricate reliable, stable electronic components on flexible substrates is required. Here, thermoset thiol-ene/acrylate shape memory polymer (SMP) substrates house indium-gallium-zinc-oxide (IGZO) TFTs and logic circuits: resulting devices exhibit stable behavior after thermal annealing at 250 °C. Fabricated, annealed devices exhibit an average mobility of 15 ± 2.5 cm2 V−1 s−1 and show stability after bending and soaking in aqueous media. TFTs on SMPs are studied after mechanical bending tests with radii of curvature of 5 mm for 104 cycles over a 4 h time period. Other TFTs are soaked in phosphate-buffered saline solution at 37 °C for 1 week. Logic inverter circuits using IGZO TFTs on SMPs represent the ability to add complex circuitry onto thin film flexible electronics. This technology can enable a new generation of implantable devices for research in healthcare fields. [ABSTRACT FROM AUTHOR]

Advancement in thin-film transistor (TFT) technologies has extended to applications that can withstand extreme bending or folding. The changes of the performances of amorphous-indium-gallium-zinc-oxide (a-IGZO) TFTs on polyimide substrate after application of extreme mechanical bending strain are studied. The TFT designs include mesh and strip patterned source/drain metal lines as well as strip patterned a-IGZO semiconductor layer. The robustness of the a-IGZO TFTs with the strain of 2.17% corresponding to the radius of 0.32 mm is tested and no crack generation even after 60 000 bending cycles is found. The split of source/drain electrodes and semiconductor layer can improve the mechanical bending stability of the TFTs. This can be possible by using conventional TFT manufacturing process so that this technology can be easily applied to build robust TFT array for foldable displays. [ABSTRACT FROM AUTHOR]

Improving reliability of low-temperature polycrystalline silicon (LTPS) and amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs), components of low-temperature polycrystalline silicon and oxide (LTPO), is crucial for fabricating high-performance and high-stability LTPS and oxide semiconductor-based electronics and display products. However, improving the reliability of these TFTs simultaneously in a uniform and effective manner within a coplanar structure is challenging. In this work, high-pressure H 2 O post-annealing (H 2 O HPPA) as a post-treatment for LTPS and a-IGZO TFTs within a coplanar structure are proposed to improve the uniformity and stability of the electrical characteristics simultaneously. It was demonstrated that oxygen and hydrogen in the HPPA-passivated defect state at the channel/gate dielectric layer interfaces and bulk gate dielectric layers of LTPS and a-IGZO TFTs considerably improve the uniformity and stability of the electrical performance and morphologies of the interfaces. Thus, the distribution of electrical characteristics (mobility, threshold voltage, and subthreshold swing) in LTPS and a-IGZO TFTs was reduced by more than 2-fold, and the trap charge densities at their interfaces and bulk gate dielectric layers were reduced by approximately 1.6-fold. Furthermore, the threshold voltage shift was decreased in both LTPS and a-IGZO-TFTs fabricated with H 2 O HPPA under negative and positive bias temperature stresses, respectively. The proposed H 2 O HPPA method can effectively facilitate the industry-level application of LTPS and oxide semiconductor-based electronics and display electronics. • The effect of LTPS and a-IGZO thin film transistors fabricated by high-pressure H 2 O post-annealing were analyzed. • O 2 and H 2 induced in H 2 O HPPA suppress defects in dielectric/channel interface and dielectric bulk of LTPS and a-IGZO TFT. • Both LTPS and a-IGZO TFTs treated by H 2 O HPPA significantly improved uniformity and reliability of electrical performance. [ABSTRACT FROM AUTHOR]

The quest for high-performance flexible circuits call for scaling of the minimum feature size in thin-film transistors (TFTs). Although reduced channel lengths can guarantee an improvement in the electrical properties of the devices, proper design rules also play a crucial role to minimize parasitics when designing fast circuits. In this letter, systematic computer-aided design simulations have guided the fabrication of high-performance flexible operational amplifiers (opamps) and logic circuits based on indium–gallium–zinc-oxide TFTs. In particular, the performance improvements due to the use of an additional third metal layer for the interconnections have been estimated for the first time. Encouraged by the simulated enhancements resulting by the decreased parasitic resistances and capacitances, both TFTs and circuits have been realized on a free-standing 50- \mu \textm -thick polymide foil using three metal layers. Despite the thicker layer stack, the TFTs have shown mechanical stability down to 5-mm bending radii. Moreover, the opamps and the logic circuits have yielded improved electrical performance with respect to the architecture with two metal layers: gain-bandwidth-product increased by 16.9%, for the first one, and propagation delay ( tpd ) decreased by 43%, for the latter one. [ABSTRACT FROM PUBLISHER]

The degradation of thin-film transistors (TFTs) caused by the self-heating effect constitutes a problem to be solved for the next generation of displays. Aluminum nitride (AlN) is a viable alternative for gate dielectric of TFTs due to its good thermal conductivity, matching coefficient of thermal expansion to indium–gallium–zinc-oxide, and excellent stability at high temperatures. Here, AlN thin films of different thicknesses were fabricated by a low temperature reactive radio-frequency magnetron sputtering process, using a low cost, metallic Al target. Their electrical properties have been thoroughly assessed. Furthermore, the 200 nm and 500 nm thick AlN layers have been integrated as gate-dielectric in transparent TFTs with indium–gallium–zinc-oxide as channel semiconductor. Our study emphasizes the potential of AlN thin films for transparent electronics, whilst the functionality of the fabricated field-effect transistors is explored and discussed. [ABSTRACT FROM AUTHOR]

In the current study, dual-active layer amorphous indium-gallium-zinc-oxide (a-IGZO) TFT has been fabricated by sequential deposition of oxygen-rich layer on a top of oxygen-poor layer in the active layer through oxygen partial pressure control in order to improve reliability under negative bias illumination stress (NBIS) condition. The method is very simple as it is performed in situ without any post treatment. Reliability of a TFT that had a thickness of oxygen-poor layer and oxygen-rich active layer in the ratio of 6:4, quite improved with the threshold voltage shift Δ of a-IGZO TFT at around 3.2 V under NBIS condition of 1000 s in comparison with a TFT (8.5 V) that comprised only oxygen-poor active layer. The increased reliability is attributed to decrease interaction with ambient and the reduction in the total neutral oxygen vacancy concentration due to the oxygen rich layer at the back-channel region, which was confirmed by X-ray photoelectron spectroscopy (XPS) analysis. [ABSTRACT FROM AUTHOR]

We propose a compact multilayer thin film color pixel and a method for efficient transmissive color in the visible regime. When the angle of incidence (AOI) varies between 0° and 60°, there is almost no change of the transmitted color. Meanwhile, additional dielectric layers at the top and bottom of the hybrid structure work as anti-reflection (AR) layers, which greatly improve the transmission efficiency. The performance can be switched by adjusting the thickness of the film, as well as controlling the charge carrier concentration in a doped indium-gallium-zinc-oxide (IGZO). Besides their simple, large scale compatible, and electron beam lithography (EBL) free fabrication route, the designed structure provides relatively high efficiency, high color purity, and low crosstalk, which may provide some new insights for structural color applications. [ABSTRACT FROM AUTHOR]

Indium–gallium–zinc oxide (IGZO) thin films were prepared in a N 2 environment by varying the annealing pressure and then tested for NO 2 gas detection. These thin films, whose average thickness ranged between 5 and 100 nm, were deposited via the sputtering on alumina substrates equipped with interdigitated Au electrodes using an IGZO polycrystalline target (ZnO: Ga 2 O 3 :In 2 O 3 = 1:1:1 mol%). The effects of annealing pressure and environment were investigated. A superior sensor response (S) was observed when increasing the annealing pressure; the prepared IGZO thin film showed an S of –800 at an operating temperature of 250 °C for 25 ppm NO 2 gas. The recovery time decreased with increasing the annealing temperature. The sensor annealed at 400 °C at 3 atm showed superior selectivity to various gases and longtime stability of 60 days was attained. The role of the oxygen vacancies in the sensor performance was also investigated. • High pressure annealing (HPA) effect on Indium-Gallium-Zinc-Oxide (IGZO) films are demonstrated for high response to NO 2 gas. • Sensor response (S = R gas /R air) of S – 800 was achieved for 25 ppm concentration of NO 2 gas. • Modulation of Oxygen Vacancy (O vac) was observed by High pressure annealing on IGZO film. • IGZO Sensor show superior stability and selectivity. [ABSTRACT FROM AUTHOR]

[Display omitted] • We use self-assembled monolayers (SAMs) to reduce gate leakage of top-gated IGZO TFT. • We engineer the IGZO/dielectric interface by dipolar, silane-anchored SAMs. • We characterize SAMs in detail by a combination of several complementary techniques. • The SAMs providing a favorable built-in electric field to reduce the leakage current. • The results correlate well with electron accepting or donating characters of SAMs. Top gate (TG) thin film transistors (TFTs) featuring amorphous metal oxide semiconductors (a -MOS), such as indium-gallium-zinc-oxide (IGZO), bear a great potential for large-area flexible and transparent electronics. The fabrication costs of these devices can be noticeably reduced by introduction of solution processes instead of standard fabrication routes involving vacuum deposition and complicate photolithography. However, solution-processed TG a -MOS TFT often causes considerable gate leakage in comparison with vacuum-processed device. In this context, we present a simple and straightforward approach to reduce the gate leakage of IGZO-based TG TFTs, which predominantly involves solution-based procedures. We engineer the IGZO/insulator interface by dipolar, silane-anchored self-assembled monolayers (SAMs) providing a favorable built-in electric field to reduce the leakage current in TFTs. The parameter correlates well with the direction and value of the molecular dipole moment defined by either electron accepting or electron donating character of the terminal tail group. These SAMs, prepared by spin-coating procedure, were characterized in detail by a combination of several complementary experimental techniques, providing also a useful background information for the device experiments. [ABSTRACT FROM AUTHOR]

We report that a pulsed negative bias stress slightly deteriorates the photoelectric stability of amorphous InGaZnO thin-film transistors, whereas a dc negative bias stress induces a large threshold voltage shift under the light. In the case of pulsed bias stresses, many of photoexcited positive charges might be recombined during the interval between pulses while those charges under dc bias drift to the channel interface without recombination. Interfacial trap density measurements explain the effects of such photoexcited positive charges on the interface. [ABSTRACT FROM AUTHOR]

The thin-film-transistor (TFT) technology has attracted significant attention in account of the possibility to manufacture transistors on large and flexible substrates, at low processing temperatures and at a low cost. Next to the well-established amorphous silicon TFT technology used mostly for displays, the amorphous Indium-Gallium-Zinc-Oxide (IGZO) and Indium-Tin-Zinc-Oxide (ITZO) materials offer a higher current conductivity and thus a better performance. This makes them interesting candidates for TFT integrated circuits also beyond displays. However, integrated circuits can be easily damaged by electrostatic discharges (ESD) and require integrated protection solutions. To find possible vulnerabilities and solutions, this paper analyzes ESD robustness of two IGZO and one ITZO TFT device architecture. • Thin-film transistors are susceptive to damage from electrostatic discharges (ESD). • ESD damage to a pixel circuit is observed to be at first gradual and then abrupt. • Transistors connected in a diode configuration could be used for ESD protection. • Compound transistors with added Indium-Tin-Zinc-Oxide show best ESD performance. [ABSTRACT FROM AUTHOR]

Solution-processed metal oxides require a great deal of thermal budget in order to achieve the desired film properties. Here, we show that the deposition temperature of sprayed zirconium oxide (ZrOx) thin film can be lowered by exposing the film surface to an ultraviolet (UV) ozone treatment at room temperature. Atomic force microscopy reveals a smooth and uniform film with the root mean square roughness reduced from ~ 0.63 nm (UVO-O) to ~ 0.28 nm (UVO-120) in the UV–ozone treated ZrOx films. X-ray photoelectron spectroscopy analysis indicates the formation of a Zr–O network on the surface film, and oxygen vacancy is reduced in the ZrOx lattice by increasing the UV–ozone treatment time. The leakage current density in Al/ZrOx/p-Si structure was reduced by three orders of magnitude by increasing the UV-ozone exposure time, while the capacitance was in the range 290–266 nF/cm2, corresponding to a relative permittivity (k) in the range 5.8–6.6 at 1 kHz. An indium gallium zinc oxide (IGZO)-based thin film transistor, employing a UV-treated ZrOx gate dielectric deposited at 200 °C, exhibits negligible hysteresis, an Ion/Ioff ratio of 104, a saturation mobility of 8.4 cm2 V−1S−1, a subthreshold slope of 0.21 V.dec−1, and a Von of 0.02 V. These results demonstrate the potentiality of low-temperature sprayed amorphous ZrOx to be applied as a dielectric in flexible and low-power-consumption oxide electronics. [ABSTRACT FROM AUTHOR]