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Abstract Oxide semiconductors have gained significant attention in electronic device industry due to their high potential for emerging thin-film transistor (TFT) applications. However, electrical contact properties such as specific contact resistivity (ρ C) and width-normalized contact resistance (R C W) are significantly inferior in oxide TFTs compared to conventional silicon metal oxide semiconductor field-effect transistors. In this study, a multi-stack interlayer (IL) consisting of titanium nitride (TiN) and indium-gallium-tin-oxide (IGTO) is inserted between source/drain electrodes and amorphous indium-gallium-zinc-oxide (IGZO). The TiN is introduced to increase conductivity of the underlying layer, while IGTO acts as an n+-layer. Our findings reveal IGTO thickness (t IGTO)-dependent electrical contact properties of IGZO TFT, where ρ C and R C W decrease as t IGTO increases to 8 nm. However, at t IGTO > 8 nm, they increase mainly due to IGTO crystallization-induced contact interface aggravation. Consequently, the IGZO TFTs with a TiN/IGTO (3/8 nm) IL reveal the lowest ρ C and R C W of 9.0 × 10−6 Ω·cm2 and 0.7 Ω·cm, significantly lower than 8.0 × 10−4 Ω·cm2 and 6.9 Ω·cm in the TFTs without the IL, respectively. This improved electrical contact properties increases field-effect mobility from 39.9 to 45.0 cm2/Vs. This study demonstrates the effectiveness of this multi-stack IL approach in oxide TFTs.

Abstract In this paper, high-performance indium gallium oxide (IGO) thin-film transistor (TFT) with a double-gate (DG) structure was developed using an atomic layer deposition route. The device consisting of 10-nm-thick IGO channel and 2/48-nm-thick SiO2/HfO2 dielectric was designed to be suitable for a display backplane in augmented and virtual reality applications. The fabricated DG TFTs exhibit outstanding device performances with field-effect mobility (μ FE) of 65.1 ± 2.3 cm2V−1 s−1, subthreshold swing of 65 ± 1 mVdec−1, and threshold voltage (V TH) of 0.42 ± 0.05 V. Both the (μ FE) and SS are considerably improved by more than two-fold in the DG IGO TFTs compared to single-gate (SG) IGO TFTs. Important finding was that the DG mode of IGO TFTs exhibits the nearly temperature independent μ FE variations in contrast to the SG mode which suffers from the severe remote Coulomb scattering. The rationale for this disparity is discussed in detail based on the potential distribution along the vertical direction using technology computer-aided design simulation. Furthermore, the DG IGO TFTs exhibit a greatly improved reliability with negligible V TH shift of − 0.22 V under a harsh negative bias thermal and illumination stress condition with an electric field of − 2 MVcm−1 and blue light illumination at 80 °C for 3600 s. It could be attributed to the increased electrostatic potential that results in fast re-trapping of the electrons generated by the light-induced ionization of deep level oxygen vacancy defects.

ABSTRACTHigh-performance electrochromic devices (ECDs) were fabricated by introducing indium tin oxide/silver/indium tin oxide (IAI) multilayers as a transparent conducting oxide (TCO) electrode in conjunction with microstructural tailoring of tungsten trioxide (WO3) as an electrochromic (EC) layer. A 15-nm-thick Ag film with a preferential orientation of (111) and smooth morphology resulted in a high optical transmittance of 90.9% and sheet resistance 16.7 Ω/sq, making it a suitable TCO. In addition, the open network WO3 film used as an EC layer was deposited by carefully controlling the chamber pressure during the sputtering process. A high chamber pressure (2.0 Pa) resulted in a WO3 film with the lowest mass density (5.72 g/cm3) and a rough morphology. Half-cell ECDs consisting of a TCO bottom electrode (BE)/WO3 stack immersed in LiClO4 electrolyte were fabricated to verify the impact of using the IAI multi-layer stack and tailored WO3 film as a TCO and EC layer, respectively. Significant enhancement in terms of coloration efficiency was achieved for the ECDs by adopting the IAI TCO and open network WO3 EC layer compared to counterpart devices with an ITO TCO or dense WO3 EC film. This can be explained by the facile carrier extraction (injection) and transport of Li ions.

Abstract Achieving high-performance p-type semiconductors has been considered one of the most challenging tasks for three-dimensional vertically integrated nanoelectronics. Although many candidates have been presented to date, the facile and scalable realization of high-mobility p-channel field-effect transistors (FETs) is still elusive. Here, we report a high-performance p-channel tellurium (Te) FET fabricated through physical vapor deposition at room temperature. A growth route involving Te deposition by sputtering, oxidation and subsequent reduction to an elemental Te film through alumina encapsulation allows the resulting p-channel FET to exhibit a high field-effect mobility of 30.9 cm2 V−1 s−1 and an I ON/OFF ratio of 5.8 × 105 with 4-inch wafer-scale integrity on a SiO2/Si substrate. Complementary metal-oxide semiconductor (CMOS) inverters using In-Ga-Zn-O and 4-nm-thick Te channels show a remarkably high gain of ~75.2 and great noise margins at small supply voltage of 3 V. We believe that this low-cost and high-performance Te layer can pave the way for future CMOS technology enabling monolithic three-dimensional integration.

This paper reports the effect of the cation composition on the electrical properties of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) where atomic layer deposition (ALD) was used to deposit an a-IGZO channel layer. The In0.38Ga0.18Zn0.44O transistors at a 200°C annealing temperature exhibited 39.4 cm2/V·s field effect mobility (µFE), −0.12 V threshold voltage (VTH), 0.40 V/decade subthreshold gate swing (SS), and >107 ION/OFF ratio, corresponding to the state-of-the-art characteristics of transistors with a sputtered IGZO channel. Further enhancement of the μFE value was observed for the devices with a higher In fraction: the In0.45Ga0.15Zn0.40O transistor had a higher μFE value of 48.3 cm2/V·s, −4.06 V VTH, 0.45 V/decade SS, and >107 ION/OFF ratio. The cation composition dependence on the performance of the a-IGZO TFTs was explained by analysing the density-of-state (DOS) distribution for the corresponding devices using the experimental independent variable (IV) and theoretical Technology Computer-aided Design (TCAD) simulation.

A flexible active-matrix organic light-emitting diode (AMOLED) display based on a poly-Si thin-film transistor (TFT) backplane is reported. The AMOLED is found to have 65 ppi resolution with 100 cd/[m.sup.2] in brightness and this is the world's first bendable AMOLED in metal foil, which can be used for various applications.

A thermally stable Ca-doped CuOx (CuCaOx) diffusion barrier to prevent the migration of Cu to amorphous InGaZnO (a-IGZO) was developed by reactive sputtering and subsequent annealing. Insertion of a 5-nm-thick CaCuOx between the Ca-dopedCu (CuCa) and a-IGZO channel films in the source/drain contact regions provided the resulting transistors with superior charge transport and lower trap density compared to the diffusion barrier-free CuCa/a-IGZO transistors. The fabricated a-IGZO transistors with the CuCa/CuCaOx stack contact exhibited a high mobility of 20.8 cm²/V ⋅ s and an Ion/off ratio of 108. Simultaneously, very stable behavior against the external positive/negate gate bias stress was observed for the a-IGZO thin-film transistors with the CuCa/CuCaOx stack contact. This was attributed to suppression of Cu-related acceptor-like traps due to the conformal formation of CuCaOx film with excellent barrier properties. [ABSTRACT FROM AUTHOR]

This paper examined the performance and bias stability of amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) with a self-aligned coplanar structure. The activation energy barrier responsible for the positive bias thermal stress (PBTS)-induced instability of the a-IGZO TFTs with low oxygen loadings can be attributed to the migration of cation interstitial defects. However, the IGZO TFTs with high oxygen loadings could not be explained by the existing defect model. The first-principle calculation indicates that the cation vacancy, such as VIn, with the hydrogen incorporation plays an important role in determining the PBTS-dependent degradation of the threshold voltage. [ABSTRACT FROM AUTHOR]

A facile route to mitigate the Fermi-level pinning between a p-type GaSb semiconductor and an Al 2O3 dielectric is proposed. Combination of the sulphurization of the GaSb surface and the subsequent rapid thermal annealing allowed for high quality GaSb/Al2O3 interfacial characteristics; the interfacial trap density value was ≤2.0 x 1012 cm-2 eV-1 in an energy range of 0.05 ≤ET -- Ev ≤0.45 eV for the PMOS capacitor via rapid thermal annealing at 575 °C. A physical rationale was given on the basis of the thermo-chemical conversion of Ga2O into Ga2O3 and the conformal elimination of Sb related elements and oxides on the GaSb surface. [ABSTRACT FROM AUTHOR]

Transition tantalum induced crystallization of amorphous zinc tin oxide (a-ZTO) was observed at low temperature annealing of 300 °C. Thin-film transistors (TFTs) with an a-ZTO channel layer exhibited a reasonable field-effect mobility of 12.4 cm2/Vs, subthreshold swing (SS) of 0.39V/decade, threshold voltage (VTH) of 1.5 V, and ION/OFF ratio of ~107. A significant improvement in the field-effect mobility (up to ~33.5 cm2/V s) was achieved for crystallized ZTO TFTs: this improvement was accomplished without compromising the SS, VTH, or ION/OFF ratio due to the presence of a highly ordered microstructure. [ABSTRACT FROM AUTHOR]

This study examined the performance and photo-bias stability of double-channel ZnSnO/InZnO (ZTO/ IZO) thin-film transistors. The field-effect mobility (μFE) and photo-bias stability of the double-channel device were improved by increasing the thickness of the front IZO film (tint) compared to the single-ZTO-channel device. A high-mobility (approximately 32.3 cm2/Vs) ZTO/IZO transistor with excellent photo-bias stability was obtained from Sn doping of the front IZO layer. First-principles calculations revealed an increase in the formation energy of O vacancy defects in the Sn-doped IZO layer compared to the IZO layer. This observation suggests that the superior photo-bias stability of the double-channel device is due to the effect of Sn doping during thermal annealing. However, these improvements were observed only when tint was less than the critical thickness. The rationale for this observation is also discussed based on the oxygen vacancy defect model. [ABSTRACT FROM AUTHOR]

This study examined the effects of hydrogen incorporation in amorphous indium gallium zinc oxide (IGZO) on the performance and photo-bias stability of the resulting thin-film transistors (TFTs). It was found that the threshold voltage of IGZO TFTs was negatively shifted without significant loss of the field-effect mobility and ION/OFF ratio with increasing hydrogen concentration, suggesting that interstitial hydrogen can act as a shallow donor. The hydrogen-doped device, however, showed more negative bias illumination stress (NBIS) instability than the undoped device, which cannot be explained by the simple shallow donor model. This NBIS-induced degradation might be associated with the increased tailing state distribution, which may stem from a hydrogen-related complex defect or compensation. [ABSTRACT FROM AUTHOR]

Thin film transistors (TFTs) were fabricated with a zinc oxide (ZnO) channel deposited by ultralow-pressure sputtering (ULPS) at a pressure less than 1.3x10-3 Pa. The field-effect mobility (μFE) and the subthreshold gate swing (SS) of the ULPS-ZnO TFTs were dramatically improved up to 8.5 cm2 /V s and 0.31 V/decade, respectively, compared to 1.6 cm2 /V s and 1.31 V/decade for the ZnO TFTs fabricated by a conventional sputtering pressure (CSP) of 6.7(10-1 Pa. The improved characteristics of the ULPS-ZnO TFTs compared to the CSP-ZnO one can be attributed to the greater densification of the ZnO semiconductor film at the lower deposition pressure. [ABSTRACT FROM AUTHOR]

The impact of a gate insulator (GI) material on the device instability of InGaZnO (IGZO) thin film transistors (TFTs) was investigated. The IGZO TFTs with SiO2 GI showed consistently better stability against the applied temperature stress and positive/negative gate bias stress than their counterparts with SiNk GI. This superior stability of the SiO2-gated device was attributed to the reduced total density of states (DOS) including the interfacial and semiconductor bulk trap densities. Based on the Meyer-Neldel rule, the total DOS energy distribution for both devices was extracted and compared, which can explain the experimental observation. [ABSTRACT FROM AUTHOR]

Thin-film transistors (TFTs) are fabricated with a tin oxide channel deposited by using ultralow pressure sputtering (ULPS). The effect of sputtering pressure on the device performance of the tin oxide TFTs was investigated. The TFTs with tin oxide channel deposited by conventional sputtering pressure did not show a promising performance. However, the saturation mobility (μsat) and the threshold voltage (Vth) of the ULPS-deposited SnOx TFTs were improved to ∼3.9 cm2/V s and ∼0.6 V, respectively. The better device performance of the ULPS-deposited SnO,. TFTs was attributed to the reduced free electron density (10°/cm3) resulting from the formation of a nanocrystalline phase. [ABSTRACT FROM AUTHOR]

The morphological and optical properties of indium tin oxide (ITO) thin films deposited by an ultralow-pressure dc magnetron sputtering (ULPS) method followed by postannealing treatment at 250°C are reported. The surface roughness of the film (Rrms.5 nm) deposited using ULPS was about 5 times lower than that of the film (Rrms: 2.7 nm) sputtered using a pressure of 6.7 X 10-1 Pa. ITO thin films with a low resistivity of 3.7 X 10-4 Ω cm were also achieved using a Continuous two-step deposition process, in which the initial layer was deposited using ULPS and then the final layer was deposited with a SP of 6.7 X 10-1 Pa, without the use of any other additional steps. Both the ULPS and continuous two-step deposition methods were found to be effective for producing ITO thin films with enhanced morphologies that make them suitable for use in display devices. [ABSTRACT FROM AUTHOR]

High-performance thin-film transistors (TFTs), in which the channel material consisted of amorphous indium-gallium-zinc oxide (a-IGZO) with a bottom gate architecture, were fabricated for array applications. It was found that the dependence of the field-effect mobility on the channel length was greatly affected by the value of the contact resistance (RC). A high contact resistance (RCW ~ 200 Ω cm) resulted in a significant drop (-22.3%) in the normalized field-effect mobility for the short channel device (10 µm), while contact-limited behavior was hardly seen for the device with a low contact resistance (RCW ~ 23 Ω cm). The difference in the channel length dependence of the field-effect mobility was comprehensively investigated based on the conduction mechanism. The fabricated n-channel a-IGZO lETs with W/L = 10/10 µm exhibited a field-effect mobility of 12.6 cm²/V s, threshold voltage of 4.7 V, on/off ratio of 108, and subthreshold gate swing of 0.56 V/decade. [ABSTRACT FROM AUTHOR]

Pt thin films of various thicknesses (30 nm ∼ 200 nm) were deposited on Si wafers with SiO2, Ti, TiO2, or IrO2 buffer layers at various temperatures (room temperature ∼ 200 °C) by a direct current magnetron sputtering process. The Pt films showed a strong (111)-preferred texture irrespective of the thickness, under-layer, and growth temperature. The authors previously reported [J-E. Lim, D-Y. Park, J.K. Jeong, G. Darlinski, H.J. Kim, and C.S. Hwang, App!. Phys. Lett. 81, 3224 (2002)] that the films were composed of three kinds of grains with slightly different (111) lattice parameters (bulklike, 1.0% and 2.1% larger). This study details the microstructural variations of the Pt films according to the variations of experimental parameters. The different deposition conditions produced slightly different crystalline structures, but the three different (111) lattice parameters were always found. Epitaxial (200) Pt films on a (200) MgO substrate and a highly (111) textured Au thin film on a SiO2/Si did not show the same splitting in the lattice parameter. The grains with 1.0% and 2.1% larger (111) lattice parameter almost disappeared after postannealing at 1000 °C. However, surface chemical binding of the Pt film before and after annealing was unchanged. Therefore, it is believed that the lattice parameter splitting in the (111) textured Pt film originated from the interfacial grains with the distorted crystal structure due probably to growth stress. [ABSTRACT FROM AUTHOR]

Bias temperature instability of metal-oxide-semiconductor field effect transistors (MOSFETs) with various concentrations of La incorporation in Hf-based dielectrics was characterized by varying the magnitude and polarity of the stress biases. Contrasting dependences of charge trapping on the magnitude of the stress biases are shown by changing the bias polarity. A model based on the distortion of asymmetric energy band diagrams and La-induced interface dipoles is suggested to explain this behaviour. Change of gate leakage currents according to La-incorporation, magnitude, and polarity of bias stresses supports the validity of the model. [ABSTRACT FROM AUTHOR]

This study examined the impact of the passivation layer on the light-enhanced bias instability of Al–Sn–Zn–In–O (AT–ZIO) thin film transistors. The suitably passivated device exhibited only a threshold voltage (Vth) shift of 0.72 V under light-illuminated negative-thermal stress conditions, whereas the device without a passivation layer suffered from a huge negative Vth shift of >11.5 V under identical conditions. The photocreated hole trapping model could not itself explain this behavior. Instead, the light-enhanced Vth instability of the unpassivated device would result mainly from the photodesorption of adsorbed oxygen ions after exposing the AT–ZIO back-surface in an ambient atmosphere. [ABSTRACT FROM AUTHOR]

We fabricated high-performance thin-film transistors (TFTs) with an amorphous-Al-Sn-Zn-In-O (a-AT-ZIO) channel deposited by cosputtering using a dual Al-Zn-O and In-Sn-O target. The fabricated AT-ZIO TFTs, which feature a bottom-gate and bottom-contact configuration, exhibited a high field-effect mobility of 31.9 cm2/V . s, an excellent subthreshold gate swing of 0.07 V/decade, and a high Ion/off ratio of > 10°, even below the process temperature of 250 °C. In addition, we demonstrated that the temperature and bias-induced stability of the bottom-gate TFT structure can significantly be improved by adopting a suitable passivation layer of atomic-layer- deposition-derived Al2O3 thin film. [ABSTRACT FROM AUTHOR]

We investigated the impact of photon irradiation on the stability of gallium-indium-zinc oxide (GIZO) thin film transistors. The application of light on the negative bias temperature stress (NBTS) accelerated the negative displacement of the threshold voltage (Vth). This phenomenon can be attributed to the trapping of the photon-induced carriers into the gate dielectric/channel interface or the gate dielectric bulk. Interestingly, the negative Vth shift under photon-enhanced NBTS condition worsened in relatively humid environments. It is suggested that moisture is a significant parameter that induces the degradation of bias-stressed GIZO transistors. [ABSTRACT FROM AUTHOR]

Effects of Gd capping of HfSiON gate dielectric on the characteristics of n metal-oxide-semiconductor field effect transistor (nMOSFET) with TaC gate electrode were investigated. MOSFETs with an in situ deposited Gd/TaC bilayer demonstrated a reduced equivalent oxide thickness, 0.9 nm, and low VTH, 0.25 V, compared with MOSFETs without Gd capping layer. Backside secondary ion mass spectroscopy revealed that Gd atoms were diffused into the high-k gate dielectric and interfacial layer between high-k dielectric and Si substrate. The dipole moment at the high-k/SiO2 interface due to Hf–O and RE–O bonds is used to explain the VTH change. [ABSTRACT FROM AUTHOR]

We compared the effect of the temperature on the device stability of Al–Zn–Sn–O (AZTO) thin film transistors (TFTs) with top gate and bottom gate architectures. While the bottom gate device without any passivation layer on the AZTO channel layer showed a large threshold voltage (Vth) shift of 1.6 V after heating it from 298 to 398 K, the naturally passivated top gate device exhibited a smaller Vth shift of 0.6 V. This different behavior is discussed based on the concept of the thermal activation energy of the subthreshold drain current. It is proposed that the suitable passivation and lower interfacial trap density for the top gate TFT are responsible for its superior temperature stability compared to the bottom gate device. [ABSTRACT FROM AUTHOR]

Thin film transistors with a channel of Zn–In–Sn–O were fabricated via a combinatorial rf sputtering method. It was found that the role of the In atoms is to enhance the mobility and to shift the threshold voltage (Vth) negatively. On the other hand, the Sn fraction is critical for improving the overall trap density including the density-of-states of the bulk channel layer and the interfacial trap density at the ZnInSnO interface. The optimized transistor was obtained at a compositional ratio of Zn:In:Sn=40:20:40, which exhibited an excellent subthreshold gate swing of 0.12 V/decade, Vth of -0.4 V, and high Ion/off ratio of >109 as well as a high field-effect mobility of 24.6 cm2/V s. [ABSTRACT FROM AUTHOR]

The local structures of amorphous In–Ga–Zn–O (InGaZnO4 and In2Ga2ZnO7) films were examined by x-ray absorption spectroscopy and fine structure analysis. The local metal-oxygen coordination in both films indicated bipyramidal GaO5, ZnO5, and trigonal InO6 clusters. Further analyses showed splitting of the Zn–O bond length suggesting distortion of the ZnO5 cluster, which evidenced the existence of localized holes in the Zn atoms. In combination with the abundance of In 5s electrons, this shows that the In–Zn hopping interactions contribute to electrical conduction. [ABSTRACT FROM AUTHOR]

We investigated the effect of the high-k TiOx (k∼40) gate dielectric on the mobility (μFE) of indium-gallium-zinc oxide (IGZO) transistors. As the thickness of the TiOx layer at the interface of the IGZO channel and SiNx gate dielectric layer increased from 2 to 8 nm, the μFE value was monotonously reduced from 9.9 to 1.8 cm2/V s. The degradation of the mobility was attributed to the Coulomb scattering mechanism rather than the phonon scattering mechanism of the high-k TiOx layer based on the behavior of the temperature-dependent mobilities for all of the IGZO transistors. [ABSTRACT FROM AUTHOR]

We proposed a homojunctioned amorphous InGaZnO (a-IGZO) thin film transistor (TFT) and compared its performance to that of a conventional structured TFT. The source/drain regions were formed in the a-IGZO channel layer using Ar and H2 plasma treatments, respectively. Hydrogen itself was found to act as a carrier of donors with H2 plasma treatment, which had effects to a depth of 50 nm. Our TFT had a field-effect mobility of 7.27 cm2/V s, an on/off ratio of 1.2×107, a threshold voltage of 0.96 V, and a subthreshold swing of 0.49 V/decade. [ABSTRACT FROM AUTHOR]

We investigated the impact of the passivation layer on the stability of indium-gallium-zinc oxide (IGZO) thin film transistors. While the device without any passivation layer showed a huge threshold voltage (Vth) shift under positive gate voltage stress, the suitably passivated device did not exhibit any Vth shift. The charge trapping model, which has been believed to be a plausible mechanism, cannot by itself explain this behavior. Instead, the Vth instability was attributed to the interaction between the exposed IGZO backsurface and oxygen and/or water in the ambient atmosphere during the gate voltage stress. [ABSTRACT FROM AUTHOR]

We investigated the feasibility of controlling the threshold voltage (Vth) by adjusting the thickness of the active layer (tactive) rather than by conventional chemical doping in indium-gallium-zinc oxide (IGZO) transistors with an inverted staggered structure. The value of Vth of the IGZO transistor was linearly modulated from -15.3±1.6 to -0.1±0.21 V by reducing tactive without any significant change in the field-effect mobility (μFE), subthreshold gate swing, or Ion/off ratio. The free electron density extracted from the relationship between tactive and Vth was 1.9×1017 cm-3, which was consistent with the value of 1.5×1017 cm-3 obtained from the C-V measurement for the 30-nm-thick IGZO films. The slight increase in the μFE with increasing tactive, which was in contradiction with the behavior of the corresponding amorphous Si transistor, was explained by the anomalous behavior of the source/drain contact resistance. [ABSTRACT FROM AUTHOR]

The effect of water exposure on amorphous indium-gallium-zinc oxide (a-IGZO) semiconductors was reported. It was found that water can diffuse in and out of the a-IGZO film, reversibly affecting the transistor properties. Two competing mechanisms depending on the thickness of the active channel were clarified. The electron donation effect caused by water adsorption dominated for the thicker a-IGZO films (>=100 nm), which was manifested in the large negative shift (>14 V) of the threshold voltage. However, in the case of the thinner a-IGZO films (<=70 nm), the dominance of the water-induced acceptorlike trap behavior was observed. The direct evidence for this behavior was that the subthreshold swing was greatly deteriorated from 0.18 V/decade (before water exposure) to 4.4 V/decade (after water exposure) for the thinnest a-IGZO films (30 nm). These results can be well explained by the screening effect of the intrinsic bulk traps of the a-IGZO semiconductor. [ABSTRACT FROM AUTHOR]

Full-color active-matrix organic light-emitting diode panels, driven by poly-Si thin-film transistors (poly-Si TFTs), were successfully fabricated on thin metal foil substrates. The p-channel poly-Si TFTs on metal foil showed a field-effect mobility of 82.9 cm²/V · s, subthreshold slope of 0.34 V/dec, threshold voltage of -1.67 V, and OFF-current of 6.6 × 10-14 A/µm. The 5.6-in panel had 160 × RGB × 350 pixels, each of which had a pixel circuit of two TFTs and one capacitor. [ABSTRACT FROM AUTHOR]

The authors attempted to grow a semi-insulating silicon carbide (SiC) epitaxial layer by in situ iron doping. The homoepitaxial growth of the iron-doped 4H-SiC layer was performed by metal-organic chemical vapor deposition using the organo-silicon precursor bis(trimethylsilylmethane) (C7H20Si2) and the metal-organic precursor t-butylferrocene (C14H17Fe). For the measurement of the resistivity of the iron-doped 4H-SiC epilayers, the authors used the on resistance of Schottky barrier diode. Based on the measurement of the on resistance, it is shown that the free carrier concentration was decreased with increasing partial pressure of t-butylferrocene. The resistivity of the iron-doped 4H-SiC epilayer was about 108 Ω cm. [ABSTRACT FROM AUTHOR]

This review gives an overview of the recent progress in vacuum-based n-type transition metal oxide (TMO) thin film transistors (TFTs). Several excellent review papers regarding metal oxide TFTs in terms of fundamental electron structure, device process and reliability have been published. In particular, the required field-effect mobility of TMO TFTs has been increasing rapidly to meet the demands of the ultra-high-resolution, large panel size and three dimensional visual effects as a megatrend of flat panel displays, such as liquid crystal displays, organic light emitting diodes and flexible displays. In this regard, the effects of the TMO composition on the performance of the resulting oxide TFTs has been reviewed, and classified into binary, ternary and quaternary composition systems. In addition, the new strategic approaches including zinc oxynitride materials, double channel structures, and composite structures have been proposed recently, and were not covered in detail in previous review papers. Special attention is given to the advanced device architecture of TMO TFTs, such as back-channel-etch and self-aligned coplanar structure, which is a key technology because of their advantages including low cost fabrication, high driving speed and unwanted visual artifact-free high quality imaging. The integration process and related issues, such as etching, post treatment, low ohmic contact and Cu interconnection, required for realizing these advanced architectures are also discussed. [ABSTRACT FROM AUTHOR]