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Low-power amplifier-discriminators based on a so-called NINO architecture have been developed with high time resolution for the readout of radiation detectors. Two different circuits were integrated in the NINO13 chip, processed in IBM 130 nm CMOS technology. The LCO version (Low Capacitance and consumption Optimization) was designed for potential use as front-end electronics in the Gigatracker of the NA62 experiment at CERN. It was developed as pixel readout for solid-state pixel detectors to permit minimum ionizing particle detection with less than 180 ps rms resolution per pixel on the output pulse, for power consumption below 300 [micro]W per pixel. The HCO version (High Capacitance Optimization) was designed with 4 mW power consumption per channel to provide timing resolution below 20 ps rms on the output pulse, for charges above 10 fC. Results presented show the potential of the LCO and HCO circuits for the precise timing readout of solid-state detectors, vacuum tubes or gas detectors, for applications in high energy physics, bio-technologies or medical imaging. Index Terms--CMOS circuits, detector instrumentation, fluorescence spectroscopy, high energy physics instrumentation, photodetectors.

This paper describes the modeling of a standard 0.25 [micro]m CMOS technology at cryogenic temperatures. In the first step of the work, the parameters of the EKV v2.6 model were extracted at different temperatures (300, 150, and 70 K). The extracted parameters were then used to optimize the performance of a room temperature designed active feedback front-end preamplifier (AFP) at 130 K. The results show that with a small adjustment of the extracted parameters it is possible to have a reasonable model at low temperatures. By optimizing the bias conditions at 130 K, a fall time down to 1.5 ns and a double pulse resolution of 6.5 ns were measured for NA60 proton beamscope. The proposed approach will also allow a low temperature design optimization for future projects, which will not be possible using only standard models provided by the foundry. Index Terms--Active feed-back, cryogenic temperatures, EKV model, front-end amplifier, transistor modeling.

Research was conducted to test whether reduced body resistance in partially-depleted silicon-on-insulator metal oxide semiconductor field-effect transistors can still promote undesirable effects. Large transistors with high transconductance were utilized to study the noise. Measurements were performed in the linear region of operation while the transistor was biased with a source-drain voltage. Results indicated the presence of an additional noise component.

The authors describe techniques to make fast, sub-nanosecond time resolution solid-state detector systems using sensors with 3D electrodes, current amplifiers, constant-fraction comparators or fast wave-form recorders, and some of the next steps to reach still faster results. [ABSTRACT FROM AUTHOR]

This paper describes the modeling of a standard 0.25 μm CMOS technology at cryogenic temperatures. In the first step of the work, the parameters of the EKV v2.6 model were extracted at different temperatures (300, 150, and 70 K). The extracted parameters were then used to optimize the performance of a room temperature designed active feedback front-end preamplifier (AFP) at 130 K. The results show that with a small adjustment of the extracted parameters it is possible to have a reasonable model at low temperatures. By optimizing the bias conditions at 130 K, a fall time down to 1.5 ns and a double pulse resolution of 6.5 ns were measured for NA60 proton beamscope. The proposed approach will also allow a low temperature design optimization for future projects, which will not be possible using only standard models provided by the foundry. [ABSTRACT FROM AUTHOR]